154 lines
3.1 KiB
ArmAsm
154 lines
3.1 KiB
ArmAsm
test_srad_1:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 0
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srad r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 0
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test_srad_1_constant:
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li r4, 1
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li r5, 0
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srad r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 0
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test_srad_2:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0
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srad r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 0
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test_srad_2_constant:
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li r4, -1
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li r5, 0
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srad r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 0
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test_srad_3:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 1
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srad r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xffffffffffffffff
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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#_ REGISTER_OUT r6 1
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test_srad_3_constant:
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li r4, -1
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li r5, 1
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srad r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xffffffffffffffff
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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#_ REGISTER_OUT r6 1
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test_srad_4:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 62
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srad r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xffffffffffffffff
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 62
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#_ REGISTER_OUT r6 1
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test_srad_4_constant:
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li r4, -1
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li r5, 62
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srad r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xffffffffffffffff
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 62
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#_ REGISTER_OUT r6 1
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test_srad_5:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 63
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srad r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xffffffffffffffff
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 63
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#_ REGISTER_OUT r6 1
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test_srad_5_constant:
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li r4, -1
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li r5, 63
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srad r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xffffffffffffffff
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 63
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#_ REGISTER_OUT r6 1
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test_srad_6:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 64
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srad r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xffffffffffffffff
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 64
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#_ REGISTER_OUT r6 1
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test_srad_6_constant:
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li r4, -1
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li r5, 64
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srad r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xffffffffffffffff
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 64
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#_ REGISTER_OUT r6 1
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test_srad_7:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 100
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srad r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xffffffffffffffff
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 100
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#_ REGISTER_OUT r6 1
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test_srad_7_constant:
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li r4, -1
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li r5, 100
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srad r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xffffffffffffffff
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 100
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#_ REGISTER_OUT r6 1
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