294 lines
12 KiB
C++
294 lines
12 KiB
C++
/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2016 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#ifndef XENIA_GPU_VULKAN_RENDER_CACHE_H_
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#define XENIA_GPU_VULKAN_RENDER_CACHE_H_
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#include "xenia/gpu/register_file.h"
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#include "xenia/gpu/shader.h"
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#include "xenia/gpu/vulkan/vulkan_shader.h"
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#include "xenia/gpu/xenos.h"
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#include "xenia/ui/vulkan/vulkan.h"
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#include "xenia/ui/vulkan/vulkan_device.h"
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namespace xe {
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namespace gpu {
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namespace vulkan {
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// TODO(benvanik): make public API?
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class CachedTileView;
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class CachedFramebuffer;
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class CachedRenderPass;
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// Uniquely identifies EDRAM tiles.
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struct TileViewKey {
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// Offset into EDRAM in 5120b tiles.
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uint16_t tile_offset;
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// Tile width of the view in base 80x16 tiles.
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uint16_t tile_width;
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// Tile height of the view in base 80x16 tiles.
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uint16_t tile_height;
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// 1 if format is ColorRenderTargetFormat, else DepthRenderTargetFormat.
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uint16_t color_or_depth : 1;
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// Either ColorRenderTargetFormat or DepthRenderTargetFormat.
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uint16_t edram_format : 15;
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};
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static_assert(sizeof(TileViewKey) == 8, "Key must be tightly packed");
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// Parsed render configuration from the current render state.
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struct RenderConfiguration {
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// Render mode (color+depth, depth-only, etc).
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xenos::ModeControl mode_control;
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// Target surface pitch, in pixels.
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uint32_t surface_pitch_px;
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// ESTIMATED target surface height, in pixels.
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uint32_t surface_height_px;
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// Surface MSAA setting.
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MsaaSamples surface_msaa;
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// Color attachments for the 4 render targets.
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struct {
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uint32_t edram_base;
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ColorRenderTargetFormat format;
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} color[4];
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// Depth/stencil attachment.
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struct {
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uint32_t edram_base;
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DepthRenderTargetFormat format;
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} depth_stencil;
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};
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// Current render state based on the register-specified configuration.
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struct RenderState {
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// Parsed configuration.
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RenderConfiguration config;
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// Render pass (to be used with pipelines/etc).
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CachedRenderPass* render_pass = nullptr;
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VkRenderPass render_pass_handle = nullptr;
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// Target framebuffer bound to the render pass.
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CachedFramebuffer* framebuffer = nullptr;
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VkFramebuffer framebuffer_handle = nullptr;
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};
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// Manages the virtualized EDRAM and the render target cache.
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//
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// On the 360 the render target is an opaque block of memory in EDRAM that's
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// only accessible via resolves. We use this to our advantage to simulate
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// something like it as best we can by having a shared backing memory with
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// a multitude of views for each tile location in EDRAM.
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//
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// This allows us to have the same base address write to the same memory
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// regardless of framebuffer format. Resolving then uses whatever format the
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// resolve requests straight from the backing memory.
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//
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// EDRAM is a beast and we only approximate it as best we can. Basically,
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// the 10MiB of EDRAM is composed of 2048 5120b tiles. Each tile is 80x16px.
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// +-----+-----+-----+---
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// |tile0|tile1|tile2|... 2048 times
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// +-----+-----+-----+---
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// Operations dealing with EDRAM deal in tile offsets, so base 0x100 is tile
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// offset 256, 256*5120=1310720b into the buffer. All rendering operations are
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// aligned to tiles so trying to draw at 256px wide will have a real width of
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// 320px by rounding up to the next tile.
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//
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// MSAA and other settings will modify the exact pixel sizes, like 4X makes
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// each tile effectively 40x8px, but they are still all 5120b. As we try to
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// emulate this we adjust our viewport when rendering to stretch pixels as
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// needed.
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//
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// The good news is that games cannot read EDRAM directly but must use a copy
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// operation to get the data out. That gives us a chance to do whatever we
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// need to (re-tile, etc) only when requested.
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//
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// To approximate the tiled EDRAM layout we use a single large chunk of memory.
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// From this memory we create many VkImages (and VkImageViews) of various
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// formats and dimensions as requested by the game. These are used as
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// attachments during rendering and as sources during copies. They are also
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// heavily aliased - lots of images will reference the same locations in the
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// underlying EDRAM buffer. The only requirement is that there are no hazards
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// with specific tiles (reading/writing the same tile through different images)
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// and otherwise it should be ok *fingers crossed*.
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//
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// One complication is the copy/resolve process itself: we need to give back
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// the data asked for in the format desired and where it goes is arbitrary
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// (any address in physical memory). If the game is good we get resolves of
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// EDRAM into fixed base addresses with scissored regions. If the game is bad
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// we are broken.
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//
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// Resolves from EDRAM result in tiled textures - that's texture tiles, not
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// EDRAM tiles. If we wanted to ensure byte-for-byte correctness we'd need to
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// then tile the images as we wrote them out. For now, we just attempt to
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// get the (X, Y) in linear space and do that. This really comes into play
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// when multiple resolves write to the same texture or memory aliased by
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// multiple textures - which is common due to predicated tiling. The examples
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// below demonstrate what this looks like, but the important thing is that
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// we are aware of partial textures and overlapping regions.
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//
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// TODO(benvanik): what, if any, barriers do we need? any transitions?
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//
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// Example with multiple render targets:
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// Two color targets of 256x256px tightly packed in EDRAM:
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// color target 0: base 0x0, pitch 320, scissor 0,0, 256x256
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// starts at tile 0, buffer offset 0
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// contains 64 tiles (320/80)*(256/16)
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// color target 1: base 0x40, pitch 320, scissor 256,0, 256x256
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// starts at tile 64 (after color target 0), buffer offset 327680b
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// contains 64 tiles
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// In EDRAM each set of 64 tiles is contiguous:
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// +------+------+ +------+------+------+
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// |ct0.0 |ct0.1 |...|ct0.63|ct1.0 |ct1.1 |...
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// +------+------+ +------+------+------+
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// To render into these, we setup two VkImages:
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// image 0: bound to buffer offset 0, 320x256x4=327680b
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// image 1: bound to buffer offset 327680b, 320x256x4=327680b
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// So when we render to them:
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// +------+-+ scissored to 256x256, actually 320x256
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// | . | | <- . appears at some untiled offset in the buffer, but
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// | | | consistent if aliased with the same format
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// +------+-+
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// In theory, this gives us proper aliasing in most cases.
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//
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// Example with horizontal predicated tiling:
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// Trying to render 1024x576 @4X MSAA, splitting into two regions
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// horizontally:
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// +----------+
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// | 1024x288 |
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// +----------+
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// | 1024x288 |
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// +----------+
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// EDRAM configured for 1056x288px with tile size 2112x567px (4X MSAA):
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// color target 0: base 0x0, pitch 1080, 26x36 tiles
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// First render (top):
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// window offset 0,0
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// scissor 0,0, 1024x288
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// First resolve (top):
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// RB_COPY_DEST_BASE 0x1F45D000
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// RB_COPY_DEST_PITCH pitch=1024, height=576
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// vertices: 0,0, 1024,0, 1024,288
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// Second render (bottom):
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// window offset 0,-288
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// scissor 0,288, 1024x288
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// Second resolve (bottom):
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// RB_COPY_DEST_BASE 0x1F57D000 (+1179648b)
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// RB_COPY_DEST_PITCH pitch=1024, height=576
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// (exactly 1024x288*4b after first resolve)
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// vertices: 0,288, 1024,288, 1024,576
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// Resolving here is easy as the textures are contiguous in memory. We can
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// snoop in the first resolve with the dest height to know the total size,
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// and in the second resolve see that it overlaps and place it in the
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// existing target.
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//
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// Example with vertical predicated tiling:
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// Trying to render 1280x720 @2X MSAA, splitting into two regions
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// vertically:
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// +-----+-----+
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// | 640 | 640 |
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// | x | x |
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// | 720 | 720 |
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// +-----+-----+
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// EDRAM configured for 640x736px with tile size 640x1472px (2X MSAA):
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// color target 0: base 0x0, pitch 640, 8x92 tiles
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// First render (left):
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// window offset 0,0
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// scissor 0,0, 640x720
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// First resolve (left):
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// RB_COPY_DEST_BASE 0x1BC6D000
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// RB_COPY_DEST_PITCH pitch=1280, height=720
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// vertices: 0,0, 640,0, 640,720
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// Second render (right):
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// window offset -640,0
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// scissor 640,0, 640x720
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// Second resolve (right):
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// RB_COPY_DEST_BASE 0x1BC81000 (+81920b)
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// RB_COPY_DEST_PITCH pitch=1280, height=720
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// vertices: 640,0, 1280,0, 1280,720
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// Resolving here is much more difficult as resolves are tiled and the right
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// half of the texture is 81920b away:
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// 81920/4bpp=20480px, /32 (texture tile size)=640px
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// We know the texture size with the first resolve and with the second we
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// must check for overlap then compute the offset (in both X and Y).
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class RenderCache {
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public:
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RenderCache(RegisterFile* register_file, ui::vulkan::VulkanDevice* device);
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~RenderCache();
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// Begins a render pass targeting the state-specified framebuffer formats.
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// The command buffer will be transitioned into the render pass phase.
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const RenderState* BeginRenderPass(VkCommandBuffer command_buffer,
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VulkanShader* vertex_shader,
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VulkanShader* pixel_shader);
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// Ends the current render pass.
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// The command buffer will be transitioned out of the render pass phase.
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void EndRenderPass();
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// Clears all cached content.
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void ClearCache();
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private:
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// Parses the current state into a configuration object.
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bool ParseConfiguration(RenderConfiguration* config);
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// Gets or creates a render pass and frame buffer for the given configuration.
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// This attempts to reuse as much as possible across render passes and
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// framebuffers.
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bool ConfigureRenderPass(RenderConfiguration* config,
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CachedRenderPass** out_render_pass,
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CachedFramebuffer** out_framebuffer);
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// Gets or creates a tile view with the given parameters.
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CachedTileView* GetTileView(const TileViewKey& view_key);
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RegisterFile* register_file_ = nullptr;
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VkDevice device_ = nullptr;
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// Entire 10MiB of EDRAM, aliased to hell by various VkImages.
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VkDeviceMemory edram_memory_ = nullptr;
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// Buffer overlayed 1:1 with edram_memory_ to allow raw access.
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VkBuffer edram_buffer_ = nullptr;
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// Cache of VkImage and VkImageView's for all of our EDRAM tilings.
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// TODO(benvanik): non-linear lookup? Should only be a small number of these.
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std::vector<CachedTileView*> cached_tile_views_;
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// Cache of render passes based on formats.
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std::vector<CachedRenderPass*> cached_render_passes_;
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// Shadows of the registers that impact the render pass we choose.
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// If the registers don't change between passes we can quickly reuse the
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// previous one.
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struct ShadowRegisters {
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uint32_t rb_modecontrol;
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uint32_t rb_surface_info;
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uint32_t rb_color_info;
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uint32_t rb_color1_info;
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uint32_t rb_color2_info;
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uint32_t rb_color3_info;
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uint32_t rb_depth_info;
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uint32_t pa_sc_window_scissor_tl;
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uint32_t pa_sc_window_scissor_br;
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ShadowRegisters() { Reset(); }
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void Reset() { std::memset(this, 0, sizeof(*this)); }
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} shadow_registers_;
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bool SetShadowRegister(uint32_t* dest, uint32_t register_name);
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// Configuration used for the current/previous Begin/End, representing the
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// current shadow register state.
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RenderState current_state_;
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// Only valid during a BeginRenderPass/EndRenderPass block.
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VkCommandBuffer current_command_buffer_ = nullptr;
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};
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} // namespace vulkan
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} // namespace gpu
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} // namespace xe
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#endif // XENIA_GPU_VULKAN_RENDER_CACHE_H_
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