086a070fa9
According to the integral promotion rules https://eel.is/c++draft/conv.prom#5.sentence-1 bit fields can be promoted to `int` if it's wide enough to store their value, and then otherwise, to `unsigned int`. Hopefully fixes Clang building (the `width_div_8` case).
354 lines
14 KiB
C++
354 lines
14 KiB
C++
/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2022 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#include "xenia/gpu/draw_extent_estimator.h"
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#include <algorithm>
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#include <cfloat>
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#include <cstdint>
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#include "xenia/base/assert.h"
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#include "xenia/base/cvar.h"
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#include "xenia/base/profiling.h"
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#include "xenia/gpu/registers.h"
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#include "xenia/gpu/ucode.h"
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#include "xenia/gpu/xenos.h"
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#include "xenia/ui/graphics_util.h"
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DEFINE_bool(
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execute_unclipped_draw_vs_on_cpu, true,
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"Execute the vertex shader for draws with clipping disabled, primarily "
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"screen-space draws (such as clears), on the CPU when possible to estimate "
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"the extent of the EDRAM involved in the draw.\n"
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"Enabling this may significantly improve GPU performance as otherwise up "
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"to the entire EDRAM may be considered used in draws without clipping, "
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"potentially resulting in spurious EDRAM range ownership transfer round "
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"trips between host render targets.\n"
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"Also, on hosts where certain render target formats have to be emulated in "
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"a lossy way (for instance, 16-bit fixed-point via 16-bit floating-point), "
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"this prevents corruption of other render targets located after the "
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"current ones in the EDRAM by lossy range ownership transfers done for "
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"those draws.",
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"GPU");
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DEFINE_bool(
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execute_unclipped_draw_vs_on_cpu_with_scissor, false,
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"Don't restrict the usage of execute_unclipped_draw_vs_on_cpu to only "
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"non-scissored draws (with the right and the bottom sides of the scissor "
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"rectangle at 8192 or beyond) even though if the scissor rectangle is "
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"present, it's usually sufficient for esimating the height of the render "
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"target.\n"
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"Enabling this may cause excessive processing of vertices on the CPU, as "
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"some games draw rectangles (for their UI, for instance) without clipping, "
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"but with a proper scissor rectangle.",
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"GPU");
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namespace xe {
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namespace gpu {
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void DrawExtentEstimator::PositionYExportSink::Export(
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ucode::ExportRegister export_register, const float* value,
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uint32_t value_mask) {
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if (export_register == ucode::ExportRegister::kVSPosition) {
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if (value_mask & 0b0010) {
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position_y_ = value[1];
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}
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if (value_mask & 0b1000) {
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position_w_ = value[3];
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}
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} else if (export_register ==
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ucode::ExportRegister::kVSPointSizeEdgeFlagKillVertex) {
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if (value_mask & 0b0001) {
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point_size_ = value[0];
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}
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if (value_mask & 0b0100) {
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vertex_kill_ = *reinterpret_cast<const uint32_t*>(&value[2]);
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}
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}
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}
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uint32_t DrawExtentEstimator::EstimateVertexMaxY(const Shader& vertex_shader) {
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SCOPE_profile_cpu_f("gpu");
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const RegisterFile& regs = register_file_;
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auto vgt_draw_initiator = regs.Get<reg::VGT_DRAW_INITIATOR>();
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if (!vgt_draw_initiator.num_indices) {
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return 0;
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}
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if (vgt_draw_initiator.source_select != xenos::SourceSelect::kDMA &&
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vgt_draw_initiator.source_select != xenos::SourceSelect::kAutoIndex) {
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// TODO(Triang3l): Support immediate indices.
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return xenos::kTexture2DCubeMaxWidthHeight;
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}
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// Not reproducing tessellation.
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if (xenos::IsMajorModeExplicit(vgt_draw_initiator.major_mode,
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vgt_draw_initiator.prim_type) &&
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regs.Get<reg::VGT_OUTPUT_PATH_CNTL>().path_select ==
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xenos::VGTOutputPath::kTessellationEnable) {
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return xenos::kTexture2DCubeMaxWidthHeight;
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}
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assert_true(vertex_shader.type() == xenos::ShaderType::kVertex);
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assert_true(vertex_shader.is_ucode_analyzed());
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if (!ShaderInterpreter::CanInterpretShader(vertex_shader)) {
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return xenos::kTexture2DCubeMaxWidthHeight;
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}
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auto vgt_dma_size = regs.Get<reg::VGT_DMA_SIZE>();
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union {
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const void* index_buffer;
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const uint16_t* index_buffer_16;
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const uint32_t* index_buffer_32;
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};
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xenos::Endian index_endian = vgt_dma_size.swap_mode;
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if (vgt_draw_initiator.source_select == xenos::SourceSelect::kDMA) {
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xenos::IndexFormat index_format = vgt_draw_initiator.index_size;
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uint32_t index_buffer_base = regs[XE_GPU_REG_VGT_DMA_BASE].u32;
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uint32_t index_buffer_read_count =
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std::min(uint32_t(vgt_draw_initiator.num_indices),
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uint32_t(vgt_dma_size.num_words));
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if (vgt_draw_initiator.index_size == xenos::IndexFormat::kInt16) {
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// Handle the index endianness to same way as the PrimitiveProcessor.
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if (index_endian == xenos::Endian::k8in32) {
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index_endian = xenos::Endian::k8in16;
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} else if (index_endian == xenos::Endian::k16in32) {
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index_endian = xenos::Endian::kNone;
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}
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index_buffer_base &= ~uint32_t(sizeof(uint16_t) - 1);
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if (trace_writer_) {
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trace_writer_->WriteMemoryRead(
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index_buffer_base, sizeof(uint16_t) * index_buffer_read_count);
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}
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} else {
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assert_true(vgt_draw_initiator.index_size == xenos::IndexFormat::kInt32);
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index_buffer_base &= ~uint32_t(sizeof(uint32_t) - 1);
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if (trace_writer_) {
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trace_writer_->WriteMemoryRead(
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index_buffer_base, sizeof(uint32_t) * index_buffer_read_count);
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}
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}
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index_buffer = memory_.TranslatePhysical(index_buffer_base);
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}
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auto pa_su_sc_mode_cntl = regs.Get<reg::PA_SU_SC_MODE_CNTL>();
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uint32_t reset_index =
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regs.Get<reg::VGT_MULTI_PRIM_IB_RESET_INDX>().reset_indx;
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uint32_t index_offset = regs.Get<reg::VGT_INDX_OFFSET>().indx_offset;
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uint32_t min_index = regs.Get<reg::VGT_MIN_VTX_INDX>().min_indx;
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uint32_t max_index = regs.Get<reg::VGT_MAX_VTX_INDX>().max_indx;
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auto pa_cl_vte_cntl = regs.Get<reg::PA_CL_VTE_CNTL>();
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float viewport_y_scale = pa_cl_vte_cntl.vport_y_scale_ena
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? regs[XE_GPU_REG_PA_CL_VPORT_YSCALE].f32
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: 1.0f;
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float viewport_y_offset = pa_cl_vte_cntl.vport_y_offset_ena
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? regs[XE_GPU_REG_PA_CL_VPORT_YOFFSET].f32
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: 0.0f;
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int32_t point_vertex_min_diameter_float = 0;
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int32_t point_vertex_max_diameter_float = 0;
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float point_constant_radius_y = 0.0f;
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if (vgt_draw_initiator.prim_type == xenos::PrimitiveType::kPointList) {
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auto pa_su_point_minmax = regs.Get<reg::PA_SU_POINT_MINMAX>();
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*reinterpret_cast<float*>(&point_vertex_min_diameter_float) =
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float(pa_su_point_minmax.min_size) * (2.0f / 16.0f);
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*reinterpret_cast<float*>(&point_vertex_max_diameter_float) =
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float(pa_su_point_minmax.max_size) * (2.0f / 16.0f);
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point_constant_radius_y =
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float(regs.Get<reg::PA_SU_POINT_SIZE>().height) * (1.0f / 16.0f);
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}
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float max_y = -FLT_MAX;
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shader_interpreter_.SetShader(vertex_shader);
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PositionYExportSink position_y_export_sink;
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shader_interpreter_.SetExportSink(&position_y_export_sink);
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for (uint32_t i = 0; i < vgt_draw_initiator.num_indices; ++i) {
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uint32_t vertex_index;
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if (vgt_draw_initiator.source_select == xenos::SourceSelect::kDMA) {
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if (i < vgt_dma_size.num_words) {
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if (vgt_draw_initiator.index_size == xenos::IndexFormat::kInt16) {
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vertex_index = index_buffer_16[i];
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} else {
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vertex_index = index_buffer_32[i];
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}
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// The Xenos only uses 24 bits of the index (reset_indx is 24-bit).
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vertex_index = xenos::GpuSwap(vertex_index, index_endian) & 0xFFFFFF;
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} else {
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vertex_index = 0;
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}
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if (pa_su_sc_mode_cntl.multi_prim_ib_ena && vertex_index == reset_index) {
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continue;
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}
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} else {
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assert_true(vgt_draw_initiator.source_select ==
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xenos::SourceSelect::kAutoIndex);
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vertex_index = i;
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}
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vertex_index =
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std::min(max_index,
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std::max(min_index, (vertex_index + index_offset) & 0xFFFFFF));
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position_y_export_sink.Reset();
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shader_interpreter_.temp_registers()[0] = float(vertex_index);
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shader_interpreter_.Execute();
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if (position_y_export_sink.vertex_kill().has_value() &&
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(position_y_export_sink.vertex_kill().value() & ~(UINT32_C(1) << 31))) {
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continue;
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}
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if (!position_y_export_sink.position_y().has_value()) {
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continue;
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}
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float vertex_y = position_y_export_sink.position_y().value();
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if (!pa_cl_vte_cntl.vtx_xy_fmt) {
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if (!position_y_export_sink.position_w().has_value()) {
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continue;
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}
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vertex_y /= position_y_export_sink.position_w().value();
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}
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vertex_y = vertex_y * viewport_y_scale + viewport_y_offset;
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if (vgt_draw_initiator.prim_type == xenos::PrimitiveType::kPointList) {
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float point_radius_y;
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if (position_y_export_sink.point_size().has_value()) {
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// Vertex-specified diameter. Clamped effectively as a signed integer in
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// the hardware, -NaN, -Infinity ... -0 to the minimum, +Infinity, +NaN
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// to the maximum.
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point_radius_y = position_y_export_sink.point_size().value();
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*reinterpret_cast<int32_t*>(&point_radius_y) = std::min(
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point_vertex_max_diameter_float,
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std::max(point_vertex_min_diameter_float,
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*reinterpret_cast<const int32_t*>(&point_radius_y)));
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point_radius_y *= 0.5f;
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} else {
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// Constant radius.
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point_radius_y = point_constant_radius_y;
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}
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vertex_y += point_radius_y;
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}
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// std::max is `a < b ? b : a`, thus in case of NaN, the first argument is
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// always returned - max_y, which is initialized to a normalized value.
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max_y = std::max(max_y, vertex_y);
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}
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shader_interpreter_.SetExportSink(nullptr);
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int32_t max_y_24p8 = ui::FloatToD3D11Fixed16p8(max_y);
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// 16p8 range is -32768 to 32767+255/256, but it's stored as uint32_t here,
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// as 24p8, so overflowing up to -8388608 to 8388608+255/256 is safe. The
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// range of the window offset plus the half-pixel offset is -16384 to 16384.5,
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// so it's safe to add both - adding it will neither move the 16p8 clamping
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// bounds -32768 and 32767+255/256 into the 0...8192 screen space range, nor
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// cause 24p8 overflow.
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if (!regs.Get<reg::PA_SU_VTX_CNTL>().pix_center) {
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max_y_24p8 += 128;
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}
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if (pa_su_sc_mode_cntl.vtx_window_offset_enable) {
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max_y_24p8 += regs.Get<reg::PA_SC_WINDOW_OFFSET>().window_y_offset * 256;
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}
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// Top-left rule - .5 exclusive without MSAA, 1. exclusive with MSAA.
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auto rb_surface_info = regs.Get<reg::RB_SURFACE_INFO>();
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return (uint32_t(std::max(int32_t(0), max_y_24p8)) +
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((rb_surface_info.msaa_samples == xenos::MsaaSamples::k1X) ? 127
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: 255)) >>
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8;
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}
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uint32_t DrawExtentEstimator::EstimateMaxY(bool try_to_estimate_vertex_max_y,
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const Shader& vertex_shader) {
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SCOPE_profile_cpu_f("gpu");
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const RegisterFile& regs = register_file_;
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auto pa_sc_window_offset = regs.Get<reg::PA_SC_WINDOW_OFFSET>();
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int32_t window_y_offset = pa_sc_window_offset.window_y_offset;
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// Scissor.
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auto pa_sc_window_scissor_br = regs.Get<reg::PA_SC_WINDOW_SCISSOR_BR>();
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int32_t scissor_bottom = int32_t(pa_sc_window_scissor_br.br_y);
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bool scissor_window_offset =
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!regs.Get<reg::PA_SC_WINDOW_SCISSOR_TL>().window_offset_disable;
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if (scissor_window_offset) {
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scissor_bottom += window_y_offset;
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}
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auto pa_sc_screen_scissor_br = regs.Get<reg::PA_SC_SCREEN_SCISSOR_BR>();
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scissor_bottom =
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std::min(scissor_bottom, int32_t(pa_sc_screen_scissor_br.br_y));
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uint32_t max_y = uint32_t(std::max(scissor_bottom, int32_t(0)));
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if (regs.Get<reg::PA_CL_CLIP_CNTL>().clip_disable) {
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// Actual extent from the vertices.
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if (try_to_estimate_vertex_max_y &&
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cvars::execute_unclipped_draw_vs_on_cpu) {
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bool estimate_vertex_max_y;
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if (cvars::execute_unclipped_draw_vs_on_cpu_with_scissor) {
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estimate_vertex_max_y = true;
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} else {
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estimate_vertex_max_y = false;
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if (scissor_bottom >= xenos::kTexture2DCubeMaxWidthHeight) {
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// Handle just the usual special 8192x8192 case in Direct3D 9 - 8192
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// may be a normal render target height (80x8192 is well within the
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// EDRAM size, for instance), no need to process the vertices on the
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// CPU in this case.
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int32_t scissor_right = int32_t(pa_sc_window_scissor_br.br_x);
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if (scissor_window_offset) {
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scissor_right += pa_sc_window_offset.window_x_offset;
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}
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scissor_right =
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std::min(scissor_right, int32_t(pa_sc_screen_scissor_br.br_x));
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if (scissor_right >= xenos::kTexture2DCubeMaxWidthHeight) {
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estimate_vertex_max_y = true;
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}
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}
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}
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if (estimate_vertex_max_y) {
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max_y = std::min(max_y, EstimateVertexMaxY(vertex_shader));
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}
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}
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} else {
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// Viewport. Though the Xenos itself doesn't have an implicit viewport
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// scissor (it's set by Direct3D 9 when a viewport is used), on hosts, it
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// usually exists and can't be disabled.
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auto pa_cl_vte_cntl = regs.Get<reg::PA_CL_VTE_CNTL>();
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float viewport_bottom = 0.0f;
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// First calculate all the integer.0 or integer.5 offsetting exactly at full
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// precision.
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if (regs.Get<reg::PA_SU_SC_MODE_CNTL>().vtx_window_offset_enable) {
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viewport_bottom += float(window_y_offset);
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}
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if (!regs.Get<reg::PA_SU_VTX_CNTL>().pix_center) {
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viewport_bottom += 0.5f;
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}
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// Then apply the floating-point viewport offset.
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if (pa_cl_vte_cntl.vport_y_offset_ena) {
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viewport_bottom += regs[XE_GPU_REG_PA_CL_VPORT_YOFFSET].f32;
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}
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viewport_bottom += pa_cl_vte_cntl.vport_y_scale_ena
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? std::abs(regs[XE_GPU_REG_PA_CL_VPORT_YSCALE].f32)
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: 1.0f;
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// Using floor, or, rather, truncation (because maxing with zero anyway)
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// similar to how viewport scissoring behaves on real AMD, Intel and Nvidia
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// GPUs on Direct3D 12 (but not WARP), also like in
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// draw_util::GetHostViewportInfo.
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// max(0.0f, viewport_bottom) to drop NaN and < 0 - max picks the first
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// argument in the !(a < b) case (always for NaN), min as float (max_y is
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// well below 2^24) to safely drop very large values.
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max_y = uint32_t(std::min(float(max_y), std::max(0.0f, viewport_bottom)));
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}
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return max_y;
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}
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} // namespace gpu
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} // namespace xe
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