287 lines
11 KiB
C++
287 lines
11 KiB
C++
/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2022 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#include "xenia/base/exception_handler.h"
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#include <signal.h>
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#include <ucontext.h>
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#include <cstdint>
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#include "xenia/base/assert.h"
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#include "xenia/base/host_thread_context.h"
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#include "xenia/base/logging.h"
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#include "xenia/base/math.h"
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#include "xenia/base/platform.h"
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namespace xe {
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bool signal_handlers_installed_ = false;
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struct sigaction original_sigill_handler_;
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struct sigaction original_sigsegv_handler_;
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// This can be as large as needed, but isn't often needed.
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// As we will be sometimes firing many exceptions we want to avoid having to
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// scan the table too much or invoke many custom handlers.
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constexpr size_t kMaxHandlerCount = 8;
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// All custom handlers, left-aligned and null terminated.
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// Executed in order.
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std::pair<ExceptionHandler::Handler, void*> handlers_[kMaxHandlerCount];
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static void ExceptionHandlerCallback(int signal_number, siginfo_t* signal_info,
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void* signal_context) {
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mcontext_t& mcontext =
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reinterpret_cast<ucontext_t*>(signal_context)->uc_mcontext;
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HostThreadContext thread_context;
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#if XE_ARCH_AMD64
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thread_context.rip = uint64_t(mcontext.gregs[REG_RIP]);
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thread_context.eflags = uint32_t(mcontext.gregs[REG_EFL]);
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// The REG_ order may be different than the register indices in the
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// instruction encoding.
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thread_context.rax = uint64_t(mcontext.gregs[REG_RAX]);
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thread_context.rcx = uint64_t(mcontext.gregs[REG_RCX]);
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thread_context.rdx = uint64_t(mcontext.gregs[REG_RDX]);
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thread_context.rbx = uint64_t(mcontext.gregs[REG_RBX]);
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thread_context.rsp = uint64_t(mcontext.gregs[REG_RSP]);
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thread_context.rbp = uint64_t(mcontext.gregs[REG_RBP]);
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thread_context.rsi = uint64_t(mcontext.gregs[REG_RSI]);
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thread_context.rdi = uint64_t(mcontext.gregs[REG_RDI]);
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thread_context.r8 = uint64_t(mcontext.gregs[REG_R8]);
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thread_context.r9 = uint64_t(mcontext.gregs[REG_R9]);
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thread_context.r10 = uint64_t(mcontext.gregs[REG_R10]);
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thread_context.r11 = uint64_t(mcontext.gregs[REG_R11]);
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thread_context.r12 = uint64_t(mcontext.gregs[REG_R12]);
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thread_context.r13 = uint64_t(mcontext.gregs[REG_R13]);
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thread_context.r14 = uint64_t(mcontext.gregs[REG_R14]);
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thread_context.r15 = uint64_t(mcontext.gregs[REG_R15]);
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std::memcpy(thread_context.xmm_registers, mcontext.fpregs->_xmm,
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sizeof(thread_context.xmm_registers));
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#elif XE_ARCH_ARM64
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std::memcpy(thread_context.x, mcontext.regs, sizeof(thread_context.x));
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thread_context.sp = mcontext.sp;
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thread_context.pc = mcontext.pc;
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thread_context.pstate = mcontext.pstate;
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struct fpsimd_context* mcontext_fpsimd = nullptr;
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struct esr_context* mcontext_esr = nullptr;
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for (struct _aarch64_ctx* mcontext_extension =
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reinterpret_cast<struct _aarch64_ctx*>(mcontext.__reserved);
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mcontext_extension->magic;
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mcontext_extension = reinterpret_cast<struct _aarch64_ctx*>(
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reinterpret_cast<uint8_t*>(mcontext_extension) +
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mcontext_extension->size)) {
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switch (mcontext_extension->magic) {
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case FPSIMD_MAGIC:
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mcontext_fpsimd =
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reinterpret_cast<struct fpsimd_context*>(mcontext_extension);
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break;
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case ESR_MAGIC:
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mcontext_esr =
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reinterpret_cast<struct esr_context*>(mcontext_extension);
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break;
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default:
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break;
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}
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}
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assert_not_null(mcontext_fpsimd);
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if (mcontext_fpsimd) {
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thread_context.fpsr = mcontext_fpsimd->fpsr;
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thread_context.fpcr = mcontext_fpsimd->fpcr;
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std::memcpy(thread_context.v, mcontext_fpsimd->vregs,
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sizeof(thread_context.v));
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}
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#endif // XE_ARCH
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Exception ex;
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switch (signal_number) {
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case SIGILL:
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ex.InitializeIllegalInstruction(&thread_context);
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break;
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case SIGSEGV: {
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Exception::AccessViolationOperation access_violation_operation;
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#if XE_ARCH_AMD64
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// x86_pf_error_code::X86_PF_WRITE
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constexpr uint64_t kX86PageFaultErrorCodeWrite = UINT64_C(1) << 1;
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access_violation_operation =
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(uint64_t(mcontext.gregs[REG_ERR]) & kX86PageFaultErrorCodeWrite)
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? Exception::AccessViolationOperation::kWrite
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: Exception::AccessViolationOperation::kRead;
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#elif XE_ARCH_ARM64
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// For a Data Abort (EC - ESR_EL1 bits 31:26 - 0b100100 from a lower
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// Exception Level, 0b100101 without a change in the Exception Level),
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// bit 6 is 0 for reading from a memory location, 1 for writing to a
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// memory location.
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if (mcontext_esr && ((mcontext_esr->esr >> 26) & 0b111110) == 0b100100) {
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access_violation_operation =
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(mcontext_esr->esr & (UINT64_C(1) << 6))
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? Exception::AccessViolationOperation::kWrite
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: Exception::AccessViolationOperation::kRead;
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} else {
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// Determine the memory access direction based on which instruction has
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// requested it.
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// esr_context may be unavailable on certain hosts (for instance, on
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// Android, it was added only in NDK r16 - which is the first NDK
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// version to support the Android API level 27, while NDK r15 doesn't
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// have esr_context in its API 26 sigcontext.h).
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// On AArch64 (unlike on AArch32), the program counter is the address of
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// the currently executing instruction.
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bool instruction_is_store;
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if (IsArm64LoadPrefetchStore(
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*reinterpret_cast<const uint32_t*>(mcontext.pc),
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instruction_is_store)) {
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access_violation_operation =
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instruction_is_store ? Exception::AccessViolationOperation::kWrite
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: Exception::AccessViolationOperation::kRead;
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} else {
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assert_always(
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"No ESR in the exception thread context, or it's not a Data "
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"Abort, and the faulting instruction is not a known load, "
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"prefetch or store instruction");
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access_violation_operation =
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Exception::AccessViolationOperation::kUnknown;
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}
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}
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#else
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access_violation_operation =
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Exception::AccessViolationOperation::kUnknown;
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#endif // XE_ARCH
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ex.InitializeAccessViolation(
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&thread_context, reinterpret_cast<uint64_t>(signal_info->si_addr),
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access_violation_operation);
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} break;
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default:
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assert_unhandled_case(signal_number);
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}
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for (size_t i = 0; i < xe::countof(handlers_) && handlers_[i].first; ++i) {
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if (handlers_[i].first(&ex, handlers_[i].second)) {
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// Exception handled.
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#if XE_ARCH_AMD64
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mcontext.gregs[REG_RIP] = greg_t(thread_context.rip);
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mcontext.gregs[REG_EFL] = greg_t(thread_context.eflags);
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uint32_t modified_register_index;
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// The order must match the order in X64Register.
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static const size_t kIntRegisterMap[] = {
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REG_RAX, REG_RCX, REG_RDX, REG_RBX, REG_RSP, REG_RBP,
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REG_RSI, REG_RDI, REG_R8, REG_R9, REG_R10, REG_R11,
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REG_R12, REG_R13, REG_R14, REG_R15,
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};
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uint16_t modified_int_registers_remaining = ex.modified_int_registers();
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while (xe::bit_scan_forward(modified_int_registers_remaining,
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&modified_register_index)) {
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modified_int_registers_remaining &=
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~(UINT16_C(1) << modified_register_index);
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mcontext.gregs[kIntRegisterMap[modified_register_index]] =
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thread_context.int_registers[modified_register_index];
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}
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uint16_t modified_xmm_registers_remaining = ex.modified_xmm_registers();
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while (xe::bit_scan_forward(modified_xmm_registers_remaining,
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&modified_register_index)) {
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modified_xmm_registers_remaining &=
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~(UINT16_C(1) << modified_register_index);
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std::memcpy(&mcontext.fpregs->_xmm[modified_register_index],
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&thread_context.xmm_registers[modified_register_index],
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sizeof(vec128_t));
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}
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#elif XE_ARCH_ARM64
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uint32_t modified_register_index;
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uint32_t modified_x_registers_remaining = ex.modified_x_registers();
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while (xe::bit_scan_forward(modified_x_registers_remaining,
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&modified_register_index)) {
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modified_x_registers_remaining &=
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~(UINT32_C(1) << modified_register_index);
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mcontext.regs[modified_register_index] =
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thread_context.x[modified_register_index];
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}
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mcontext.sp = thread_context.sp;
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mcontext.pc = thread_context.pc;
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mcontext.pstate = thread_context.pstate;
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if (mcontext_fpsimd) {
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mcontext_fpsimd->fpsr = thread_context.fpsr;
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mcontext_fpsimd->fpcr = thread_context.fpcr;
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uint32_t modified_v_registers_remaining = ex.modified_v_registers();
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while (xe::bit_scan_forward(modified_v_registers_remaining,
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&modified_register_index)) {
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modified_v_registers_remaining &=
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~(UINT32_C(1) << modified_register_index);
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std::memcpy(&mcontext_fpsimd->vregs[modified_register_index],
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&thread_context.v[modified_register_index],
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sizeof(vec128_t));
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mcontext.regs[modified_register_index] =
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thread_context.x[modified_register_index];
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}
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}
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#endif // XE_ARCH
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return;
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}
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}
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}
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void ExceptionHandler::Install(Handler fn, void* data) {
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if (!signal_handlers_installed_) {
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struct sigaction signal_handler;
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std::memset(&signal_handler, 0, sizeof(signal_handler));
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signal_handler.sa_sigaction = ExceptionHandlerCallback;
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signal_handler.sa_flags = SA_SIGINFO;
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if (sigaction(SIGILL, &signal_handler, &original_sigill_handler_) != 0) {
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assert_always("Failed to install new SIGILL handler");
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}
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if (sigaction(SIGSEGV, &signal_handler, &original_sigsegv_handler_) != 0) {
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assert_always("Failed to install new SIGSEGV handler");
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}
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signal_handlers_installed_ = true;
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}
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for (size_t i = 0; i < xe::countof(handlers_); ++i) {
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if (!handlers_[i].first) {
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handlers_[i].first = fn;
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handlers_[i].second = data;
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return;
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}
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}
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assert_always("Too many exception handlers installed");
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}
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void ExceptionHandler::Uninstall(Handler fn, void* data) {
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for (size_t i = 0; i < xe::countof(handlers_); ++i) {
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if (handlers_[i].first == fn && handlers_[i].second == data) {
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for (; i < xe::countof(handlers_) - 1; ++i) {
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handlers_[i] = handlers_[i + 1];
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}
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handlers_[i].first = nullptr;
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handlers_[i].second = nullptr;
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break;
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}
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}
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bool has_any = false;
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for (size_t i = 0; i < xe::countof(handlers_); ++i) {
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if (handlers_[i].first) {
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has_any = true;
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break;
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}
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}
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if (!has_any) {
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if (signal_handlers_installed_) {
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if (sigaction(SIGILL, &original_sigill_handler_, NULL) != 0) {
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assert_always("Failed to restore original SIGILL handler");
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}
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if (sigaction(SIGSEGV, &original_sigsegv_handler_, NULL) != 0) {
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assert_always("Failed to restore original SIGSEGV handler");
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}
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signal_handlers_installed_ = false;
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}
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}
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}
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} // namespace xe
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