521 lines
17 KiB
C++
521 lines
17 KiB
C++
/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2017 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#ifndef XENIA_GPU_REGISTERS_H_
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#define XENIA_GPU_REGISTERS_H_
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#include <cstdint>
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#include <cstdlib>
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#include "xenia/gpu/xenos.h"
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// Most registers can be found from:
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// https://github.com/UDOOboard/Kernel_Unico/blob/master/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h
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// Some registers were added on Adreno specifically and are not referenced in
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// game .pdb files and never set by games.
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namespace xe {
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namespace gpu {
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enum Register {
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#define XE_GPU_REGISTER(index, type, name) XE_GPU_REG_##name = index,
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#include "xenia/gpu/register_table.inc"
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#undef XE_GPU_REGISTER
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};
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namespace reg {
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/*******************************************************************************
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___ ___ _ _ _____ ___ ___ _
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/ __/ _ \| \| |_ _| _ \/ _ \| |
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| (_| (_) | .` | | | | / (_) | |__
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\___\___/|_|\_| |_| |_|_\\___/|____|
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*******************************************************************************/
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union COHER_STATUS_HOST {
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struct {
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uint32_t matching_contexts : 8; // +0
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uint32_t rb_copy_dest_base_ena : 1; // +8
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uint32_t dest_base_0_ena : 1; // +9
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uint32_t dest_base_1_ena : 1; // +10
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uint32_t dest_base_2_ena : 1; // +11
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uint32_t dest_base_3_ena : 1; // +12
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uint32_t dest_base_4_ena : 1; // +13
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uint32_t dest_base_5_ena : 1; // +14
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uint32_t dest_base_6_ena : 1; // +15
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uint32_t dest_base_7_ena : 1; // +16
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uint32_t : 7; // +17
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uint32_t vc_action_ena : 1; // +24
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uint32_t tc_action_ena : 1; // +25
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uint32_t pglb_action_ena : 1; // +26
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uint32_t : 4; // +27
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uint32_t status : 1; // +31
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_COHER_STATUS_HOST;
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};
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union WAIT_UNTIL {
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struct {
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uint32_t : 1; // +0
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uint32_t wait_re_vsync : 1; // +1
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uint32_t wait_fe_vsync : 1; // +2
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uint32_t wait_vsync : 1; // +3
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uint32_t wait_dsply_id0 : 1; // +4
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uint32_t wait_dsply_id1 : 1; // +5
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uint32_t wait_dsply_id2 : 1; // +6
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uint32_t : 3; // +7
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uint32_t wait_cmdfifo : 1; // +10
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uint32_t : 3; // +11
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uint32_t wait_2d_idle : 1; // +14
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uint32_t wait_3d_idle : 1; // +15
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uint32_t wait_2d_idleclean : 1; // +16
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uint32_t wait_3d_idleclean : 1; // +17
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uint32_t : 2; // +18
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uint32_t cmdfifo_entries : 4; // +20
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_WAIT_UNTIL;
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};
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/*******************************************************************************
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___ ___ ___ _ _ ___ _ _ ___ ___ ___
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/ __| __/ _ \| | | | __| \| |/ __| __| _ \
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\__ \ _| (_) | |_| | _|| .` | (__| _|| /
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|___/___\__\_\\___/|___|_|\_|\___|___|_|_\
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*******************************************************************************/
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union SQ_PROGRAM_CNTL {
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struct {
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// Note from a2xx.xml:
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// Only 0x3F worth of valid register values for VS_NUM_REG and PS_NUM_REG,
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// but high bit is set to indicate "0 registers used".
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uint32_t vs_num_reg : 8; // +0
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uint32_t ps_num_reg : 8; // +8
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uint32_t vs_resource : 1; // +16
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uint32_t ps_resource : 1; // +17
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uint32_t param_gen : 1; // +18
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uint32_t gen_index_pix : 1; // +19
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uint32_t vs_export_count : 4; // +20
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xenos::VertexShaderExportMode vs_export_mode : 3; // +24
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uint32_t ps_export_mode : 4; // +27
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uint32_t gen_index_vtx : 1; // +31
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_SQ_PROGRAM_CNTL;
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};
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union SQ_CONTEXT_MISC {
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struct {
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uint32_t inst_pred_optimize : 1; // +0
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uint32_t sc_output_screen_xy : 1; // +1
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xenos::SampleControl sc_sample_cntl : 2; // +2
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uint32_t : 4; // +4
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uint32_t param_gen_pos : 8; // +8
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uint32_t perfcounter_ref : 1; // +16
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uint32_t yeild_optimize : 1; // +17 sic
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uint32_t tx_cache_sel : 1; // +18
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_SQ_CONTEXT_MISC;
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};
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/*******************************************************************************
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__ _____ ___ _____ _____ __
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\ \ / / __| _ \_ _| __\ \/ /
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\ V /| _|| / | | | _| > <
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\_/ |___|_|_\ |_| |___/_/\_\
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___ ___ ___ _ _ ___ ___ ___ _ _ _ ___
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/ __| _ \/ _ \| | | | _ \ __| _ \ /_\ | \| | \
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| (_ | / (_) | |_| | _/ _|| / / _ \| .` | |) |
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\___|_|_\\___/ \___/|_| |___|_|_\ /_/ \_\_|\_|___/
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_____ ___ ___ ___ ___ _ _ _ _____ ___ ___
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|_ _| __/ __/ __| __| | | | /_\_ _/ _ \| _ \
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| | | _|\__ \__ \ _|| |__| |__ / _ \| || (_) | /
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|_| |___|___/___/___|____|____/_/ \_\_| \___/|_|_\
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*******************************************************************************/
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union VGT_OUTPUT_PATH_CNTL {
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struct {
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xenos::VGTOutputPath path_select : 2; // +0
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_VGT_OUTPUT_PATH_CNTL;
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};
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union VGT_HOS_CNTL {
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struct {
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xenos::TessellationMode tess_mode : 2; // +0
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_VGT_HOS_CNTL;
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};
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/*******************************************************************************
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___ ___ ___ __ __ ___ _____ _____ _____
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| _ \ _ \_ _| \/ |_ _|_ _|_ _\ \ / / __|
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| _/ /| || |\/| || | | | | | \ V /| _|
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|_| |_|_\___|_| |_|___| |_| |___| \_/ |___|
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_ ___ ___ ___ __ __ ___ _ ___ ___
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/_\ / __/ __| __| \/ | _ ) | | __| _ \
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/ _ \\__ \__ \ _|| |\/| | _ \ |__| _|| /
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/_/ \_\___/___/___|_| |_|___/____|___|_|_\
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*******************************************************************************/
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union PA_SU_POINT_MINMAX {
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struct {
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// Radius, 12.4 fixed point.
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uint32_t min_size : 16; // +0
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uint32_t max_size : 16; // +16
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_PA_SU_POINT_MINMAX;
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};
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union PA_SU_POINT_SIZE {
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struct {
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// 1/2 width or height, 12.4 fixed point.
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uint32_t height : 16; // +0
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uint32_t width : 16; // +16
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_PA_SU_POINT_SIZE;
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};
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// Setup Unit / Scanline Converter mode cntl
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union PA_SU_SC_MODE_CNTL {
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struct {
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uint32_t cull_front : 1; // +0
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uint32_t cull_back : 1; // +1
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// 0 - front is CCW, 1 - front is CW.
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uint32_t face : 1; // +2
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xenos::PolygonModeEnable poly_mode : 2; // +3
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xenos::PolygonType polymode_front_ptype : 3; // +5
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xenos::PolygonType polymode_back_ptype : 3; // +8
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uint32_t poly_offset_front_enable : 1; // +11
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uint32_t poly_offset_back_enable : 1; // +12
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uint32_t poly_offset_para_enable : 1; // +13
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uint32_t : 1; // +14
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uint32_t msaa_enable : 1; // +15
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uint32_t vtx_window_offset_enable : 1; // +16
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// LINE_STIPPLE_ENABLE was added on Adreno.
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uint32_t : 2; // +17
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uint32_t provoking_vtx_last : 1; // +19
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uint32_t persp_corr_dis : 1; // +20
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uint32_t multi_prim_ib_ena : 1; // +21
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uint32_t : 1; // +22
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uint32_t quad_order_enable : 1; // +23
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// WAIT_RB_IDLE_ALL_TRI and WAIT_RB_IDLE_FIRST_TRI_NEW_STATE were added on
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// Adreno.
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// TODO(Triang3l): Find SC_ONE_QUAD_PER_CLOCK offset.
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_PA_SU_SC_MODE_CNTL;
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};
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// Setup Unit Vertex Control
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union PA_SU_VTX_CNTL {
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struct {
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uint32_t pix_center : 1; // +0 1 = half pixel offset (OpenGL).
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uint32_t round_mode : 2; // +1
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uint32_t quant_mode : 3; // +3
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_PA_SU_VTX_CNTL;
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};
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union PA_SC_MPASS_PS_CNTL {
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struct {
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uint32_t mpass_pix_vec_per_pass : 20; // +0
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uint32_t : 11; // +20
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uint32_t mpass_ps_ena : 1; // +31
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_PA_SC_MPASS_PS_CNTL;
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};
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// Scanline converter viz query
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union PA_SC_VIZ_QUERY {
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struct {
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uint32_t viz_query_ena : 1; // +0
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uint32_t viz_query_id : 6; // +1
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uint32_t kill_pix_post_early_z : 1; // +7
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_PA_SC_VIZ_QUERY;
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};
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// Clipper clip control
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union PA_CL_CLIP_CNTL {
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struct {
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uint32_t ucp_ena_0 : 1; // +0
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uint32_t ucp_ena_1 : 1; // +1
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uint32_t ucp_ena_2 : 1; // +2
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uint32_t ucp_ena_3 : 1; // +3
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uint32_t ucp_ena_4 : 1; // +4
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uint32_t ucp_ena_5 : 1; // +5
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uint32_t : 8; // +6
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uint32_t ps_ucp_mode : 2; // +14
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uint32_t clip_disable : 1; // +16
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uint32_t ucp_cull_only_ena : 1; // +17
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uint32_t boundary_edge_flag_ena : 1; // +18
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uint32_t dx_clip_space_def : 1; // +19
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uint32_t dis_clip_err_detect : 1; // +20
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uint32_t vtx_kill_or : 1; // +21
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uint32_t xy_nan_retain : 1; // +22
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uint32_t z_nan_retain : 1; // +23
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uint32_t w_nan_retain : 1; // +24
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_PA_CL_CLIP_CNTL;
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};
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// Viewport transform engine control
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union PA_CL_VTE_CNTL {
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struct {
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uint32_t vport_x_scale_ena : 1; // +0
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uint32_t vport_x_offset_ena : 1; // +1
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uint32_t vport_y_scale_ena : 1; // +2
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uint32_t vport_y_offset_ena : 1; // +3
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uint32_t vport_z_scale_ena : 1; // +4
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uint32_t vport_z_offset_ena : 1; // +5
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uint32_t : 2; // +6
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uint32_t vtx_xy_fmt : 1; // +8
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uint32_t vtx_z_fmt : 1; // +9
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uint32_t vtx_w0_fmt : 1; // +10
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uint32_t perfcounter_ref : 1; // +11
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_PA_CL_VTE_CNTL;
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};
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union PA_SC_WINDOW_OFFSET {
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struct {
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int32_t window_x_offset : 15; // +0
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uint32_t : 1; // +15
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int32_t window_y_offset : 15; // +16
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_PA_SC_WINDOW_OFFSET;
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};
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union PA_SC_WINDOW_SCISSOR_TL {
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struct {
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uint32_t tl_x : 14; // +0
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uint32_t : 2; // +14
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uint32_t tl_y : 14; // +16
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uint32_t : 1; // +30
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uint32_t window_offset_disable : 1; // +31
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_PA_SC_WINDOW_SCISSOR_TL;
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};
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union PA_SC_WINDOW_SCISSOR_BR {
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struct {
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uint32_t br_x : 14; // +0
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uint32_t : 2; // +14
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uint32_t br_y : 14; // +16
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_PA_SC_WINDOW_SCISSOR_BR;
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};
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/*******************************************************************************
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___ ___
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| _ \ _ )
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| / _ \
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|_|_\___/
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*******************************************************************************/
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union RB_MODECONTROL {
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struct {
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xenos::ModeControl edram_mode : 3; // +0
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_RB_MODECONTROL;
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};
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union RB_SURFACE_INFO {
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struct {
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uint32_t surface_pitch : 14; // +0
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uint32_t : 2; // +14
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MsaaSamples msaa_samples : 2; // +16
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uint32_t hiz_pitch : 14; // +18
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_RB_SURFACE_INFO;
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};
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union RB_COLORCONTROL {
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struct {
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CompareFunction alpha_func : 3; // +0
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uint32_t alpha_test_enable : 1; // +3
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uint32_t alpha_to_mask_enable : 1; // +4
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// Everything in between was added on Adreno.
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uint32_t : 19; // +5
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uint32_t alpha_to_mask_offset0 : 2; // +24
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uint32_t alpha_to_mask_offset1 : 2; // +26
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uint32_t alpha_to_mask_offset2 : 2; // +28
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uint32_t alpha_to_mask_offset3 : 2; // +30
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_RB_COLORCONTROL;
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};
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union RB_COLOR_INFO {
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struct {
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uint32_t color_base : 12; // +0
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uint32_t : 4; // +12
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ColorRenderTargetFormat color_format : 4; // +16
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int32_t color_exp_bias : 6; // +20
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_RB_COLOR_INFO;
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// RB_COLOR[1-3]_INFO also use this format.
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static const Register rt_register_indices[4];
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};
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union RB_COLOR_MASK {
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struct {
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uint32_t write_red0 : 1; // +0
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uint32_t write_green0 : 1; // +1
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uint32_t write_blue0 : 1; // +2
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uint32_t write_alpha0 : 1; // +3
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uint32_t write_red1 : 1; // +4
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uint32_t write_green1 : 1; // +5
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uint32_t write_blue1 : 1; // +6
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uint32_t write_alpha1 : 1; // +7
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uint32_t write_red2 : 1; // +8
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uint32_t write_green2 : 1; // +9
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uint32_t write_blue2 : 1; // +10
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uint32_t write_alpha2 : 1; // +11
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uint32_t write_red3 : 1; // +12
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uint32_t write_green3 : 1; // +13
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uint32_t write_blue3 : 1; // +14
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uint32_t write_alpha3 : 1; // +15
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_RB_COLOR_MASK;
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};
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union RB_BLENDCONTROL {
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struct {
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BlendFactor color_srcblend : 5; // +0
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BlendOp color_comb_fcn : 3; // +5
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BlendFactor color_destblend : 5; // +8
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uint32_t : 3; // +13
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BlendFactor alpha_srcblend : 5; // +16
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BlendOp alpha_comb_fcn : 3; // +21
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BlendFactor alpha_destblend : 5; // +24
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// BLEND_FORCE_ENABLE and BLEND_FORCE were added on Adreno.
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};
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uint32_t value;
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// RB_BLENDCONTROL[0-3] use this format.
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static constexpr Register register_index = XE_GPU_REG_RB_BLENDCONTROL0;
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static const Register rt_register_indices[4];
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};
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union RB_DEPTHCONTROL {
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struct {
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uint32_t stencil_enable : 1; // +0
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uint32_t z_enable : 1; // +1
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uint32_t z_write_enable : 1; // +2
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// EARLY_Z_ENABLE was added on Adreno.
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uint32_t : 1; // +3
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CompareFunction zfunc : 3; // +4
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uint32_t backface_enable : 1; // +7
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CompareFunction stencilfunc : 3; // +8
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StencilOp stencilfail : 3; // +11
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StencilOp stencilzpass : 3; // +14
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StencilOp stencilzfail : 3; // +17
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CompareFunction stencilfunc_bf : 3; // +20
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StencilOp stencilfail_bf : 3; // +23
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StencilOp stencilzpass_bf : 3; // +26
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StencilOp stencilzfail_bf : 3; // +29
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_RB_DEPTHCONTROL;
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};
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union RB_STENCILREFMASK {
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struct {
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uint32_t stencilref : 8; // +0
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uint32_t stencilmask : 8; // +8
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uint32_t stencilwritemask : 8; // +16
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_RB_STENCILREFMASK;
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// RB_STENCILREFMASK_BF also uses this format.
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};
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union RB_DEPTH_INFO {
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struct {
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uint32_t depth_base : 12; // +0
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uint32_t : 4; // +12
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DepthRenderTargetFormat depth_format : 1; // +16
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};
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|
uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_RB_DEPTH_INFO;
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};
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union RB_COPY_CONTROL {
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struct {
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uint32_t copy_src_select : 3; // +0 Depth is 4.
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uint32_t : 1; // +3
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xenos::CopySampleSelect copy_sample_select : 3; // +4
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uint32_t : 1; // +7
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uint32_t color_clear_enable : 1; // +8
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uint32_t depth_clear_enable : 1; // +9
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uint32_t : 10; // +10
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xenos::CopyCommand copy_command : 2; // +20
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|
};
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|
uint32_t value;
|
|
static constexpr Register register_index = XE_GPU_REG_RB_COPY_CONTROL;
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|
};
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|
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union RB_COPY_DEST_INFO {
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struct {
|
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Endian128 copy_dest_endian : 3; // +0
|
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uint32_t copy_dest_array : 1; // +3
|
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uint32_t copy_dest_slice : 3; // +4
|
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ColorFormat copy_dest_format : 6; // +7
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uint32_t copy_dest_number : 3; // +13
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int32_t copy_dest_exp_bias : 6; // +16
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uint32_t : 2; // +22
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uint32_t copy_dest_swap : 1; // +24
|
|
};
|
|
uint32_t value;
|
|
static constexpr Register register_index = XE_GPU_REG_RB_COPY_DEST_INFO;
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|
};
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|
|
|
union RB_COPY_DEST_PITCH {
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|
struct {
|
|
uint32_t copy_dest_pitch : 14; // +0
|
|
uint32_t : 2; // +14
|
|
uint32_t copy_dest_height : 14; // +16
|
|
};
|
|
uint32_t value;
|
|
static constexpr Register register_index = XE_GPU_REG_RB_COPY_DEST_PITCH;
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|
};
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} // namespace reg
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} // namespace gpu
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} // namespace xe
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#endif // XENIA_GPU_REGISTERS_H_
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