f31869092c
add split_map class for mapping keys to values in a way that optimizes for frequent searches and infrequent insertions/removals remove jump table implementation of GetColorRenderTargetFormatComponentCount, it was appearing relatively high in profiles. instead pack the component counts into a single 32 bit word, which is indexed by shifting Add cvar to align all basic blocks to a boundary Add mmio aware load paths liberally apply XE_RESTRICT in ringbuffer related code Removed the IS_TRUE and IS_FALSE opcodes, they were pointless duplicates of COMPARE_EQ/COMPARE_NE and i want to simplify our set of opcodes for future backends More work on LVSR/LVSL/STVR/STVL opcodes Optimized X64 translated code emission, now only compute instrkey once Add code for pre-computing integer division magic numbers Optimized GetHostViewportInfo a little Move args for GetHostViewportInfo into a class, cache the result and compare for future queries. moved GetHostViewportInfo far lower on the profile Add (currently not functional, and very racy) asynchronous memcpy code. will improve it and actually use it in future commits. Add non-temporal memcpy function for huge page-aligned allocations. Used for copying to shared memory/readback hoist are_accumulated_render_targets_valid_ check out of loop in render_target_cache already bound check. Add stosb/movsb code for small constant memcpys/memsets that arent worth the overhead of memcpy/memset
56 lines
1.7 KiB
C++
56 lines
1.7 KiB
C++
/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2014 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#ifndef XENIA_CPU_BACKEND_X64_X64_SEQUENCES_H_
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#define XENIA_CPU_BACKEND_X64_X64_SEQUENCES_H_
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#include "xenia/base/logging.h"
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#include "xenia/cpu/hir/instr.h"
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#include <unordered_map>
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#define assert_impossible_sequence(name) \
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assert_always("impossible sequence hit" #name); \
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XELOGE("impossible sequence hit: {}", #name)
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namespace xe {
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namespace cpu {
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namespace backend {
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namespace x64 {
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class X64Emitter;
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typedef bool (*SequenceSelectFn)(X64Emitter&, const hir::Instr*, uint32_t ikey);
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extern std::unordered_map<uint32_t, SequenceSelectFn> sequence_table;
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template <typename T>
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bool Register() {
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sequence_table.insert({T::head_key(), T::Select});
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return true;
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}
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template <typename T, typename Tn, typename... Ts>
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static bool Register() {
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bool b = true;
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b = b && Register<T>(); // Call the above function
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b = b && Register<Tn, Ts...>(); // Call ourself again (recursively)
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return b;
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}
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#define EMITTER_OPCODE_TABLE(name, ...) \
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const auto X64_INSTR_##name = Register<__VA_ARGS__>();
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bool SelectSequence(X64Emitter* e, const hir::Instr* i,
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const hir::Instr** new_tail);
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} // namespace x64
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} // namespace backend
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} // namespace cpu
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} // namespace xe
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#endif // XENIA_CPU_BACKEND_X64_X64_SEQUENCES_H_
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