714 lines
25 KiB
C++
714 lines
25 KiB
C++
/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2015 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#include "xenia/gpu/packet_disassembler.h"
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#include "xenia/gpu/xenos.h"
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namespace xe {
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namespace gpu {
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using namespace xe::gpu::xenos;
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PacketCategory PacketDisassembler::GetPacketCategory(const uint8_t* base_ptr) {
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const uint32_t packet = xe::load_and_swap<uint32_t>(base_ptr);
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const uint32_t packet_type = packet >> 30;
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switch (packet_type) {
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case 0x00:
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case 0x01:
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case 0x02: {
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return PacketCategory::kGeneric;
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}
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case 0x03: {
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uint32_t opcode = (packet >> 8) & 0x7F;
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switch (opcode) {
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case PM4_DRAW_INDX:
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case PM4_DRAW_INDX_2:
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return PacketCategory::kDraw;
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case PM4_XE_SWAP:
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return PacketCategory::kSwap;
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default:
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return PacketCategory::kGeneric;
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}
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}
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default: {
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assert_unhandled_case(packet_type);
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return PacketCategory::kGeneric;
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}
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}
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}
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bool PacketDisassembler::DisasmPacketType0(const uint8_t* base_ptr,
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uint32_t packet,
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PacketInfo* out_info) {
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static constexpr PacketTypeInfo type_0_info = {PacketCategory::kGeneric,
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"PM4_TYPE0"};
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out_info->type_info = &type_0_info;
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uint32_t count = ((packet >> 16) & 0x3FFF) + 1;
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out_info->count = 1 + count;
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auto ptr = base_ptr + 4;
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uint32_t base_index = (packet & 0x7FFF);
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uint32_t write_one_reg = (packet >> 15) & 0x1;
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out_info->actions.reserve(count);
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for (uint32_t m = 0; m < count; m++) {
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uint32_t reg_data = xe::load_and_swap<uint32_t>(ptr);
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uint32_t target_index = write_one_reg ? base_index : base_index + m;
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out_info->actions.emplace_back(
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PacketAction::RegisterWrite(target_index, reg_data));
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ptr += 4;
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}
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return true;
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}
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bool PacketDisassembler::DisasmPacketType1(const uint8_t* base_ptr,
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uint32_t packet,
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PacketInfo* out_info) {
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static constexpr PacketTypeInfo type_1_info = {PacketCategory::kGeneric,
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"PM4_TYPE1"};
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out_info->type_info = &type_1_info;
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out_info->count = 1 + 2;
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auto ptr = base_ptr + 4;
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out_info->actions.reserve(2);
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uint32_t reg_index_1 = packet & 0x7FF;
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uint32_t reg_index_2 = (packet >> 11) & 0x7FF;
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uint32_t reg_data_1 = xe::load_and_swap<uint32_t>(ptr);
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uint32_t reg_data_2 = xe::load_and_swap<uint32_t>(ptr + 4);
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out_info->actions.emplace_back(
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PacketAction::RegisterWrite(reg_index_1, reg_data_1));
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out_info->actions.emplace_back(
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PacketAction::RegisterWrite(reg_index_2, reg_data_2));
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return true;
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}
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bool PacketDisassembler::DisasmPacketType2(const uint8_t* base_ptr,
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uint32_t packet,
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PacketInfo* out_info) {
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static constexpr PacketTypeInfo type_2_info = {PacketCategory::kGeneric,
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"PM4_TYPE2"};
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out_info->type_info = &type_2_info;
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out_info->count = 1;
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return true;
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}
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bool PacketDisassembler::DisasmPacketType3(const uint8_t* base_ptr,
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uint32_t packet,
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PacketInfo* out_info) {
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static constexpr PacketTypeInfo type_3_unknown_info = {
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PacketCategory::kGeneric, "PM4_TYPE3_UNKNOWN"};
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out_info->type_info = &type_3_unknown_info;
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uint32_t opcode = (packet >> 8) & 0x7F;
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uint32_t count = ((packet >> 16) & 0x3FFF) + 1;
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out_info->count = 1 + count;
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auto ptr = base_ptr + 4;
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if (packet & 1) {
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out_info->predicated = true;
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}
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using Type = PacketAction::Type;
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bool result = true;
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auto& out_actions = out_info->actions;
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out_actions.reserve(1);
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switch (opcode) {
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case PM4_ME_INIT: {
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// initialize CP's micro-engine
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static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
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"PM4_ME_INIT"};
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out_actions.emplace_back(PacketAction::MeInit((uint32_t*)ptr, count));
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out_info->type_info = &op_info;
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break;
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}
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case PM4_NOP: {
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// skip N 32-bit words to get to the next packet
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// No-op, ignore some data.
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static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
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"PM4_NOP"};
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out_info->type_info = &op_info;
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break;
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}
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case PM4_INTERRUPT: {
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// generate interrupt from the command stream
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static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
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"PM4_INTERRUPT"};
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out_info->type_info = &op_info;
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PacketAction intaction;
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intaction.type = Type::kGenInterrupt;
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intaction.gen_interrupt.cpu_mask = xe::load_and_swap<uint32_t>(ptr + 0);
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out_actions.emplace_back(std::move(intaction));
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break;
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}
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case PM4_XE_SWAP: {
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// Xenia-specific VdSwap hook.
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// VdSwap will post this to tell us we need to swap the screen/fire an
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// interrupt.
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// 63 words here, but only the first has any data.
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static constexpr PacketTypeInfo op_info = {PacketCategory::kSwap,
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"PM4_XE_SWAP"};
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out_info->type_info = &op_info;
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PacketAction xsa;
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xsa.type = Type::kXeSwap;
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xsa.xe_swap.frontbuffer_ptr = xe::load_and_swap<uint32_t>(ptr + 0);
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out_actions.emplace_back(std::move(xsa));
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break;
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}
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case PM4_INDIRECT_BUFFER:
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case PM4_INDIRECT_BUFFER_PFD: {
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// indirect buffer dispatch
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static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
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"PM4_INDIRECT_BUFFER"};
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out_info->type_info = &op_info;
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PacketAction iba;
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iba.type = Type::kIndirBuffer;
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iba.indir_buffer.list_ptr = xe::load_and_swap<uint32_t>(ptr);
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iba.indir_buffer.list_length = xe::load_and_swap<uint32_t>(ptr + 4);
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out_actions.emplace_back(std::move(iba));
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break;
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}
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case PM4_WAIT_REG_MEM: {
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// wait until a register or memory location is a specific value
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static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
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"PM4_WAIT_REG_MEM"};
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out_info->type_info = &op_info;
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PacketAction wait_action;
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wait_action.type = PacketAction::Type::kWaitRegMem;
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auto& wrm = wait_action.wait_reg_mem;
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wrm.wait_info = xe::load_and_swap<uint32_t>(ptr + 0);
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wrm.poll_reg_addr = xe::load_and_swap<uint32_t>(ptr + 4);
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wrm.ref = xe::load_and_swap<uint32_t>(ptr + 8);
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wrm.mask = xe::load_and_swap<uint32_t>(ptr + 12);
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wrm.wait = xe::load_and_swap<uint32_t>(ptr + 16);
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out_actions.emplace_back(std::move(wait_action));
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break;
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}
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case PM4_REG_RMW: {
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// register read/modify/write
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// ? (used during shader upload and edram setup)
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static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
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"PM4_REG_RMW"};
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out_info->type_info = &op_info;
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PacketAction rmw_action;
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rmw_action.type = PacketAction::Type::kRegRmw;
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auto& rmw = rmw_action.reg_rmw;
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uint32_t rmw_info = xe::load_and_swap<uint32_t>(ptr + 0);
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rmw.rmw_info = rmw_info;
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rmw.and_mask = xe::load_and_swap<uint32_t>(ptr + 4);
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rmw.or_mask = xe::load_and_swap<uint32_t>(ptr + 8);
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out_actions.emplace_back(std::move(rmw_action));
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break;
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}
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case PM4_COND_WRITE: {
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// conditional write to memory or register
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static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
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"PM4_COND_WRITE"};
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out_info->type_info = &op_info;
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PacketAction cwr_action;
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cwr_action.type = PacketAction::Type::kCondWrite;
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auto& cwr = cwr_action.cond_write;
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cwr.wait_info = xe::load_and_swap<uint32_t>(ptr + 0);
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cwr.poll_reg_addr = xe::load_and_swap<uint32_t>(ptr + 4);
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cwr.ref = xe::load_and_swap<uint32_t>(ptr + 8);
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cwr.mask = xe::load_and_swap<uint32_t>(ptr + 12);
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cwr.write_reg_addr = xe::load_and_swap<uint32_t>(ptr + 16);
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cwr.write_data = xe::load_and_swap<uint32_t>(ptr + 20);
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out_actions.emplace_back(std::move(cwr_action));
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break;
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}
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case PM4_EVENT_WRITE: {
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// generate an event that creates a write to memory when completed
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static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
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"PM4_EVENT_WRITE"};
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out_info->type_info = &op_info;
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PacketAction evw_action;
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evw_action.type = Type::kEventWrite;
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evw_action.event_write.initiator = xe::load_and_swap<uint32_t>(ptr + 0);
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out_actions.emplace_back(std::move(evw_action));
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break;
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}
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case PM4_EVENT_WRITE_SHD: {
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// generate a VS|PS_done event
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static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
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"PM4_EVENT_WRITE_SHD"};
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out_info->type_info = &op_info;
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PacketAction evws_action;
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evws_action.type = Type::kEventWriteSHD;
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auto& evws = evws_action.event_write_shd;
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evws.initiator = xe::load_and_swap<uint32_t>(ptr + 0);
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evws.address = xe::load_and_swap<uint32_t>(ptr + 4);
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evws.value = xe::load_and_swap<uint32_t>(ptr + 8);
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out_actions.emplace_back(std::move(evws_action));
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break;
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}
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case PM4_EVENT_WRITE_EXT: {
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// generate a screen extent event
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static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
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"PM4_EVENT_WRITE_EXT"};
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out_info->type_info = &op_info;
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PacketAction eve_action;
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eve_action.type = Type::kEventWriteExt;
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auto& eve = eve_action.event_write_ext;
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uint32_t unk0 = xe::load_and_swap<uint32_t>(ptr + 0);
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uint32_t unk1 = xe::load_and_swap<uint32_t>(ptr + 4);
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eve.unk0 = unk0;
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eve.unk1 = unk1;
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out_actions.emplace_back(std::move(eve_action));
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break;
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}
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case PM4_DRAW_INDX: {
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// initiate fetch of index buffer and draw
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// dword0 = viz query info
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static constexpr PacketTypeInfo op_info = {PacketCategory::kDraw,
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"PM4_DRAW_INDX"};
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out_info->type_info = &op_info;
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uint32_t dword0 = xe::load_and_swap<uint32_t>(ptr + 0);
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uint32_t dword1 = xe::load_and_swap<uint32_t>(ptr + 4);
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uint32_t index_count = dword1 >> 16;
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auto prim_type = static_cast<xenos::PrimitiveType>(dword1 & 0x3F);
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uint32_t src_sel = (dword1 >> 6) & 0x3;
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PacketAction di_action;
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di_action.type = Type::kDrawIndx;
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auto& di = di_action.draw_indx;
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di.dword0 = dword0;
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di.dword1 = dword1;
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di.index_count = index_count;
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di.prim_type = prim_type;
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di.src_sel = src_sel;
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if (src_sel == 0x0) {
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// Indexed draw.
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uint32_t guest_base = xe::load_and_swap<uint32_t>(ptr + 8);
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uint32_t index_size = xe::load_and_swap<uint32_t>(ptr + 12);
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auto endianness = static_cast<xenos::Endian>(index_size >> 30);
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index_size &= 0x00FFFFFF;
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bool index_32bit = (dword1 >> 11) & 0x1;
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index_size *= index_32bit ? 4 : 2;
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di.index_size = index_size;
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di.guest_base = guest_base;
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di.endianness = endianness;
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} else if (src_sel == 0x2) {
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// Auto draw.
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} else {
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// Unknown source select.
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assert_always();
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}
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out_actions.emplace_back(std::move(di_action));
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break;
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}
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case PM4_DRAW_INDX_2: {
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// draw using supplied indices in packet
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static constexpr PacketTypeInfo op_info = {PacketCategory::kDraw,
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"PM4_DRAW_INDX_2"};
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out_info->type_info = &op_info;
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uint32_t dword0 = xe::load_and_swap<uint32_t>(ptr + 0);
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uint32_t index_count = dword0 >> 16;
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auto prim_type = static_cast<xenos::PrimitiveType>(dword0 & 0x3F);
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uint32_t src_sel = (dword0 >> 6) & 0x3;
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assert_true(src_sel == 0x2); // 'SrcSel=AutoIndex'
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bool index_32bit = (dword0 >> 11) & 0x1;
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uint32_t indices_size = index_count * (index_32bit ? 4 : 2);
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auto index_ptr = ptr + 4;
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PacketAction di2_action;
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di2_action.type = Type::kDrawIndx2;
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di2_action.words.reserve(index_count);
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auto& di2 = di2_action.draw_indx2;
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di2.dword0 = dword0;
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di2.index_count = index_count;
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di2.indices_size = indices_size;
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di2.prim_type = prim_type;
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di2.src_sel = src_sel;
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if (index_32bit) {
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di2_action.InjectBeWords((uint32_t*)index_ptr, index_count);
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} else {
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di2_action.InjectBeHalfwordsAsWords((uint16_t*)index_ptr, index_count);
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}
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out_actions.emplace_back(std::move(di2_action));
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break;
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}
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case PM4_SET_CONSTANT: {
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// load constant into chip and to memory
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// PM4_REG(reg) ((0x4 << 16) | (GSL_HAL_SUBBLOCK_OFFSET(reg)))
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// reg - 0x2000
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static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
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"PM4_SET_CONSTANT"};
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out_info->type_info = &op_info;
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uint32_t offset_type = xe::load_and_swap<uint32_t>(ptr + 0);
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uint32_t index = offset_type & 0x7FF;
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uint32_t type = (offset_type >> 16) & 0xFF;
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switch (type) {
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case 0: // ALU
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index += 0x4000;
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break;
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case 1: // FETCH
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index += 0x4800;
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break;
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case 2: // BOOL
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index += 0x4900;
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break;
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case 3: // LOOP
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index += 0x4908;
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break;
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case 4: // REGISTERS
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index += 0x2000;
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break;
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default:
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assert_always();
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result = false;
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break;
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}
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out_actions.reserve(count - 1);
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for (uint32_t n = 0; n < count - 1; n++, index++) {
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uint32_t data = xe::load_and_swap<uint32_t>(ptr + 4 + n * 4);
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out_actions.emplace_back(PacketAction::RegisterWrite(index, data));
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}
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break;
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}
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case PM4_SET_CONSTANT2: {
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static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
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"PM4_SET_CONSTANT2"};
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out_info->type_info = &op_info;
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uint32_t offset_type = xe::load_and_swap<uint32_t>(ptr + 0);
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uint32_t index = offset_type & 0xFFFF;
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out_actions.reserve(count - 1);
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for (uint32_t n = 0; n < count - 1; n++, index++) {
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uint32_t data = xe::load_and_swap<uint32_t>(ptr + 4 + n * 4);
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out_actions.emplace_back(PacketAction::RegisterWrite(index, data));
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}
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return true;
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break;
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}
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case PM4_LOAD_ALU_CONSTANT: {
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// load constants from memory
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static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
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"PM4_LOAD_ALU_CONSTANT"};
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out_info->type_info = &op_info;
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uint32_t address = xe::load_and_swap<uint32_t>(ptr + 0);
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address &= 0x3FFFFFFF;
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uint32_t offset_type = xe::load_and_swap<uint32_t>(ptr + 4);
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uint32_t index = offset_type & 0x7FF;
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uint32_t size_dwords = xe::load_and_swap<uint32_t>(ptr + 8);
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size_dwords &= 0xFFF;
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uint32_t type = (offset_type >> 16) & 0xFF;
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switch (type) {
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case 0: // ALU
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index += 0x4000;
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break;
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case 1: // FETCH
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index += 0x4800;
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break;
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case 2: // BOOL
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index += 0x4900;
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break;
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case 3: // LOOP
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index += 0x4908;
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break;
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case 4: // REGISTERS
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index += 0x2000;
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break;
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default:
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assert_always();
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return true;
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}
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out_actions.reserve(size_dwords);
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for (uint32_t n = 0; n < size_dwords; n++, index++) {
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// Hrm, ?
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// xe::load_and_swap<uint32_t>(membase_ + GpuToCpu(address + n * 4));
|
|
uint32_t data = 0xDEADBEEF;
|
|
out_actions.emplace_back(PacketAction::RegisterWrite(index, data));
|
|
}
|
|
break;
|
|
}
|
|
case PM4_SET_SHADER_CONSTANTS: {
|
|
static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
|
|
"PM4_SET_SHADER_CONSTANTS"};
|
|
out_info->type_info = &op_info;
|
|
uint32_t offset_type = xe::load_and_swap<uint32_t>(ptr + 0);
|
|
uint32_t index = offset_type & 0xFFFF;
|
|
|
|
out_actions.reserve(count - 1);
|
|
|
|
for (uint32_t n = 0; n < count - 1; n++, index++) {
|
|
uint32_t data = xe::load_and_swap<uint32_t>(ptr + 4 + n * 4);
|
|
out_actions.emplace_back(PacketAction::RegisterWrite(index, data));
|
|
}
|
|
return true;
|
|
}
|
|
case PM4_IM_LOAD: {
|
|
// load sequencer instruction memory (pointer-based)
|
|
static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
|
|
"PM4_IM_LOAD"};
|
|
out_info->type_info = &op_info;
|
|
uint32_t addr_type = xe::load_and_swap<uint32_t>(ptr + 0);
|
|
auto shader_type = static_cast<xenos::ShaderType>(addr_type & 0x3);
|
|
uint32_t addr = addr_type & ~0x3;
|
|
uint32_t start_size = xe::load_and_swap<uint32_t>(ptr + 4);
|
|
uint32_t start = start_size >> 16;
|
|
uint32_t size_dwords = start_size & 0xFFFF; // dwords
|
|
|
|
PacketAction iml_action;
|
|
iml_action.type = Type::kImLoad;
|
|
auto& iml = iml_action.im_load;
|
|
iml.addr = addr;
|
|
iml.shader_type = shader_type;
|
|
iml.size_dwords = size_dwords;
|
|
iml.start = start;
|
|
|
|
out_actions.emplace_back(std::move(iml_action));
|
|
|
|
assert_true(start == 0);
|
|
break;
|
|
}
|
|
case PM4_IM_LOAD_IMMEDIATE: {
|
|
// load sequencer instruction memory (code embedded in packet)
|
|
static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
|
|
"PM4_IM_LOAD_IMMEDIATE"};
|
|
out_info->type_info = &op_info;
|
|
uint32_t dword0 = xe::load_and_swap<uint32_t>(ptr + 0);
|
|
uint32_t dword1 = xe::load_and_swap<uint32_t>(ptr + 4);
|
|
auto shader_type = static_cast<xenos::ShaderType>(dword0);
|
|
uint32_t start_size = dword1;
|
|
uint32_t start = start_size >> 16;
|
|
uint32_t size_dwords = start_size & 0xFFFF; // dwords
|
|
|
|
PacketAction imi_action;
|
|
imi_action.type = Type::kImLoadImmediate;
|
|
imi_action.words.reserve(size_dwords);
|
|
auto& imi = imi_action.im_load_imm;
|
|
imi.shader_type = shader_type;
|
|
imi.size_dwords = size_dwords;
|
|
imi.start = start;
|
|
|
|
imi_action.InjectBeWords(reinterpret_cast<const uint32_t*>(ptr + 8),
|
|
size_dwords);
|
|
|
|
out_actions.emplace_back(std::move(imi_action));
|
|
|
|
assert_true(start == 0);
|
|
break;
|
|
}
|
|
case PM4_INVALIDATE_STATE: {
|
|
// selective invalidation of state pointers
|
|
static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
|
|
"PM4_INVALIDATE_STATE"};
|
|
out_info->type_info = &op_info;
|
|
uint32_t mask = xe::load_and_swap<uint32_t>(ptr + 0);
|
|
|
|
PacketAction inv_action;
|
|
inv_action.type = Type::kInvalidateState;
|
|
inv_action.invalidate_state.state_mask = mask;
|
|
|
|
out_actions.emplace_back(std::move(inv_action));
|
|
break;
|
|
}
|
|
case PM4_SET_BIN_MASK_LO: {
|
|
static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
|
|
"PM4_SET_BIN_MASK_LO"};
|
|
out_info->type_info = &op_info;
|
|
uint32_t value = xe::load_and_swap<uint32_t>(ptr);
|
|
// bin_mask_ = (bin_mask_ & 0xFFFFFFFF00000000ull) | value;
|
|
|
|
PacketAction action;
|
|
action.type = Type::kSetBinMaskLo;
|
|
action.lohi_op.value = value;
|
|
out_actions.emplace_back(std::move(action));
|
|
|
|
break;
|
|
}
|
|
case PM4_SET_BIN_MASK_HI: {
|
|
static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
|
|
"PM4_SET_BIN_MASK_HI"};
|
|
out_info->type_info = &op_info;
|
|
uint32_t value = xe::load_and_swap<uint32_t>(ptr);
|
|
|
|
PacketAction action;
|
|
action.type = Type::kSetBinMaskHi;
|
|
action.lohi_op.value = value;
|
|
out_actions.emplace_back(std::move(action));
|
|
break;
|
|
}
|
|
case PM4_SET_BIN_SELECT_LO: {
|
|
static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
|
|
"PM4_SET_BIN_SELECT_LO"};
|
|
out_info->type_info = &op_info;
|
|
uint32_t value = xe::load_and_swap<uint32_t>(ptr);
|
|
PacketAction action;
|
|
action.type = Type::kSetBinSelectLo;
|
|
action.lohi_op.value = value;
|
|
out_actions.emplace_back(std::move(action));
|
|
|
|
break;
|
|
}
|
|
case PM4_SET_BIN_SELECT_HI: {
|
|
static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
|
|
"PM4_SET_BIN_SELECT_HI"};
|
|
out_info->type_info = &op_info;
|
|
uint32_t value = xe::load_and_swap<uint32_t>(ptr);
|
|
|
|
PacketAction action;
|
|
action.type = Type::kSetBinSelectHi;
|
|
action.lohi_op.value = value;
|
|
out_actions.emplace_back(std::move(action));
|
|
break;
|
|
}
|
|
case PM4_CONTEXT_UPDATE: {
|
|
uint32_t value = xe::load_and_swap<uint32_t>(ptr);
|
|
PacketAction ctxu;
|
|
ctxu.type = Type::kContextUpdate;
|
|
ctxu.context_update.maybe_unused = value;
|
|
out_actions.emplace_back(std::move(ctxu));
|
|
break;
|
|
}
|
|
case PM4_WAIT_FOR_IDLE: {
|
|
uint32_t value = xe::load_and_swap<uint32_t>(ptr);
|
|
PacketAction wfi;
|
|
wfi.type = Type::kWaitForIdle;
|
|
wfi.wait_for_idle.probably_unused = value;
|
|
out_actions.emplace_back(std::move(wfi));
|
|
break;
|
|
}
|
|
|
|
case PM4_VIZ_QUERY: {
|
|
uint32_t value = xe::load_and_swap<uint32_t>(ptr);
|
|
|
|
PacketAction vzq;
|
|
vzq.type = Type::kVizQuery;
|
|
vzq.vizquery.dword0 = value;
|
|
vzq.vizquery.id = value & 0x3F;
|
|
vzq.vizquery.end = !!(value & 0x100);
|
|
out_actions.emplace_back(std::move(vzq));
|
|
break;
|
|
}
|
|
case PM4_EVENT_WRITE_ZPD: {
|
|
uint32_t value = xe::load_and_swap<uint32_t>(ptr);
|
|
|
|
PacketAction evz;
|
|
evz.type = Type::kEventWriteZPD;
|
|
evz.event_write_zpd.initiator = value;
|
|
out_actions.emplace_back(std::move(evz));
|
|
break;
|
|
}
|
|
case PM4_MEM_WRITE: {
|
|
PacketAction mwr;
|
|
mwr.type = Type::kMemWrite;
|
|
mwr.words.reserve(count - 1);
|
|
|
|
uint32_t write_addr = xe::load_and_swap<uint32_t>(ptr);
|
|
auto endianness = static_cast<xenos::Endian>(write_addr & 0x3);
|
|
auto addr = write_addr & ~0x3;
|
|
|
|
mwr.mem_write.addr = addr;
|
|
mwr.mem_write.endianness = endianness;
|
|
|
|
// can't use injectbewords here, have to apply gpuswap to each element
|
|
for (uint32_t i = 0; i < count - 1; i++) {
|
|
uint32_t write_data = xe::load_and_swap<uint32_t>(&ptr[(i + 1) * 4]);
|
|
write_data = GpuSwap(write_data, endianness);
|
|
mwr.words.push_back(write_data);
|
|
write_addr += 4;
|
|
}
|
|
|
|
out_actions.emplace_back(std::move(mwr));
|
|
break;
|
|
}
|
|
|
|
case PM4_REG_TO_MEM: {
|
|
PacketAction r2m;
|
|
r2m.type = Type::kRegToMem;
|
|
r2m.reg2mem.reg_addr = xe::load_and_swap<uint32_t>(ptr);
|
|
uint32_t dword1 = xe::load_and_swap<uint32_t>(ptr + 4);
|
|
r2m.reg2mem.endianness = static_cast<xenos::Endian>(dword1 & 0x3);
|
|
r2m.reg2mem.mem_addr = dword1 & (~3U);
|
|
out_actions.emplace_back(std::move(r2m));
|
|
break;
|
|
}
|
|
|
|
// Ignored packets - useful if breaking on the default handler below.
|
|
case 0x50: { // 0xC0015000 usually 2 words, 0xFFFFFFFF / 0x00000000
|
|
static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
|
|
"PM4_TYPE3_0x50"};
|
|
out_info->type_info = &op_info;
|
|
break;
|
|
}
|
|
case 0x51: { // 0xC0015100 usually 2 words, 0xFFFFFFFF / 0xFFFFFFFF
|
|
static constexpr PacketTypeInfo op_info = {PacketCategory::kGeneric,
|
|
"PM4_TYPE3_0x51"};
|
|
out_info->type_info = &op_info;
|
|
break;
|
|
}
|
|
default: {
|
|
result = false;
|
|
break;
|
|
}
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
bool PacketDisassembler::DisasmPacket(const uint8_t* base_ptr,
|
|
PacketInfo* out_info) {
|
|
const uint32_t packet = xe::load_and_swap<uint32_t>(base_ptr);
|
|
const uint32_t packet_type = packet >> 30;
|
|
switch (packet_type) {
|
|
case 0x00:
|
|
return DisasmPacketType0(base_ptr, packet, out_info);
|
|
case 0x01:
|
|
return DisasmPacketType1(base_ptr, packet, out_info);
|
|
case 0x02:
|
|
return DisasmPacketType2(base_ptr, packet, out_info);
|
|
case 0x03:
|
|
return DisasmPacketType3(base_ptr, packet, out_info);
|
|
default:
|
|
assert_unhandled_case(packet_type);
|
|
return false;
|
|
}
|
|
}
|
|
|
|
} // namespace gpu
|
|
} // namespace xe
|