384 lines
5.1 KiB
ArmAsm
384 lines
5.1 KiB
ArmAsm
test_twlti_1:
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#_ REGISTER_IN r3 24
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twlti r3, 16
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blr
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#_ REGISTER_OUT r3 24
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test_twlti_1_constant:
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li r3, 24
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twlti r3, 16
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blr
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#_ REGISTER_OUT r3 24
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test_twlti_2:
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#_ REGISTER_IN r3 24
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twlti r3, 0
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blr
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#_ REGISTER_OUT r3 24
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test_twlti_2_constant:
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li r3, 24
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twlti r3, 0
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blr
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#_ REGISTER_OUT r3 24
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test_twlei_1:
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#_ REGISTER_IN r3 24
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twlei r3, 16
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blr
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#_ REGISTER_OUT r3 24
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test_twlei_1_constant:
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li r3, 24
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twlei r3, 16
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blr
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#_ REGISTER_OUT r3 24
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test_twlei_2:
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#_ REGISTER_IN r3 24
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twlei r3, 0
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blr
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#_ REGISTER_OUT r3 24
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test_twlei_2_constant:
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li r3, 24
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twlei r3, 0
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blr
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#_ REGISTER_OUT r3 24
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test_tweqi_1:
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#_ REGISTER_IN r3 0
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tweqi r3, 24
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blr
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#_ REGISTER_OUT r3 0
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test_tweqi_1_constant:
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li r3, 0
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tweqi r3, 24
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blr
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#_ REGISTER_OUT r3 0
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test_tweqi_2:
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#_ REGISTER_IN r3 24
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tweqi r3, 0
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blr
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#_ REGISTER_OUT r3 24
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test_tweqi_2_constant:
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li r3, 24
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tweqi r3, 0
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blr
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#_ REGISTER_OUT r3 24
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test_twgei_1:
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#_ REGISTER_IN r3 24
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twgei r3, 48
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blr
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#_ REGISTER_OUT r3 24
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test_twgei_1_constant:
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li r3, 24
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twgei r3, 48
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blr
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#_ REGISTER_OUT r3 24
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test_twgei_2:
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#_ REGISTER_IN r3 0
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twgei r3, 48
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blr
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#_ REGISTER_OUT r3 0
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test_twgei_2_constant:
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li r3, 0
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twgei r3, 48
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blr
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#_ REGISTER_OUT r3 0
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test_twgei_3:
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#_ REGISTER_IN r3 -1
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twgei r3, 0
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blr
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#_ REGISTER_OUT r3 -1
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test_twgei_3_constant:
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li r3, -1
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twgei r3, 0
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blr
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#_ REGISTER_OUT r3 -1
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test_twgti_1:
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#_ REGISTER_IN r3 24
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twgti r3, 48
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blr
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#_ REGISTER_OUT r3 24
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test_twgti_1_constant:
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li r3, 24
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twgti r3, 48
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blr
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#_ REGISTER_OUT r3 24
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test_twgti_2:
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#_ REGISTER_IN r3 0
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twgti r3, 48
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blr
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#_ REGISTER_OUT r3 0
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test_twgti_2_constant:
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li r3, 0
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twgti r3, 48
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blr
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#_ REGISTER_OUT r3 0
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test_twgti_3:
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#_ REGISTER_IN r3 -1
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twgti r3, 0
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blr
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#_ REGISTER_OUT r3 -1
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test_twgti_3_constant:
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li r3, -1
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twgti r3, 0
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blr
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#_ REGISTER_OUT r3 -1
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test_twnli_1:
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#_ REGISTER_IN r3 24
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twnli r3, 48
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blr
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#_ REGISTER_OUT r3 24
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test_twnli_1_constant:
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li r3, 24
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twnli r3, 48
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blr
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#_ REGISTER_OUT r3 24
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test_twnli_2:
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#_ REGISTER_IN r3 0
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twnli r3, 48
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blr
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#_ REGISTER_OUT r3 0
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test_twnli_2_constant:
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li r3, 0
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twnli r3, 48
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blr
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#_ REGISTER_OUT r3 0
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test_twnli_3:
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#_ REGISTER_IN r3 -1
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twnli r3, 0
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blr
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#_ REGISTER_OUT r3 -1
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test_twnli_3_constant:
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li r3, -1
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twnli r3, 0
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blr
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#_ REGISTER_OUT r3 -1
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test_twnei_1:
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#_ REGISTER_IN r3 24
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twnei r3, 24
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blr
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#_ REGISTER_OUT r3 24
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test_twnei_1_constant:
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li r3, 24
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twnei r3, 24
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blr
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#_ REGISTER_OUT r3 24
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test_twnei_2:
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#_ REGISTER_IN r3 0
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twnei r3, 0
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blr
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#_ REGISTER_OUT r3 0
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test_twnei_2_constant:
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li r3, 0
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twnei r3, 0
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blr
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#_ REGISTER_OUT r3 0
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test_twngi_1:
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#_ REGISTER_IN r3 24
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twngi r3, 16
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blr
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#_ REGISTER_OUT r3 24
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test_twngi_1_constant:
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li r3, 24
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twngi r3, 16
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blr
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#_ REGISTER_OUT r3 24
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test_twngi_2:
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#_ REGISTER_IN r3 24
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twngi r3, 0
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blr
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#_ REGISTER_OUT r3 24
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test_twngi_2_constant:
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li r3, 24
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twngi r3, 0
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blr
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#_ REGISTER_OUT r3 24
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test_twngi_3:
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#_ REGISTER_IN r3 0
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twngi r3, -1
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blr
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#_ REGISTER_OUT r3 0
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test_twngi_3_constant:
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li r3, 0
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twngi r3, -1
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blr
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#_ REGISTER_OUT r3 0
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test_twllti_1:
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#_ REGISTER_IN r3 24
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twllti r3, 16
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blr
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#_ REGISTER_OUT r3 24
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test_twllti_1_constant:
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li r3, 24
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twllti r3, 16
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blr
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#_ REGISTER_OUT r3 24
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test_twllti_2:
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#_ REGISTER_IN r3 24
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twllti r3, 0
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blr
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#_ REGISTER_OUT r3 24
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test_twllti_2_constant:
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li r3, 24
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twllti r3, 0
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blr
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#_ REGISTER_OUT r3 24
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test_twllei_1:
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#_ REGISTER_IN r3 24
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twllei r3, 16
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blr
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#_ REGISTER_OUT r3 24
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test_twllei_1_constant:
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li r3, 24
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twllei r3, 16
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blr
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#_ REGISTER_OUT r3 24
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test_twllei_2:
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#_ REGISTER_IN r3 24
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twllei r3, 0
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blr
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#_ REGISTER_OUT r3 24
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test_twllei_2_constant:
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li r3, 24
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twllei r3, 0
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blr
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#_ REGISTER_OUT r3 24
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test_twlgei_1:
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#_ REGISTER_IN r3 24
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twlgei r3, 48
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blr
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#_ REGISTER_OUT r3 24
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test_twlgei_1_constant:
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li r3, 24
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twlgei r3, 48
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blr
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#_ REGISTER_OUT r3 24
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test_twlgei_2:
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#_ REGISTER_IN r3 0
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twlgei r3, 48
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blr
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#_ REGISTER_OUT r3 0
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test_twlgei_2_constant:
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li r3, 0
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twlgei r3, 48
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blr
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#_ REGISTER_OUT r3 0
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test_twlgti_1:
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#_ REGISTER_IN r3 24
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twlgti r3, 48
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blr
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#_ REGISTER_OUT r3 24
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test_twlgti_1_constant:
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li r3, 24
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twlgti r3, 48
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blr
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#_ REGISTER_OUT r3 24
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test_twlgti_2:
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#_ REGISTER_IN r3 0
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twlgti r3, 48
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blr
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#_ REGISTER_OUT r3 0
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test_twlgti_2_constant:
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li r3, 0
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twlgti r3, 48
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blr
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#_ REGISTER_OUT r3 0
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test_twlnli_1:
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#_ REGISTER_IN r3 24
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twlnli r3, 48
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blr
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#_ REGISTER_OUT r3 24
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test_twlnli_1_constant:
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li r3, 24
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twlnli r3, 48
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blr
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#_ REGISTER_OUT r3 24
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test_twlnli_2:
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#_ REGISTER_IN r3 0
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twlnli r3, 48
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blr
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#_ REGISTER_OUT r3 0
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test_twlnli_2_constant:
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li r3, 0
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twlnli r3, 48
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blr
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#_ REGISTER_OUT r3 0
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test_twlngi_1:
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#_ REGISTER_IN r3 24
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twlngi r3, 16
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blr
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#_ REGISTER_OUT r3 24
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test_twlngi_1_constant:
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li r3, 24
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twlngi r3, 16
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blr
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#_ REGISTER_OUT r3 24
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test_twlngi_2:
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#_ REGISTER_IN r3 24
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twlngi r3, 0
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blr
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#_ REGISTER_OUT r3 24
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test_twlngi_2_constant:
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li r3, 24
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twlngi r3, 0
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blr
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#_ REGISTER_OUT r3 24
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