39745 lines
1.1 MiB
39745 lines
1.1 MiB
test_fmadd_1_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x0000000000000000
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fmadd f4, f1, f2, f3
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|
blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x0000000000000000
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#_ REGISTER_OUT f4 0x0000000000000000
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|
|
|
test_fmadd_1_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x0000000000000000
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fmadd. f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x0000000000000000
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#_ REGISTER_OUT f4 0x0000000000000000
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#_ REGISTER_OUT cr 0x00000000
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test_fmadd_2_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x8000000000000000
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fmadd f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x8000000000000000
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#_ REGISTER_OUT f4 0x0000000000000000
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test_fmadd_2_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x8000000000000000
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fmadd. f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x8000000000000000
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#_ REGISTER_OUT f4 0x0000000000000000
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#_ REGISTER_OUT cr 0x00000000
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test_fmadd_3_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x0000000000000001
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fmadd f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x0000000000000001
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#_ REGISTER_OUT f4 0x0000000000000001
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test_fmadd_3_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x0000000000000001
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fmadd. f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x0000000000000001
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#_ REGISTER_OUT f4 0x0000000000000001
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#_ REGISTER_OUT cr 0x00000000
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test_fmadd_4_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
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fmadd f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
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#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
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test_fmadd_4_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
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fmadd. f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
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#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
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#_ REGISTER_OUT cr 0x00000000
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test_fmadd_5_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x3FF0000000000000
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fmadd f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x3FF0000000000000
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#_ REGISTER_OUT f4 0x3FF0000000000000
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test_fmadd_5_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x3FF0000000000000
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fmadd. f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x3FF0000000000000
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#_ REGISTER_OUT f4 0x3FF0000000000000
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#_ REGISTER_OUT cr 0x00000000
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test_fmadd_6_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xBFF0000000000000
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fmadd f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xBFF0000000000000
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#_ REGISTER_OUT f4 0xBFF0000000000000
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test_fmadd_6_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xBFF0000000000000
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fmadd. f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xBFF0000000000000
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#_ REGISTER_OUT f4 0xBFF0000000000000
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#_ REGISTER_OUT cr 0x00000000
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test_fmadd_7_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xC1E0000000000000
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fmadd f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xC1E0000000000000
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#_ REGISTER_OUT f4 0xC1E0000000000000
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test_fmadd_7_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xC1E0000000000000
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fmadd. f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xC1E0000000000000
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#_ REGISTER_OUT f4 0xC1E0000000000000
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#_ REGISTER_OUT cr 0x00000000
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test_fmadd_8_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x41DFFFFFFFC00000
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fmadd f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
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#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
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test_fmadd_8_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x41DFFFFFFFC00000
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fmadd. f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
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#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
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#_ REGISTER_OUT cr 0x00000000
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test_fmadd_9_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x7FF0000000000000
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fmadd f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x7FF0000000000000
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#_ REGISTER_OUT f4 0x7FF0000000000000
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test_fmadd_9_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x7FF0000000000000
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fmadd. f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x7FF0000000000000
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#_ REGISTER_OUT f4 0x7FF0000000000000
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#_ REGISTER_OUT cr 0x00000000
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test_fmadd_10_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xFFF0000000000000
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fmadd f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xFFF0000000000000
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#_ REGISTER_OUT f4 0xFFF0000000000000
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test_fmadd_10_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xFFF0000000000000
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fmadd. f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xFFF0000000000000
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#_ REGISTER_OUT f4 0xFFF0000000000000
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#_ REGISTER_OUT cr 0x00000000
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test_fmadd_11_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xFFF8000000000000
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fmadd f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xFFF8000000000000
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#_ REGISTER_OUT f4 0xFFF8000000000000
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test_fmadd_11_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xFFF8000000000000
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fmadd. f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xFFF8000000000000
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#_ REGISTER_OUT f4 0xFFF8000000000000
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#_ REGISTER_OUT cr 0x00000000
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test_fmadd_12_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xFFF4000000000000
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fmadd f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xFFF4000000000000
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#_ REGISTER_OUT f4 0xFFFC000000000000
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test_fmadd_12_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xFFF4000000000000
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fmadd. f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xFFF4000000000000
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#_ REGISTER_OUT f4 0xFFFC000000000000
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#_ REGISTER_OUT cr 0x0A000000
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test_fmadd_13_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x8000000000000000
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#_ REGISTER_IN f3 0x0000000000000000
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fmadd f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x8000000000000000
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#_ REGISTER_OUT f3 0x0000000000000000
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#_ REGISTER_OUT f4 0x0000000000000000
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test_fmadd_13_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x8000000000000000
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#_ REGISTER_IN f3 0x0000000000000000
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fmadd. f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x8000000000000000
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#_ REGISTER_OUT f3 0x0000000000000000
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#_ REGISTER_OUT f4 0x0000000000000000
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#_ REGISTER_OUT cr 0x00000000
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test_fmadd_14_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x8000000000000000
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#_ REGISTER_IN f3 0x8000000000000000
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fmadd f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x8000000000000000
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#_ REGISTER_OUT f3 0x8000000000000000
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#_ REGISTER_OUT f4 0x8000000000000000
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|
|
|
test_fmadd_14_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x8000000000000000
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#_ REGISTER_IN f3 0x8000000000000000
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fmadd. f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x8000000000000000
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#_ REGISTER_OUT f3 0x8000000000000000
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#_ REGISTER_OUT f4 0x8000000000000000
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#_ REGISTER_OUT cr 0x00000000
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|
|
|
test_fmadd_15_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x8000000000000000
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#_ REGISTER_IN f3 0x0000000000000001
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fmadd f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x8000000000000000
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#_ REGISTER_OUT f3 0x0000000000000001
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#_ REGISTER_OUT f4 0x0000000000000001
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|
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|
test_fmadd_15_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x8000000000000000
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#_ REGISTER_IN f3 0x0000000000000001
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fmadd. f4, f1, f2, f3
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|
blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x8000000000000000
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#_ REGISTER_OUT f3 0x0000000000000001
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#_ REGISTER_OUT f4 0x0000000000000001
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#_ REGISTER_OUT cr 0x00000000
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|
|
|
test_fmadd_16_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x8000000000000000
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#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
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fmadd f4, f1, f2, f3
|
|
blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_16_cr_GEN:
|
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#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
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|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_17_GEN:
|
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#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_17_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_18_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_18_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_19_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_19_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_20_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_20_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_21_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_21_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_22_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_22_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_23_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_23_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_24_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_24_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_25_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_25_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_26_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_26_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_27_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_27_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_28_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_28_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_29_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_29_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_30_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_30_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_31_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_31_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_32_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_32_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_33_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_33_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_34_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_34_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_35_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_35_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_36_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_36_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_37_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_37_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_38_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_38_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_39_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_39_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_40_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_40_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_41_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_41_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_42_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_42_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_43_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_43_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_44_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_44_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_45_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_45_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_46_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_46_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_47_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_47_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_48_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_48_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_49_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_49_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_50_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_50_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_51_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_51_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_52_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_52_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_53_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_53_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_54_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_54_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_55_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_55_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_56_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_56_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_57_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_57_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_58_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_58_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_59_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_59_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_60_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_60_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_61_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_61_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_62_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmadd_62_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_63_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_63_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_64_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_64_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_65_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_65_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_66_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_66_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_67_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_67_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_68_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_68_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_69_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_69_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_70_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_70_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_71_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_71_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_72_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_72_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_73_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_73_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_74_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmadd_74_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_75_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_75_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_76_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_76_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_77_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_77_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_78_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_78_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_79_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_79_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_80_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_80_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_81_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_81_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_82_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_82_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_83_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_83_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_84_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_84_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_85_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_85_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_86_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_86_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_87_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_87_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_88_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_88_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_89_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_89_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_90_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_90_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_91_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_91_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_92_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_92_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_93_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_93_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_94_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_94_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_95_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_95_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_96_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_96_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_97_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_97_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_98_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_98_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_99_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_99_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_100_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_100_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_101_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_101_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_102_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_102_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_103_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_103_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_104_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_104_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_105_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_105_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_106_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_106_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_107_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_107_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_108_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_108_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_109_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_109_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_110_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_110_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_111_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_111_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_112_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_112_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_113_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_113_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_114_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_114_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_115_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_115_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_116_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_116_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_117_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_117_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_118_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_118_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_119_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_119_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_120_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_120_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_121_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_121_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_122_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_122_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_123_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_123_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_124_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_124_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_125_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_125_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_126_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_126_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_127_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_127_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_128_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_128_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_129_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_129_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_130_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_130_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_131_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_131_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_132_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_132_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_133_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_133_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_134_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_134_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_135_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_135_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_136_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_136_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_137_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_137_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_138_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_138_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_139_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_139_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_140_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_140_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_141_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_141_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_142_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_142_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_143_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_143_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_144_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_144_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_145_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_145_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_146_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmadd_146_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_147_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_147_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_148_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_148_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_149_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_149_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_150_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_150_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_151_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_151_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_152_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_152_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_153_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_153_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_154_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_154_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_155_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_155_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_156_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_156_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_157_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_157_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_158_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_158_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_159_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_159_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_160_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_160_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_161_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_161_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_162_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_162_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_163_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_163_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_164_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_164_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_165_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_165_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_166_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_166_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_167_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_167_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_168_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_168_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_169_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_169_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_170_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmadd_170_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_171_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_171_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_172_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_172_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_173_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_173_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_174_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_174_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_175_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_175_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_176_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_176_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_177_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_177_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_178_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_178_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_179_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_179_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_180_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_180_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_181_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_181_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_182_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmadd_182_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_183_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_183_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_184_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_184_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_185_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_185_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_186_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_186_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_187_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_187_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_188_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_188_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_189_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_189_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_190_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_190_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_191_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_191_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_192_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_192_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_193_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_193_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_194_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmadd_194_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_195_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_195_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_196_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_196_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_197_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_197_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_198_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_198_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_199_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_199_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_200_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_200_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_201_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_201_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_202_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_202_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_203_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_203_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_204_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_204_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_205_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_205_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_206_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_206_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_207_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_207_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_208_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_208_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_209_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_209_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_210_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_210_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_211_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_211_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_212_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_212_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_213_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_213_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_214_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_214_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_215_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_215_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_216_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_216_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_217_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_217_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_218_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_218_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_219_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_219_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_220_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_220_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_221_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_221_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_222_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_222_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_223_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_223_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_224_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_224_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_225_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_225_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_226_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_226_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_227_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_227_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_228_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_228_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_229_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_229_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_230_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmadd_230_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_231_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_231_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_232_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_232_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_233_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_233_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_234_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_234_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_235_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_235_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_236_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_236_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_237_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_237_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_238_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_238_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_239_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_239_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_240_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_240_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_241_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_241_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_242_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_242_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_243_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_243_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_244_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_244_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_245_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_245_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_246_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_246_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_247_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_247_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_248_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_248_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_249_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_249_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_250_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_250_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_251_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_251_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_252_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_252_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_253_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_253_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_254_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_254_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_255_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_255_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_256_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_256_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_257_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_257_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_258_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_258_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_259_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_259_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_260_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_260_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_261_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_261_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_262_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_262_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_263_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_263_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_264_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_264_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_265_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_265_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_266_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_266_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_267_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_267_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_268_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_268_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_269_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_269_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_270_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_270_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_271_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_271_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_272_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_272_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_273_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_273_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_274_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_274_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_275_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_275_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_276_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_276_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_277_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_277_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_278_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_278_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_279_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_279_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_280_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_280_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_281_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_281_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_282_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_282_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_283_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_283_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_284_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_284_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_285_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_285_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_286_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_286_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_287_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_287_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_288_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_288_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_289_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_289_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_290_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_290_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_291_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_291_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_292_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_292_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_293_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_293_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_294_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_294_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_295_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_295_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_296_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_296_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_297_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_297_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_298_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_298_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_299_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_299_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_300_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_300_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_301_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_301_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_302_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmadd_302_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_303_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_303_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_304_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_304_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_305_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_305_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_306_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_306_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_307_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_307_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_308_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_308_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_309_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_309_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_310_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_310_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_311_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_311_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_312_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_312_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_313_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_313_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_314_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_314_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_315_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_315_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_316_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_316_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_317_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_317_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_318_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_318_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_319_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_319_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_320_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_320_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_321_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_321_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_322_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_322_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_323_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_323_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_324_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_324_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_325_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_325_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_326_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_326_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_327_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_327_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_328_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_328_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_329_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_329_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_330_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_330_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_331_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_331_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_332_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_332_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_333_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_333_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_334_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_334_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_335_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_335_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_336_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_336_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_337_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_337_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_338_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_338_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_339_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000002
|
|
|
|
test_fmadd_339_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000002
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_340_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x0010000000000000
|
|
|
|
test_fmadd_340_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x0010000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_341_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_341_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_342_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_342_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_343_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_343_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_344_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_344_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_345_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_345_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_346_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_346_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_347_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_347_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_348_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_348_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_349_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmadd_349_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_350_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmadd_350_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_351_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_351_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_352_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFE
|
|
|
|
test_fmadd_352_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_353_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_353_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_354_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_354_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_355_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_355_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_356_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_356_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_357_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_357_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_358_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_358_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_359_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_359_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_360_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_360_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_361_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000080000000
|
|
|
|
test_fmadd_361_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000080000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_362_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000080000000
|
|
|
|
test_fmadd_362_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000080000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_363_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x800000007FFFFFFF
|
|
|
|
test_fmadd_363_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x800000007FFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_364_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFF7FFFFFFF
|
|
|
|
test_fmadd_364_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFF7FFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_365_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_365_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_366_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_366_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_367_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_367_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_368_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_368_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_369_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_369_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_370_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_370_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_371_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_371_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_372_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_372_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_373_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFF
|
|
|
|
test_fmadd_373_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_374_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFF
|
|
|
|
test_fmadd_374_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_375_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000080000000
|
|
|
|
test_fmadd_375_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000080000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_376_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x001000007FFFFFFE
|
|
|
|
test_fmadd_376_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x001000007FFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_377_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_377_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_378_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_378_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_379_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_379_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_380_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_380_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_381_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_381_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_382_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_382_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_383_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_383_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_384_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_384_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_385_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_385_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_386_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_386_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_387_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_387_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_388_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_388_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_389_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_389_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_390_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_390_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_391_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_391_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_392_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_392_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_393_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_393_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_394_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_394_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_395_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_395_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_396_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_396_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_397_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_397_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_398_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_398_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_399_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_399_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_400_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_400_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_401_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_401_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_402_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_402_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_403_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_403_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_404_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_404_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_405_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_405_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_406_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_406_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_407_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_407_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_408_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_408_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_409_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_409_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_410_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_410_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_411_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_411_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_412_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_412_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_413_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_413_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_414_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_414_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_415_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_415_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_416_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_416_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_417_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_417_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_418_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_418_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_419_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_419_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_420_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_420_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_421_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_421_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_422_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_422_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_423_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_423_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_424_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_424_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_425_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_425_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_426_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_426_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_427_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_427_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_428_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_428_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_429_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_429_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_430_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_430_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_431_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_431_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_432_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_432_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_433_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_433_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_434_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_434_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_435_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_435_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_436_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_436_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_437_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_437_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_438_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_438_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_439_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_439_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_440_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_440_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_441_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_441_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_442_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_442_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_443_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_443_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_444_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_444_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_445_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_445_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_446_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmadd_446_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_447_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_447_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_448_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_448_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_449_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_449_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_450_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_450_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_451_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_451_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_452_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_452_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_453_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_453_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_454_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_454_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_455_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_455_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_456_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_456_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_457_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_457_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_458_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_458_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_459_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_459_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_460_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_460_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_461_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_461_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_462_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_462_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_463_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_463_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_464_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_464_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_465_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_465_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_466_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_466_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_467_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_467_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_468_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_468_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_469_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_469_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_470_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_470_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_471_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_471_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_472_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_472_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_473_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_473_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_474_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_474_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_475_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_475_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_476_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_476_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_477_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_477_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_478_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_478_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_479_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_479_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_480_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_480_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_481_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_481_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_482_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_482_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_483_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0010000000000000
|
|
|
|
test_fmadd_483_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0010000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_484_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x001FFFFFFFFFFFFE
|
|
|
|
test_fmadd_484_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x001FFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_485_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_485_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_486_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_486_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_487_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_487_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_488_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_488_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_489_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_489_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_490_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_490_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_491_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_491_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_492_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_492_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_493_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmadd_493_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_494_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmadd_494_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_495_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFE
|
|
|
|
test_fmadd_495_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_496_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_496_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_497_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_497_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_498_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_498_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_499_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_499_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_500_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_500_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_501_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_501_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_502_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_502_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_503_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_503_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_504_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_504_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_505_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
|
|
test_fmadd_505_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_506_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
|
|
test_fmadd_506_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_507_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
|
|
test_fmadd_507_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_508_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFBFFFFE
|
|
|
|
test_fmadd_508_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFBFFFFE
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_509_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_509_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_510_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_510_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_511_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_511_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_512_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_512_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_513_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_513_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_514_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_514_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_515_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_515_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_516_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_516_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_517_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
|
|
test_fmadd_517_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_518_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
|
|
test_fmadd_518_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_519_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
|
|
test_fmadd_519_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_520_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFFFFFFE
|
|
|
|
test_fmadd_520_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_521_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_521_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_522_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_522_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_523_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_523_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_524_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_524_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_525_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_525_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_526_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_526_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_527_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_527_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_528_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_528_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_529_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_529_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_530_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_530_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_531_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_531_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_532_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_532_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_533_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_533_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_534_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_534_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_535_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_535_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_536_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_536_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_537_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_537_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_538_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_538_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_539_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_539_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_540_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_540_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_541_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_541_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_542_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_542_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_543_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_543_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_544_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_544_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_545_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_545_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_546_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_546_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_547_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_547_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_548_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_548_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_549_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_549_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_550_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_550_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_551_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_551_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_552_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_552_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_553_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_553_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_554_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_554_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_555_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_555_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_556_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_556_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_557_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_557_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_558_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_558_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_559_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_559_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_560_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_560_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_561_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_561_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_562_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_562_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_563_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_563_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_564_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_564_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_565_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_565_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_566_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_566_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_567_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_567_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_568_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_568_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_569_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_569_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_570_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_570_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_571_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_571_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_572_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_572_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_573_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_573_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_574_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_574_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_575_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_575_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_576_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_576_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_577_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_577_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_578_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_578_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_579_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_579_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_580_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_580_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_581_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_581_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_582_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_582_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_583_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_583_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_584_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_584_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_585_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_585_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_586_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_586_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_587_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_587_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_588_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_588_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_589_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_589_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_590_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmadd_590_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_591_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_591_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_592_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_592_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_593_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_593_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_594_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_594_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_595_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_595_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_596_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_596_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_597_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_597_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_598_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_598_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_599_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_599_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_600_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_600_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_601_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_601_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_602_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_602_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_603_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000002
|
|
|
|
test_fmadd_603_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000002
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_604_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x0010000000000000
|
|
|
|
test_fmadd_604_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x0010000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_605_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_605_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_606_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_606_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_607_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_607_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_608_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_608_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_609_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_609_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_610_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_610_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_611_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_611_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_612_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_612_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_613_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_613_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_614_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_614_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_615_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0010000000000000
|
|
|
|
test_fmadd_615_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0010000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_616_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x001FFFFFFFFFFFFE
|
|
|
|
test_fmadd_616_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x001FFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_617_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_617_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_618_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_618_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_619_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_619_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_620_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_620_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_621_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_621_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_622_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_622_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_623_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_623_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_624_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_624_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_625_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_625_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_626_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_626_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_627_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_627_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_628_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_628_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_629_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x4000000000000000
|
|
|
|
test_fmadd_629_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x4000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_630_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_630_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_631_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmadd_631_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_632_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmadd_632_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_633_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_633_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_634_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_634_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_635_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_635_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_636_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_636_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_637_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_637_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_638_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_638_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_639_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_639_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_640_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_640_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_641_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_641_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_642_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC000000000000000
|
|
|
|
test_fmadd_642_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_643_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000200000
|
|
|
|
test_fmadd_643_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000200000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_644_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFF800000
|
|
|
|
test_fmadd_644_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_645_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_645_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_646_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_646_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_647_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_647_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_648_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_648_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_649_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_649_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_650_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_650_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_651_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_651_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_652_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_652_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_653_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmadd_653_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_654_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000200000
|
|
|
|
test_fmadd_654_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000200000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_655_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1F0000000000000
|
|
|
|
test_fmadd_655_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1F0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_656_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_656_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_657_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_657_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_658_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_658_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_659_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_659_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_660_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_660_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_661_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_661_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_662_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_662_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_663_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_663_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_664_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_664_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_665_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmadd_665_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_666_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFF800000
|
|
|
|
test_fmadd_666_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_667_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_667_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_668_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41EFFFFFFFC00000
|
|
|
|
test_fmadd_668_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41EFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_669_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_669_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_670_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_670_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_671_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_671_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_672_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_672_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_673_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_673_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_674_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_674_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_675_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_675_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_676_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_676_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_677_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_677_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_678_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_678_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_679_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_679_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_680_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_680_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_681_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_681_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_682_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_682_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_683_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_683_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_684_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_684_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_685_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_685_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_686_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_686_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_687_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_687_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_688_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_688_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_689_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_689_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_690_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_690_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_691_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_691_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_692_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_692_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_693_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_693_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_694_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_694_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_695_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_695_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_696_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_696_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_697_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_697_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_698_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_698_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_699_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_699_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_700_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_700_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_701_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_701_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_702_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_702_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_703_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_703_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_704_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_704_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_705_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_705_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_706_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_706_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_707_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_707_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_708_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_708_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_709_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_709_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_710_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_710_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_711_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_711_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_712_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_712_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_713_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_713_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_714_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_714_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_715_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_715_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_716_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_716_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_717_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_717_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_718_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_718_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_719_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_719_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_720_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_720_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_721_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_721_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_722_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmadd_722_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_723_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_723_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_724_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_724_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_725_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_725_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_726_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_726_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_727_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_727_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_728_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_728_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_729_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_729_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_730_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_730_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_731_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_731_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_732_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_732_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_733_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_733_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_734_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_734_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_735_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_735_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_736_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_736_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_737_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_737_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_738_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_738_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_739_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_739_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_740_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_740_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_741_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_741_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_742_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_742_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_743_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_743_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_744_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_744_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_745_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmadd_745_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_746_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmadd_746_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_747_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_747_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_748_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFE
|
|
|
|
test_fmadd_748_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_749_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_749_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_750_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_750_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_751_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_751_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_752_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_752_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_753_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_753_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_754_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_754_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_755_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_755_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_756_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_756_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_757_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmadd_757_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_758_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmadd_758_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_759_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFE
|
|
|
|
test_fmadd_759_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_760_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_760_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_761_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_761_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_762_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_762_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_763_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_763_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_764_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_764_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_765_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_765_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_766_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_766_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_767_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_767_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_768_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_768_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_769_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_769_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_770_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_770_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_771_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_771_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_772_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_772_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_773_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_773_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_774_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC000000000000000
|
|
|
|
test_fmadd_774_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_775_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000200000
|
|
|
|
test_fmadd_775_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000200000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_776_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFF800000
|
|
|
|
test_fmadd_776_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_777_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_777_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_778_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_778_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_779_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_779_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_780_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_780_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_781_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_781_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_782_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_782_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_783_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_783_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_784_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_784_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_785_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x4000000000000000
|
|
|
|
test_fmadd_785_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x4000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_786_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_786_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_787_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmadd_787_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_788_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmadd_788_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_789_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_789_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_790_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_790_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_791_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_791_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_792_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_792_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_793_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmadd_793_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_794_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmadd_794_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_795_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmadd_795_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_796_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmadd_796_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_797_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000200000
|
|
|
|
test_fmadd_797_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000200000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_798_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_798_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_799_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_799_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_800_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41EFFFFFFFE00000
|
|
|
|
test_fmadd_800_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41EFFFFFFFE00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_801_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_801_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_802_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_802_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_803_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_803_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_804_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_804_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_805_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmadd_805_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_806_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmadd_806_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_807_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmadd_807_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_808_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmadd_808_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_809_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFF800000
|
|
|
|
test_fmadd_809_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_810_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_810_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_811_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1EFFFFFFFE00000
|
|
|
|
test_fmadd_811_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1EFFFFFFFE00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_812_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_812_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_813_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_813_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_814_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_814_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_815_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_815_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_816_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_816_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_817_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_817_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_818_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_818_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_819_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_819_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_820_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_820_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_821_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_821_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_822_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_822_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_823_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_823_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_824_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_824_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_825_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_825_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_826_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_826_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_827_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_827_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_828_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_828_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_829_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_829_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_830_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_830_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_831_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_831_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_832_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_832_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_833_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_833_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_834_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_834_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_835_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_835_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_836_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_836_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_837_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_837_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_838_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_838_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_839_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_839_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_840_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_840_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_841_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_841_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_842_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_842_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_843_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_843_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_844_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_844_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_845_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_845_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_846_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_846_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_847_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_847_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_848_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_848_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_849_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_849_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_850_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_850_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_851_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_851_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_852_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_852_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_853_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_853_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_854_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_854_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_855_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_855_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_856_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_856_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_857_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_857_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_858_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_858_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_859_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_859_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_860_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_860_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_861_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_861_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_862_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_862_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_863_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_863_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_864_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_864_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_865_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_865_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_866_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmadd_866_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_867_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_867_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_868_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_868_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_869_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_869_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_870_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_870_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_871_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_871_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_872_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_872_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_873_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_873_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_874_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_874_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_875_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_875_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_876_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_876_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_877_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_877_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_878_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_878_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_879_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_879_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_880_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_880_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_881_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_881_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_882_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_882_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_883_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_883_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_884_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_884_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_885_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_885_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_886_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_886_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_887_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_887_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_888_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_888_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_889_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000080000000
|
|
|
|
test_fmadd_889_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000080000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_890_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000080000000
|
|
|
|
test_fmadd_890_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000080000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_891_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x800000007FFFFFFF
|
|
|
|
test_fmadd_891_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x800000007FFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_892_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFF7FFFFFFF
|
|
|
|
test_fmadd_892_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFF7FFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_893_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_893_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_894_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_894_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_895_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_895_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_896_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_896_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_897_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_897_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_898_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_898_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_899_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_899_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_900_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_900_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_901_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
|
|
test_fmadd_901_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_902_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
|
|
test_fmadd_902_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_903_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
|
|
test_fmadd_903_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_904_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFBFFFFE
|
|
|
|
test_fmadd_904_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFBFFFFE
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_905_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_905_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_906_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_906_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_907_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_907_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_908_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_908_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_909_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_909_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_910_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_910_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_911_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_911_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_912_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_912_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_913_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_913_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_914_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_914_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_915_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_915_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_916_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_916_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_917_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmadd_917_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_918_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000200000
|
|
|
|
test_fmadd_918_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000200000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_919_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1F0000000000000
|
|
|
|
test_fmadd_919_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1F0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_920_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_920_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_921_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_921_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_922_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_922_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_923_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_923_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_924_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_924_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_925_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmadd_925_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_926_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmadd_926_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_927_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmadd_927_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_928_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmadd_928_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_929_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000200000
|
|
|
|
test_fmadd_929_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000200000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_930_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_930_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_931_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_931_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_932_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41EFFFFFFFE00000
|
|
|
|
test_fmadd_932_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41EFFFFFFFE00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_933_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_933_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_934_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_934_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_935_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_935_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_936_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_936_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_937_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
|
|
test_fmadd_937_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_938_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
|
|
test_fmadd_938_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_939_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
|
|
test_fmadd_939_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_940_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
|
|
test_fmadd_940_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_941_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
|
|
test_fmadd_941_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_942_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
|
|
test_fmadd_942_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_943_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFFC00000
|
|
|
|
test_fmadd_943_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_944_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x43D0000000200000
|
|
|
|
test_fmadd_944_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x43D0000000200000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_945_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_945_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_946_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_946_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_947_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_947_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_948_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_948_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_949_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmadd_949_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_950_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmadd_950_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_951_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmadd_951_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_952_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmadd_952_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_953_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmadd_953_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_954_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmadd_954_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_955_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC3D0000000000000
|
|
|
|
test_fmadd_955_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC3D0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_956_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFF800000
|
|
|
|
test_fmadd_956_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_957_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_957_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_958_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_958_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_959_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_959_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_960_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_960_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_961_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_961_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_962_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_962_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_963_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_963_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_964_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_964_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_965_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_965_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_966_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_966_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_967_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_967_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_968_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_968_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_969_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_969_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_970_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_970_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_971_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_971_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_972_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_972_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_973_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_973_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_974_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_974_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_975_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_975_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_976_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_976_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_977_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_977_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_978_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_978_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_979_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_979_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_980_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_980_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_981_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_981_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_982_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_982_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_983_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_983_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_984_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_984_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_985_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_985_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_986_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_986_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_987_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_987_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_988_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_988_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_989_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_989_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_990_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_990_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_991_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_991_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_992_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_992_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_993_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_993_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_994_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_994_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_995_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_995_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_996_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_996_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_997_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_997_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_998_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_998_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_999_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_999_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1000_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1000_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1001_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1001_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1002_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1002_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1003_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1003_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1004_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1004_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1005_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1005_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1006_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1006_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1007_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1007_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1008_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1008_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1009_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_1009_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1010_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_1010_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1011_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_1011_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1012_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_1012_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1013_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_1013_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1014_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_1014_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1015_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_1015_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1016_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_1016_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1017_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1017_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1018_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1018_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1019_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1019_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1020_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1020_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1021_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_1021_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1022_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmadd_1022_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1023_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmadd_1023_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1024_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmadd_1024_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1025_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_1025_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1026_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_1026_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1027_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_1027_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1028_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_1028_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1029_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1029_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1030_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1030_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1031_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1031_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1032_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1032_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1033_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFF
|
|
|
|
test_fmadd_1033_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1034_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFF
|
|
|
|
test_fmadd_1034_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1035_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000080000000
|
|
|
|
test_fmadd_1035_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000080000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1036_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x001000007FFFFFFE
|
|
|
|
test_fmadd_1036_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x001000007FFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1037_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_1037_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1038_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_1038_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1039_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_1039_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1040_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_1040_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1041_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1041_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1042_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1042_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1043_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1043_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1044_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1044_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1045_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
|
|
test_fmadd_1045_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1046_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
|
|
test_fmadd_1046_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1047_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
|
|
test_fmadd_1047_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1048_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFFFFFFE
|
|
|
|
test_fmadd_1048_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1049_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmadd_1049_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1050_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_1050_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1051_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_1051_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1052_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_1052_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1053_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1053_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1054_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1054_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1055_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1055_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1056_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1056_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1057_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_1057_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1058_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_1058_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1059_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_1059_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1060_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmadd_1060_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1061_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmadd_1061_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1062_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFF800000
|
|
|
|
test_fmadd_1062_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1063_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmadd_1063_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1064_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41EFFFFFFFC00000
|
|
|
|
test_fmadd_1064_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x41EFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1065_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1065_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1066_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1066_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1067_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1067_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1068_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1068_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1069_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmadd_1069_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1070_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmadd_1070_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1071_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmadd_1071_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1072_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmadd_1072_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1073_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFF800000
|
|
|
|
test_fmadd_1073_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1074_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmadd_1074_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1075_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1EFFFFFFFE00000
|
|
|
|
test_fmadd_1075_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC1EFFFFFFFE00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1076_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmadd_1076_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1077_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1077_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1078_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1078_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1079_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1079_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1080_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1080_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1081_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmadd_1081_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1082_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmadd_1082_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1083_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmadd_1083_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1084_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmadd_1084_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1085_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmadd_1085_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1086_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmadd_1086_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1087_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC3D0000000000000
|
|
|
|
test_fmadd_1087_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC3D0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1088_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFF800000
|
|
|
|
test_fmadd_1088_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1089_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1089_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1090_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1090_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1091_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1091_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1092_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1092_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1093_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
|
|
test_fmadd_1093_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1094_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
|
|
test_fmadd_1094_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1095_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
|
|
test_fmadd_1095_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1096_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
|
|
test_fmadd_1096_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1097_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
|
|
test_fmadd_1097_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1098_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
|
|
test_fmadd_1098_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1099_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF400000
|
|
|
|
test_fmadd_1099_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF400000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmadd_1100_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFFC00000
|
|
|
|
test_fmadd_1100_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1101_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1101_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1102_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1102_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1103_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1103_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1104_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1104_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1105_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1105_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1106_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1106_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1107_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1107_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1108_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1108_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1109_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1109_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1110_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1110_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1111_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1111_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1112_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1112_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1113_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1113_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1114_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1114_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1115_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1115_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1116_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1116_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1117_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1117_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1118_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1118_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1119_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1119_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1120_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1120_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1121_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1121_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1122_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1122_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1123_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1123_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1124_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1124_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1125_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1125_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1126_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1126_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1127_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1127_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1128_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1128_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1129_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1129_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1130_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1130_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1131_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1131_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1132_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1132_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1133_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1133_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1134_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1134_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1135_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1135_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1136_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1136_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1137_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1137_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1138_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1138_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1139_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1139_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1140_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1140_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1141_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1141_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1142_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1142_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1143_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1143_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1144_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1144_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1145_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1145_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1146_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1146_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1147_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1147_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1148_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1148_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1149_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1149_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1150_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1150_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1151_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1151_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1152_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1152_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1153_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1153_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1154_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1154_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1155_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1155_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1156_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1156_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1157_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1157_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1158_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1158_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1159_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1159_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1160_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1160_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1161_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1161_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1162_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1162_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1163_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1163_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1164_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1164_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1165_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1165_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1166_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1166_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1167_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1167_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1168_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1168_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1169_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1169_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1170_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1170_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1171_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1171_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1172_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1172_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1173_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1173_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1174_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1174_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1175_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1175_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1176_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1176_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1177_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1177_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1178_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1178_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1179_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1179_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1180_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1180_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1181_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1181_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1182_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1182_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1183_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1183_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1184_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1184_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1185_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1185_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1186_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1186_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1187_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1187_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1188_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1188_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1189_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1189_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1190_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1190_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1191_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1191_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1192_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1192_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1193_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1193_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1194_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1194_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1195_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1195_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1196_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1196_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1197_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1197_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1198_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1198_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1199_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1199_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1200_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1200_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1201_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1201_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1202_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1202_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1203_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1203_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1204_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1204_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1205_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1205_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1206_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1206_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1207_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1207_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1208_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1208_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1209_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1209_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1210_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1210_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1211_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1211_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1212_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1212_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1213_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1213_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1214_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1214_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1215_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1215_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1216_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1216_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1217_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1217_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1218_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1218_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1219_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1219_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1220_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1220_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1221_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1221_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1222_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1222_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1223_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1223_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1224_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1224_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1225_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1225_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1226_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1226_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1227_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1227_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1228_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1228_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1229_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1229_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1230_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1230_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1231_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1231_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1232_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1232_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1233_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1233_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1234_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1234_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1235_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1235_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1236_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1236_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1237_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1237_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1238_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1238_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1239_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1239_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1240_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1240_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1241_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1241_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1242_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1242_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1243_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1243_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1244_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1244_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1245_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1245_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1246_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1246_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1247_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1247_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1248_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1248_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1249_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1249_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1250_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1250_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1251_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1251_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1252_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1252_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1253_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1253_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1254_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1254_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1255_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1255_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1256_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1256_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1257_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1257_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1258_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1258_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1259_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1259_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1260_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1260_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1261_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1261_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1262_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1262_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1263_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1263_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1264_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1264_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1265_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1265_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1266_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1266_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1267_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1267_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1268_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1268_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1269_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1269_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1270_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1270_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1271_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1271_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1272_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1272_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1273_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1273_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1274_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1274_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1275_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1275_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1276_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1276_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1277_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1277_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1278_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1278_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1279_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1279_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1280_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1280_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1281_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1281_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1282_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1282_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1283_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1283_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1284_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1284_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1285_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1285_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1286_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1286_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1287_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1287_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1288_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1288_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1289_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1289_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1290_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1290_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1291_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1291_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1292_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1292_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1293_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1293_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1294_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1294_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1295_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1295_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1296_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1296_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1297_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1297_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1298_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1298_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1299_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1299_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1300_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1300_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1301_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1301_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1302_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1302_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1303_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1303_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1304_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1304_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1305_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1305_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1306_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1306_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1307_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1307_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1308_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1308_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1309_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1309_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1310_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1310_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1311_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1311_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1312_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1312_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1313_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1313_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1314_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1314_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1315_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1315_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1316_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1316_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1317_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1317_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1318_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1318_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1319_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1319_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1320_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1320_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1321_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1321_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1322_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1322_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1323_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1323_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1324_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1324_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1325_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1325_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1326_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1326_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1327_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1327_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1328_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1328_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1329_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1329_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1330_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1330_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1331_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1331_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1332_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1332_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1333_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1333_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1334_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1334_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1335_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1335_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1336_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1336_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1337_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1337_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1338_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1338_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1339_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1339_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1340_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1340_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1341_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1341_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1342_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1342_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1343_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1343_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1344_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1344_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1345_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1345_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1346_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1346_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1347_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1347_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1348_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1348_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1349_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1349_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1350_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1350_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1351_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1351_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1352_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1352_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1353_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1353_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1354_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1354_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1355_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1355_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1356_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1356_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1357_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1357_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1358_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1358_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1359_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1359_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1360_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1360_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1361_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1361_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1362_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1362_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1363_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1363_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1364_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1364_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1365_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1365_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1366_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1366_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1367_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1367_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1368_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1368_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1369_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1369_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1370_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1370_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1371_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1371_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1372_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1372_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1373_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1373_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1374_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1374_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1375_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1375_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1376_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1376_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1377_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1377_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1378_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1378_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1379_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1379_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1380_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1380_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1381_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1381_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1382_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1382_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1383_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1383_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1384_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1384_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1385_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1385_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1386_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1386_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1387_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1387_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1388_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1388_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1389_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1389_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1390_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1390_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1391_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1391_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1392_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1392_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1393_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1393_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1394_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1394_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1395_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1395_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1396_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1396_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1397_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1397_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1398_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1398_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1399_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1399_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1400_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1400_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1401_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1401_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1402_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmadd_1402_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1403_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1403_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1404_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1404_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1405_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1405_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1406_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1406_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1407_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1407_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1408_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1408_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1409_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1409_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1410_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1410_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1411_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1411_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1412_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1412_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1413_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmadd_1413_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1414_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmadd_1414_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1415_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1415_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1416_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1416_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1417_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1417_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1418_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1418_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1419_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1419_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1420_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1420_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1421_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1421_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1422_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1422_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1423_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1423_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1424_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1424_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1425_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1425_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1426_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1426_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1427_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1427_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1428_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1428_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1429_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1429_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1430_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1430_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1431_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1431_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1432_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1432_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1433_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1433_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1434_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1434_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1435_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1435_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1436_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1436_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1437_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1437_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1438_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1438_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1439_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1439_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1440_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1440_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1441_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1441_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1442_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1442_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1443_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1443_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1444_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1444_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1445_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1445_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1446_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1446_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1447_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1447_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1448_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1448_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1449_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1449_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1450_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1450_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1451_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1451_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1452_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1452_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1453_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1453_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1454_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1454_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1455_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1455_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1456_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1456_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1457_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1457_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1458_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1458_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1459_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1459_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1460_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1460_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1461_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1461_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1462_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1462_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1463_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1463_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1464_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1464_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1465_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1465_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1466_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1466_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1467_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1467_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1468_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1468_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1469_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1469_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1470_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1470_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1471_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1471_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1472_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1472_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1473_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1473_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1474_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1474_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1475_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1475_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1476_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1476_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1477_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1477_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1478_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1478_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1479_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1479_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1480_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1480_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1481_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1481_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1482_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1482_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1483_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1483_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1484_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1484_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1485_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1485_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1486_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1486_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1487_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1487_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1488_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1488_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1489_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1489_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1490_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1490_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1491_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1491_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1492_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1492_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1493_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1493_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1494_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1494_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1495_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1495_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1496_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1496_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1497_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1497_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1498_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1498_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1499_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1499_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1500_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1500_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1501_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1501_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1502_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1502_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1503_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1503_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1504_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1504_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1505_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1505_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1506_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1506_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1507_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1507_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1508_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1508_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1509_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1509_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1510_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1510_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1511_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1511_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1512_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1512_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1513_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1513_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1514_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1514_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1515_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1515_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1516_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1516_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1517_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1517_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1518_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1518_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1519_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1519_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1520_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1520_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1521_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1521_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1522_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1522_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1523_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1523_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1524_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1524_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1525_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1525_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1526_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1526_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1527_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1527_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1528_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1528_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1529_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1529_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1530_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1530_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1531_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1531_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1532_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1532_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1533_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1533_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1534_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1534_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1535_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1535_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1536_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1536_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1537_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1537_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1538_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1538_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1539_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1539_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1540_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1540_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1541_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1541_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1542_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1542_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1543_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1543_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1544_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1544_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1545_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1545_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1546_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1546_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1547_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1547_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1548_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1548_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1549_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1549_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1550_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1550_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1551_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1551_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1552_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1552_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1553_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1553_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1554_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1554_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1555_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1555_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1556_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1556_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1557_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1557_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1558_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1558_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1559_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1559_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1560_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1560_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1561_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1561_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1562_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1562_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1563_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1563_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1564_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1564_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1565_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1565_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1566_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1566_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1567_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1567_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1568_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1568_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1569_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1569_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1570_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1570_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1571_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1571_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmadd_1572_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1572_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1573_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1573_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1574_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1574_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1575_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1575_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1576_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1576_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1577_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1577_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1578_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1578_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1579_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1579_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1580_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1580_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1581_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1581_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1582_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1582_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1583_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1583_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1584_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmadd_1584_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1585_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1585_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1586_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1586_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1587_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1587_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1588_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1588_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1589_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1589_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1590_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1590_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1591_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1591_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1592_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1592_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1593_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1593_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1594_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1594_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1595_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1595_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1596_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1596_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1597_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1597_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1598_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1598_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1599_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1599_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1600_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1600_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1601_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1601_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1602_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1602_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1603_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1603_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1604_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1604_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1605_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1605_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1606_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1606_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1607_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1607_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1608_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1608_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1609_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1609_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1610_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1610_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1611_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1611_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1612_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1612_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1613_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1613_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1614_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1614_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1615_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1615_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1616_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1616_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1617_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1617_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1618_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1618_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1619_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1619_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1620_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1620_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1621_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1621_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1622_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1622_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1623_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1623_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1624_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1624_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1625_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1625_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1626_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1626_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1627_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1627_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1628_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1628_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1629_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1629_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1630_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1630_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1631_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1631_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1632_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1632_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1633_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1633_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1634_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1634_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1635_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1635_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1636_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1636_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1637_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1637_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1638_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1638_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1639_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1639_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1640_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1640_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1641_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1641_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1642_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1642_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1643_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1643_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1644_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1644_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1645_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1645_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1646_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1646_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1647_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1647_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1648_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1648_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1649_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1649_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1650_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1650_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1651_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1651_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1652_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1652_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1653_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1653_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1654_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1654_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1655_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1655_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1656_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1656_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1657_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1657_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1658_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1658_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1659_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1659_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1660_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1660_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1661_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1661_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1662_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1662_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1663_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1663_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1664_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1664_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1665_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1665_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1666_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1666_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1667_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1667_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1668_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1668_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1669_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1669_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1670_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1670_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1671_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1671_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1672_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1672_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1673_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1673_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1674_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1674_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1675_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1675_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1676_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1676_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1677_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1677_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1678_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1678_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1679_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1679_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1680_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1680_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1681_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1681_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1682_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1682_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1683_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1683_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1684_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1684_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1685_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1685_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1686_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1686_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1687_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1687_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1688_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1688_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1689_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1689_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1690_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1690_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1691_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1691_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1692_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1692_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1693_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1693_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1694_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1694_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1695_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1695_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1696_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1696_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1697_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1697_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1698_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1698_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1699_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1699_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1700_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1700_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1701_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1701_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1702_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1702_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1703_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1703_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1704_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1704_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1705_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1705_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1706_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1706_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1707_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1707_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1708_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1708_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1709_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1709_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1710_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1710_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1711_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1711_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1712_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1712_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1713_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1713_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1714_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1714_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1715_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1715_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1716_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1716_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1717_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1717_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1718_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1718_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1719_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1719_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1720_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1720_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1721_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1721_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1722_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1722_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1723_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1723_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1724_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1724_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1725_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1725_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1726_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1726_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1727_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1727_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmadd_1728_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmadd_1728_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmadd. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|