39745 lines
1.1 MiB
39745 lines
1.1 MiB
test_fmsub_1_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x0000000000000000
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|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
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|
#_ REGISTER_OUT f4 0x0000000000000000
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|
|
|
test_fmsub_1_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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|
#_ REGISTER_IN f2 0x0000000000000000
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|
#_ REGISTER_IN f3 0x0000000000000000
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|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
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|
#_ REGISTER_OUT f4 0x0000000000000000
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|
#_ REGISTER_OUT cr 0x00000000
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|
|
|
test_fmsub_2_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x8000000000000000
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fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
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#_ REGISTER_OUT f4 0x0000000000000000
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|
|
|
test_fmsub_2_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x8000000000000000
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fmsub. f4, f1, f2, f3
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|
blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
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|
#_ REGISTER_OUT f2 0x0000000000000000
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|
#_ REGISTER_OUT f3 0x8000000000000000
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#_ REGISTER_OUT f4 0x0000000000000000
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#_ REGISTER_OUT cr 0x00000000
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|
|
|
test_fmsub_3_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x0000000000000001
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fmsub f4, f1, f2, f3
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|
blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
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|
#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x0000000000000001
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#_ REGISTER_OUT f4 0x8000000000000001
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|
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|
test_fmsub_3_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x0000000000000001
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fmsub. f4, f1, f2, f3
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|
blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x0000000000000001
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#_ REGISTER_OUT f4 0x8000000000000001
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#_ REGISTER_OUT cr 0x00000000
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test_fmsub_4_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
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fmsub f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
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#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
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test_fmsub_4_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
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fmsub. f4, f1, f2, f3
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|
blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
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#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
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#_ REGISTER_OUT cr 0x00000000
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|
|
test_fmsub_5_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x3FF0000000000000
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fmsub f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x3FF0000000000000
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#_ REGISTER_OUT f4 0xBFF0000000000000
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test_fmsub_5_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x3FF0000000000000
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fmsub. f4, f1, f2, f3
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blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x3FF0000000000000
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#_ REGISTER_OUT f4 0xBFF0000000000000
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#_ REGISTER_OUT cr 0x00000000
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|
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test_fmsub_6_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xBFF0000000000000
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fmsub f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xBFF0000000000000
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#_ REGISTER_OUT f4 0x3FF0000000000000
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test_fmsub_6_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xBFF0000000000000
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fmsub. f4, f1, f2, f3
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blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xBFF0000000000000
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#_ REGISTER_OUT f4 0x3FF0000000000000
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#_ REGISTER_OUT cr 0x00000000
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test_fmsub_7_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xC1E0000000000000
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fmsub f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xC1E0000000000000
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#_ REGISTER_OUT f4 0x41E0000000000000
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test_fmsub_7_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xC1E0000000000000
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fmsub. f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xC1E0000000000000
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#_ REGISTER_OUT f4 0x41E0000000000000
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#_ REGISTER_OUT cr 0x00000000
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test_fmsub_8_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x41DFFFFFFFC00000
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fmsub f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
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#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
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test_fmsub_8_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x41DFFFFFFFC00000
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fmsub. f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
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#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
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#_ REGISTER_OUT cr 0x00000000
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test_fmsub_9_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x7FF0000000000000
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fmsub f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x7FF0000000000000
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#_ REGISTER_OUT f4 0xFFF0000000000000
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test_fmsub_9_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0x7FF0000000000000
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fmsub. f4, f1, f2, f3
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|
blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0x7FF0000000000000
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#_ REGISTER_OUT f4 0xFFF0000000000000
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#_ REGISTER_OUT cr 0x00000000
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test_fmsub_10_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xFFF0000000000000
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fmsub f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xFFF0000000000000
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#_ REGISTER_OUT f4 0x7FF0000000000000
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test_fmsub_10_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xFFF0000000000000
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fmsub. f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xFFF0000000000000
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#_ REGISTER_OUT f4 0x7FF0000000000000
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#_ REGISTER_OUT cr 0x00000000
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|
test_fmsub_11_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xFFF8000000000000
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fmsub f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xFFF8000000000000
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#_ REGISTER_OUT f4 0xFFF8000000000000
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test_fmsub_11_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xFFF8000000000000
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fmsub. f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xFFF8000000000000
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#_ REGISTER_OUT f4 0xFFF8000000000000
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#_ REGISTER_OUT cr 0x00000000
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|
|
test_fmsub_12_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xFFF4000000000000
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fmsub f4, f1, f2, f3
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blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xFFF4000000000000
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#_ REGISTER_OUT f4 0xFFFC000000000000
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|
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test_fmsub_12_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x0000000000000000
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#_ REGISTER_IN f3 0xFFF4000000000000
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fmsub. f4, f1, f2, f3
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|
blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x0000000000000000
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#_ REGISTER_OUT f3 0xFFF4000000000000
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#_ REGISTER_OUT f4 0xFFFC000000000000
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#_ REGISTER_OUT cr 0x0A000000
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|
|
test_fmsub_13_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x8000000000000000
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#_ REGISTER_IN f3 0x0000000000000000
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fmsub f4, f1, f2, f3
|
|
blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x8000000000000000
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#_ REGISTER_OUT f3 0x0000000000000000
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#_ REGISTER_OUT f4 0x8000000000000000
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|
|
|
test_fmsub_13_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x8000000000000000
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#_ REGISTER_IN f3 0x0000000000000000
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fmsub. f4, f1, f2, f3
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|
blr
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#_ REGISTER_OUT f1 0x0000000000000000
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#_ REGISTER_OUT f2 0x8000000000000000
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#_ REGISTER_OUT f3 0x0000000000000000
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#_ REGISTER_OUT f4 0x8000000000000000
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#_ REGISTER_OUT cr 0x00000000
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|
|
|
test_fmsub_14_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x8000000000000000
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#_ REGISTER_IN f3 0x8000000000000000
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|
fmsub f4, f1, f2, f3
|
|
blr
|
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#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
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|
#_ REGISTER_OUT f3 0x8000000000000000
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#_ REGISTER_OUT f4 0x0000000000000000
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|
|
|
test_fmsub_14_cr_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x8000000000000000
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|
#_ REGISTER_IN f3 0x8000000000000000
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|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
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|
#_ REGISTER_OUT f2 0x8000000000000000
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|
#_ REGISTER_OUT f3 0x8000000000000000
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#_ REGISTER_OUT f4 0x0000000000000000
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|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_15_GEN:
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#_ REGISTER_IN f1 0x0000000000000000
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#_ REGISTER_IN f2 0x8000000000000000
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#_ REGISTER_IN f3 0x0000000000000001
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|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
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|
#_ REGISTER_OUT f2 0x8000000000000000
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|
#_ REGISTER_OUT f3 0x0000000000000001
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|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_15_cr_GEN:
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|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
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|
#_ REGISTER_IN f3 0x0000000000000001
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|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
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|
#_ REGISTER_OUT f4 0x8000000000000001
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|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_16_GEN:
|
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#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_16_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_17_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_17_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_18_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_18_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_19_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_19_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_20_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_20_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_21_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_21_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_22_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_22_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_23_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_23_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_24_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_24_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_25_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_25_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_26_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_26_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_27_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_27_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_28_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_28_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_29_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_29_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_30_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_30_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_31_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_31_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_32_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_32_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_33_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_33_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_34_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_34_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_35_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_35_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_36_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_36_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_37_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_37_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_38_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_38_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_39_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_39_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_40_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_40_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_41_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_41_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_42_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_42_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_43_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_43_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_44_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_44_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_45_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_45_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_46_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_46_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_47_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_47_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_48_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_48_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_49_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_49_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_50_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_50_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_51_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_51_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_52_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_52_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_53_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_53_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_54_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_54_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_55_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_55_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_56_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_56_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_57_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_57_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_58_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_58_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_59_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_59_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_60_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_60_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_61_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmsub_61_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_62_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_62_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_63_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_63_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_64_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_64_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_65_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_65_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_66_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_66_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_67_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_67_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_68_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_68_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_69_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_69_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_70_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_70_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_71_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_71_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_72_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_72_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_73_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmsub_73_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_74_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_74_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_75_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_75_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_76_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_76_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_77_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_77_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_78_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_78_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_79_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_79_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_80_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_80_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_81_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_81_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_82_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_82_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_83_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_83_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_84_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_84_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_85_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_85_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_86_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_86_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_87_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_87_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_88_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_88_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_89_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_89_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_90_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_90_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_91_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_91_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_92_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_92_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_93_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_93_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_94_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_94_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_95_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_95_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_96_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_96_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_97_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_97_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_98_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_98_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_99_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_99_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_100_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_100_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_101_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_101_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_102_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_102_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_103_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_103_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_104_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_104_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_105_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_105_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_106_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_106_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_107_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_107_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_108_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_108_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_109_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_109_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_110_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_110_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_111_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_111_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_112_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_112_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_113_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_113_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_114_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_114_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_115_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_115_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_116_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_116_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_117_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_117_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_118_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_118_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_119_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_119_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_120_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_120_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_121_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_121_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_122_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_122_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_123_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_123_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_124_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_124_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_125_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_125_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_126_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_126_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_127_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_127_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_128_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_128_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_129_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_129_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_130_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_130_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_131_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_131_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_132_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_132_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_133_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_133_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_134_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_134_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_135_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_135_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_136_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_136_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_137_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_137_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_138_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_138_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_139_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_139_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_140_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_140_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_141_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_141_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_142_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_142_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_143_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_143_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_144_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_144_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_145_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmsub_145_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_146_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_146_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_147_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_147_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_148_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_148_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_149_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_149_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_150_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_150_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_151_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_151_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_152_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_152_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_153_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_153_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_154_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_154_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_155_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_155_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_156_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_156_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_157_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_157_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_158_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_158_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_159_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_159_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_160_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_160_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_161_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_161_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_162_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_162_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_163_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_163_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_164_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_164_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_165_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_165_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_166_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_166_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_167_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_167_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_168_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_168_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_169_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmsub_169_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_170_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_170_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_171_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_171_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_172_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_172_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_173_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_173_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_174_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_174_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_175_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_175_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_176_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_176_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_177_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_177_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_178_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_178_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_179_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_179_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_180_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_180_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_181_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmsub_181_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_182_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_182_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_183_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_183_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_184_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_184_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_185_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_185_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_186_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_186_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_187_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_187_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_188_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_188_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_189_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_189_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_190_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_190_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_191_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_191_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_192_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_192_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_193_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmsub_193_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_194_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_194_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_195_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_195_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_196_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_196_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_197_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_197_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_198_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_198_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_199_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_199_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_200_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_200_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_201_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_201_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_202_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_202_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_203_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_203_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_204_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_204_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_205_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_205_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_206_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_206_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_207_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_207_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_208_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_208_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_209_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_209_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_210_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_210_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_211_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_211_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_212_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_212_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_213_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_213_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_214_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_214_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_215_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_215_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_216_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_216_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_217_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_217_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_218_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_218_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_219_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_219_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_220_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_220_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_221_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_221_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_222_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_222_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_223_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_223_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_224_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_224_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_225_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_225_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_226_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_226_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_227_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_227_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_228_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_228_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_229_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmsub_229_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_230_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_230_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_231_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_231_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_232_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_232_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_233_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_233_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_234_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_234_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_235_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_235_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_236_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_236_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_237_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_237_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_238_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_238_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_239_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_239_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_240_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_240_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_241_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_241_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_242_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_242_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_243_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_243_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_244_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_244_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_245_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_245_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_246_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_246_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_247_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_247_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_248_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_248_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_249_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_249_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_250_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_250_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_251_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_251_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_252_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_252_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_253_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_253_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_254_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_254_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_255_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_255_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_256_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_256_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_257_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_257_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_258_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_258_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_259_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_259_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_260_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_260_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_261_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_261_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_262_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_262_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_263_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_263_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_264_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_264_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_265_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_265_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_266_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_266_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_267_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_267_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_268_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_268_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_269_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_269_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_270_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_270_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_271_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_271_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_272_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_272_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_273_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_273_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_274_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_274_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_275_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_275_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_276_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_276_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_277_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_277_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_278_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_278_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_279_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_279_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_280_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_280_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_281_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_281_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_282_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_282_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_283_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_283_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_284_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_284_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_285_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_285_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_286_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_286_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_287_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_287_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_288_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_288_cr_GEN:
|
|
#_ REGISTER_IN f1 0x8000000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x8000000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_289_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_289_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_290_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_290_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_291_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_291_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_292_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_292_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_293_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_293_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_294_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_294_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_295_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_295_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_296_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_296_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_297_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_297_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_298_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_298_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_299_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_299_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_300_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_300_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_301_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmsub_301_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_302_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_302_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_303_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_303_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_304_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_304_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_305_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_305_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_306_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_306_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_307_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_307_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_308_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_308_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_309_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_309_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_310_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_310_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_311_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_311_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_312_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_312_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_313_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_313_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_314_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_314_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_315_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_315_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_316_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_316_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_317_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_317_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_318_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_318_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_319_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_319_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_320_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_320_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_321_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_321_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_322_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_322_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_323_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_323_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_324_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_324_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_325_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_325_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_326_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_326_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_327_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_327_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_328_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_328_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_329_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_329_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_330_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_330_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_331_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_331_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_332_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_332_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_333_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_333_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_334_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_334_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_335_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_335_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_336_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_336_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_337_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmsub_337_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_338_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmsub_338_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_339_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_339_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_340_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFE
|
|
|
|
test_fmsub_340_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_341_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_341_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_342_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_342_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_343_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_343_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_344_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_344_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_345_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_345_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_346_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_346_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_347_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_347_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_348_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_348_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_349_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_349_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_350_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_350_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_351_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000002
|
|
|
|
test_fmsub_351_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000002
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_352_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x8010000000000000
|
|
|
|
test_fmsub_352_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x8010000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_353_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_353_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_354_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_354_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_355_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_355_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_356_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_356_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_357_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_357_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_358_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_358_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_359_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_359_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_360_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_360_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_361_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000080000000
|
|
|
|
test_fmsub_361_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000080000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_362_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000080000000
|
|
|
|
test_fmsub_362_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000080000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_363_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000080000001
|
|
|
|
test_fmsub_363_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000080000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_364_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x801000007FFFFFFF
|
|
|
|
test_fmsub_364_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x801000007FFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_365_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_365_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_366_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_366_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_367_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_367_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_368_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_368_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_369_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_369_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_370_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_370_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_371_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_371_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_372_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_372_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_373_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFF
|
|
|
|
test_fmsub_373_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_374_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFF
|
|
|
|
test_fmsub_374_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_375_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFE
|
|
|
|
test_fmsub_375_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_376_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFF80000000
|
|
|
|
test_fmsub_376_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFF80000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_377_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_377_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_378_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_378_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_379_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_379_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_380_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_380_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_381_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_381_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_382_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_382_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_383_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_383_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_384_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_384_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_385_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_385_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_386_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_386_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_387_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_387_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_388_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_388_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_389_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_389_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_390_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_390_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_391_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_391_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_392_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_392_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_393_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_393_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_394_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_394_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_395_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_395_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_396_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_396_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_397_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_397_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_398_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_398_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_399_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_399_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_400_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_400_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_401_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_401_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_402_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_402_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_403_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_403_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_404_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_404_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_405_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_405_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_406_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_406_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_407_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_407_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_408_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_408_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_409_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_409_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_410_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_410_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_411_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_411_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_412_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_412_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_413_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_413_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_414_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_414_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_415_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_415_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_416_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_416_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_417_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_417_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_418_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_418_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_419_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_419_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_420_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_420_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_421_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_421_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_422_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_422_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_423_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_423_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_424_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_424_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_425_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_425_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_426_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_426_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_427_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_427_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_428_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_428_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_429_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_429_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_430_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_430_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_431_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_431_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_432_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_432_cr_GEN:
|
|
#_ REGISTER_IN f1 0x0000000000000001
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x0000000000000001
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_433_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_433_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_434_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_434_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_435_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_435_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_436_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_436_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_437_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_437_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_438_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_438_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_439_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_439_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_440_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_440_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_441_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_441_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_442_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_442_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_443_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_443_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_444_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_444_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_445_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmsub_445_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_446_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_446_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_447_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_447_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_448_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_448_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_449_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_449_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_450_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_450_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_451_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_451_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_452_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_452_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_453_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_453_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_454_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_454_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_455_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_455_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_456_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_456_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_457_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_457_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_458_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_458_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_459_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_459_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_460_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_460_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_461_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_461_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_462_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_462_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_463_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_463_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_464_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_464_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_465_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_465_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_466_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_466_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_467_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_467_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_468_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_468_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_469_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_469_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_470_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_470_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_471_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_471_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_472_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_472_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_473_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_473_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_474_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_474_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_475_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_475_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_476_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_476_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_477_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_477_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_478_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_478_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_479_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_479_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_480_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_480_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_481_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmsub_481_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_482_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmsub_482_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_483_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFE
|
|
|
|
test_fmsub_483_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_484_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_484_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_485_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_485_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_486_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_486_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_487_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_487_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_488_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_488_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_489_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_489_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_490_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_490_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_491_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_491_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_492_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_492_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_493_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_493_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_494_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_494_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_495_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8010000000000000
|
|
|
|
test_fmsub_495_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8010000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_496_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x801FFFFFFFFFFFFE
|
|
|
|
test_fmsub_496_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x801FFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_497_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_497_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_498_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_498_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_499_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_499_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_500_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_500_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_501_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_501_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_502_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_502_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_503_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_503_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_504_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_504_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_505_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
|
|
test_fmsub_505_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_506_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
|
|
test_fmsub_506_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_507_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
|
|
test_fmsub_507_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_508_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x82000000001FFFFF
|
|
|
|
test_fmsub_508_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x82000000001FFFFF
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_509_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_509_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_510_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_510_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_511_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_511_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_512_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_512_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_513_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_513_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_514_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_514_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_515_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_515_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_516_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_516_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_517_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
|
|
test_fmsub_517_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_518_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
|
|
test_fmsub_518_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_519_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
|
|
test_fmsub_519_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_520_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFF7FFFFE
|
|
|
|
test_fmsub_520_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFF7FFFFE
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_521_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_521_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_522_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_522_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_523_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_523_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_524_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_524_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_525_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_525_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_526_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_526_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_527_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_527_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_528_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_528_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_529_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_529_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_530_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_530_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_531_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_531_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_532_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_532_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_533_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_533_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_534_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_534_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_535_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_535_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_536_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_536_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_537_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_537_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_538_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_538_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_539_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_539_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_540_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_540_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_541_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_541_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_542_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_542_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_543_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_543_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_544_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_544_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_545_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_545_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_546_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_546_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_547_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_547_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_548_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_548_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_549_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_549_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_550_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_550_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_551_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_551_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_552_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_552_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_553_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_553_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_554_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_554_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_555_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_555_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_556_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_556_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_557_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_557_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_558_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_558_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_559_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_559_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_560_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_560_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_561_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_561_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_562_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_562_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_563_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_563_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_564_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_564_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_565_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_565_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_566_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_566_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_567_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_567_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_568_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_568_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_569_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_569_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_570_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_570_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_571_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_571_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_572_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_572_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_573_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_573_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_574_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_574_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_575_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_575_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_576_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_576_cr_GEN:
|
|
#_ REGISTER_IN f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_577_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_577_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_578_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_578_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_579_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_579_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_580_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_580_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_581_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_581_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_582_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_582_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_583_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_583_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_584_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_584_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_585_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_585_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_586_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_586_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_587_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_587_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_588_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_588_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_589_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmsub_589_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_590_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_590_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_591_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_591_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_592_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_592_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_593_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_593_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_594_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_594_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_595_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_595_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_596_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_596_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_597_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_597_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_598_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_598_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_599_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_599_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_600_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_600_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_601_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmsub_601_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_602_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
|
|
test_fmsub_602_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_603_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_603_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_604_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFE
|
|
|
|
test_fmsub_604_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_605_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_605_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_606_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_606_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_607_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_607_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_608_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_608_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_609_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_609_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_610_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_610_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_611_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_611_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_612_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_612_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_613_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmsub_613_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_614_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
|
|
test_fmsub_614_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_615_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFE
|
|
|
|
test_fmsub_615_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x000FFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_616_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_616_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_617_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_617_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_618_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_618_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_619_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_619_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_620_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_620_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_621_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_621_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_622_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_622_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_623_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_623_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_624_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_624_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_625_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_625_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_626_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_626_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_627_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_627_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_628_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_628_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_629_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_629_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_630_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x4000000000000000
|
|
|
|
test_fmsub_630_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x4000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_631_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000200000
|
|
|
|
test_fmsub_631_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000200000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_632_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFF800000
|
|
|
|
test_fmsub_632_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_633_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_633_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_634_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_634_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_635_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_635_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_636_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_636_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_637_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_637_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_638_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_638_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_639_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_639_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_640_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_640_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_641_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC000000000000000
|
|
|
|
test_fmsub_641_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_642_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_642_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_643_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmsub_643_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_644_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmsub_644_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_645_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_645_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_646_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_646_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_647_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_647_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_648_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_648_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_649_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmsub_649_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_650_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmsub_650_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_651_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmsub_651_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_652_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmsub_652_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_653_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000200000
|
|
|
|
test_fmsub_653_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000200000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_654_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_654_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_655_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_655_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_656_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1EFFFFFFFE00000
|
|
|
|
test_fmsub_656_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1EFFFFFFFE00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_657_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_657_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_658_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_658_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_659_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_659_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_660_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_660_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_661_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmsub_661_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_662_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmsub_662_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_663_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmsub_663_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_664_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmsub_664_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_665_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFF800000
|
|
|
|
test_fmsub_665_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_666_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_666_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_667_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41EFFFFFFFE00000
|
|
|
|
test_fmsub_667_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41EFFFFFFFE00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_668_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_668_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_669_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_669_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_670_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_670_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_671_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_671_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_672_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_672_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_673_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_673_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_674_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_674_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_675_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_675_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_676_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_676_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_677_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_677_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_678_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_678_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_679_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_679_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_680_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_680_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_681_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_681_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_682_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_682_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_683_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_683_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_684_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_684_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_685_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_685_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_686_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_686_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_687_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_687_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_688_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_688_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_689_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_689_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_690_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_690_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_691_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_691_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_692_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_692_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_693_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_693_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_694_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_694_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_695_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_695_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_696_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_696_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_697_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_697_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_698_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_698_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_699_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_699_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_700_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_700_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_701_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_701_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_702_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_702_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_703_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_703_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_704_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_704_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_705_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_705_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_706_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_706_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_707_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_707_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_708_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_708_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_709_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_709_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_710_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_710_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_711_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_711_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_712_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_712_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_713_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_713_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_714_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_714_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_715_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_715_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_716_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_716_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_717_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_717_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_718_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_718_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_719_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_719_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_720_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_720_cr_GEN:
|
|
#_ REGISTER_IN f1 0x3FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x3FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_721_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmsub_721_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_722_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_722_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_723_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_723_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_724_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_724_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_725_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_725_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_726_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_726_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_727_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_727_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_728_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_728_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_729_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_729_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_730_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_730_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_731_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_731_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_732_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_732_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_733_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_733_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_734_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_734_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_735_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_735_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_736_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_736_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_737_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_737_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_738_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_738_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_739_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_739_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_740_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_740_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_741_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_741_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_742_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_742_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_743_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_743_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_744_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_744_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_745_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_745_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_746_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_746_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_747_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000002
|
|
|
|
test_fmsub_747_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000002
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_748_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x8010000000000000
|
|
|
|
test_fmsub_748_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x8010000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_749_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_749_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_750_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_750_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_751_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_751_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_752_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_752_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_753_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_753_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_754_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_754_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_755_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_755_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_756_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_756_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_757_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_757_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_758_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_758_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_759_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8010000000000000
|
|
|
|
test_fmsub_759_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8010000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_760_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x801FFFFFFFFFFFFE
|
|
|
|
test_fmsub_760_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x801FFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_761_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_761_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_762_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_762_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_763_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_763_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_764_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_764_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_765_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_765_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_766_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_766_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_767_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_767_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_768_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_768_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_769_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_769_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_770_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_770_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_771_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_771_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_772_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_772_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_773_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC000000000000000
|
|
|
|
test_fmsub_773_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_774_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_774_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_775_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmsub_775_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_776_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmsub_776_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_777_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_777_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_778_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_778_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_779_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_779_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_780_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_780_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_781_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_781_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_782_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_782_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_783_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_783_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_784_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_784_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_785_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_785_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_786_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x4000000000000000
|
|
|
|
test_fmsub_786_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x4000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_787_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000200000
|
|
|
|
test_fmsub_787_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000200000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_788_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFF800000
|
|
|
|
test_fmsub_788_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_789_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_789_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_790_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_790_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_791_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_791_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_792_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_792_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_793_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_793_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_794_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_794_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_795_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_795_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_796_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_796_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_797_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmsub_797_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_798_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000200000
|
|
|
|
test_fmsub_798_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000200000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_799_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41F0000000000000
|
|
|
|
test_fmsub_799_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41F0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_800_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_800_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_801_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_801_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_802_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_802_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_803_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_803_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_804_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_804_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_805_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_805_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_806_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_806_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_807_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_807_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_808_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_808_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_809_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmsub_809_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_810_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFF800000
|
|
|
|
test_fmsub_810_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_811_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_811_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_812_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1EFFFFFFFC00000
|
|
|
|
test_fmsub_812_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1EFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_813_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_813_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_814_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_814_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_815_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_815_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_816_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_816_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_817_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_817_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_818_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_818_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_819_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_819_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_820_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_820_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_821_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_821_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_822_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_822_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_823_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_823_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_824_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_824_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_825_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_825_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_826_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_826_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_827_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_827_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_828_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_828_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_829_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_829_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_830_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_830_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_831_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_831_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_832_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_832_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_833_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_833_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_834_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_834_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_835_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_835_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_836_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_836_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_837_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_837_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_838_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_838_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_839_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_839_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_840_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_840_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_841_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_841_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_842_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_842_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_843_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_843_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_844_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_844_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_845_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_845_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_846_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_846_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_847_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_847_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_848_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_848_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_849_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_849_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_850_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_850_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_851_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_851_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_852_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_852_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_853_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_853_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_854_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_854_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_855_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_855_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_856_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_856_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_857_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_857_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_858_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_858_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_859_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_859_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_860_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_860_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_861_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_861_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_862_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_862_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_863_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_863_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_864_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_864_cr_GEN:
|
|
#_ REGISTER_IN f1 0xBFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xBFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_865_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmsub_865_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_866_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_866_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_867_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_867_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_868_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_868_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_869_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_869_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_870_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_870_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_871_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_871_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_872_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_872_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_873_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_873_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_874_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_874_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_875_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_875_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_876_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_876_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_877_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_877_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_878_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_878_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_879_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_879_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_880_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_880_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_881_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_881_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_882_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_882_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_883_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_883_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_884_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_884_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_885_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_885_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_886_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_886_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_887_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_887_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_888_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_888_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_889_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000080000000
|
|
|
|
test_fmsub_889_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000080000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_890_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000080000000
|
|
|
|
test_fmsub_890_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000080000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_891_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000080000001
|
|
|
|
test_fmsub_891_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000080000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_892_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x801000007FFFFFFF
|
|
|
|
test_fmsub_892_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x801000007FFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_893_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_893_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_894_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_894_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_895_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_895_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_896_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_896_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_897_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_897_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_898_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_898_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_899_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_899_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_900_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_900_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_901_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
|
|
test_fmsub_901_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_902_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
|
|
test_fmsub_902_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_903_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
|
|
test_fmsub_903_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x81FFFFFFFFFFFFFE
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_904_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x82000000001FFFFF
|
|
|
|
test_fmsub_904_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x82000000001FFFFF
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_905_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_905_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_906_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_906_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_907_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_907_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_908_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_908_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_909_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_909_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_910_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_910_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_911_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_911_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_912_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_912_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_913_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmsub_913_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_914_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmsub_914_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_915_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmsub_915_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_916_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmsub_916_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_917_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000200000
|
|
|
|
test_fmsub_917_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000200000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_918_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_918_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_919_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_919_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_920_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1EFFFFFFFE00000
|
|
|
|
test_fmsub_920_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1EFFFFFFFE00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_921_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_921_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_922_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_922_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_923_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_923_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_924_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_924_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_925_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_925_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_926_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_926_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_927_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_927_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_928_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_928_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_929_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmsub_929_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_930_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000200000
|
|
|
|
test_fmsub_930_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000200000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_931_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41F0000000000000
|
|
|
|
test_fmsub_931_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41F0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_932_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_932_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_933_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_933_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_934_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_934_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_935_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_935_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_936_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_936_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_937_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
|
|
test_fmsub_937_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_938_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
|
|
test_fmsub_938_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_939_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
|
|
test_fmsub_939_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_940_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
|
|
test_fmsub_940_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_941_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
|
|
test_fmsub_941_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_942_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
|
|
test_fmsub_942_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x43D0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_943_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x43D0000000200000
|
|
|
|
test_fmsub_943_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x43D0000000200000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_944_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFFC00000
|
|
|
|
test_fmsub_944_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_945_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_945_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_946_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_946_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_947_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_947_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_948_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_948_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_949_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmsub_949_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_950_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmsub_950_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_951_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmsub_951_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_952_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmsub_952_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_953_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmsub_953_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_954_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmsub_954_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_955_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFF800000
|
|
|
|
test_fmsub_955_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_956_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC3D0000000000000
|
|
|
|
test_fmsub_956_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC3D0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_957_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_957_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_958_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_958_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_959_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_959_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_960_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_960_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_961_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_961_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_962_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_962_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_963_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_963_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_964_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_964_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_965_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_965_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_966_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_966_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_967_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_967_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_968_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_968_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_969_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_969_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_970_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_970_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_971_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_971_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_972_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_972_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_973_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_973_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_974_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_974_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_975_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_975_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_976_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_976_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_977_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_977_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_978_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_978_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_979_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_979_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_980_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_980_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_981_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_981_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_982_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_982_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_983_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_983_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_984_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_984_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_985_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_985_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_986_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_986_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_987_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_987_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_988_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_988_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_989_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_989_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_990_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_990_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_991_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_991_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_992_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_992_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_993_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_993_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_994_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_994_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_995_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_995_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_996_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_996_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_997_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_997_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_998_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_998_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_999_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_999_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1000_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1000_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1001_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1001_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1002_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1002_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1003_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1003_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1004_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1004_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1005_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1005_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1006_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1006_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1007_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1007_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1008_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1008_cr_GEN:
|
|
#_ REGISTER_IN f1 0xC1E0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xC1E0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1009_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_1009_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1010_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_1010_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1011_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_1011_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1012_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_1012_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1013_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_1013_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1014_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_1014_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1015_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_1015_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1016_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_1016_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1017_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1017_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1018_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1018_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1019_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1019_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1020_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1020_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1021_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
|
|
test_fmsub_1021_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x8000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1022_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_1022_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1023_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
|
|
test_fmsub_1023_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x8000000000000001
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1024_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
|
|
test_fmsub_1024_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1025_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_1025_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1026_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_1026_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1027_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_1027_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1028_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_1028_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1029_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1029_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1030_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1030_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1031_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1031_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1032_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1032_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1033_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFF
|
|
|
|
test_fmsub_1033_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1034_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFF
|
|
|
|
test_fmsub_1034_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFF
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1035_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFE
|
|
|
|
test_fmsub_1035_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x000000007FFFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1036_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFF80000000
|
|
|
|
test_fmsub_1036_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x800FFFFF80000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1037_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_1037_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1038_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_1038_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1039_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_1039_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1040_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_1040_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1041_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1041_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1042_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1042_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1043_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1043_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1044_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1044_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1045_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
|
|
test_fmsub_1045_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1046_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
|
|
test_fmsub_1046_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1047_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
|
|
test_fmsub_1047_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFFBFFFFE
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1048_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFF7FFFFE
|
|
|
|
test_fmsub_1048_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x01FFFFFFFF7FFFFE
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1049_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
|
|
test_fmsub_1049_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xBFF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1050_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_1050_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1051_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_1051_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1052_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_1052_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1053_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1053_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1054_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1054_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1055_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1055_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1056_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1056_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1057_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmsub_1057_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1058_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmsub_1058_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1059_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmsub_1059_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1060_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
|
|
test_fmsub_1060_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1061_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFF800000
|
|
|
|
test_fmsub_1061_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x41DFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1062_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
|
|
test_fmsub_1062_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x41E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1063_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41EFFFFFFFE00000
|
|
|
|
test_fmsub_1063_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x41EFFFFFFFE00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1064_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
|
|
test_fmsub_1064_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x0000000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1065_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1065_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1066_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1066_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1067_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1067_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1068_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1068_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1069_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_1069_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1070_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_1070_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1071_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_1071_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1072_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
|
|
test_fmsub_1072_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1073_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
|
|
test_fmsub_1073_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1E0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1074_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFF800000
|
|
|
|
test_fmsub_1074_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC1DFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1075_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
|
|
test_fmsub_1075_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x3FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1076_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1EFFFFFFFC00000
|
|
|
|
test_fmsub_1076_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC1EFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1077_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1077_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1078_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1078_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1079_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1079_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1080_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1080_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1081_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmsub_1081_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1082_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmsub_1082_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1083_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmsub_1083_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1084_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmsub_1084_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1085_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmsub_1085_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1086_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
|
|
test_fmsub_1086_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1087_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFF800000
|
|
|
|
test_fmsub_1087_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xC3CFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1088_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC3D0000000000000
|
|
|
|
test_fmsub_1088_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xC3D0000000000000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1089_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1089_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1090_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1090_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1091_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1091_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1092_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1092_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1093_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
|
|
test_fmsub_1093_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1094_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
|
|
test_fmsub_1094_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1095_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
|
|
test_fmsub_1095_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1096_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
|
|
test_fmsub_1096_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1097_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
|
|
test_fmsub_1097_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1098_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
|
|
test_fmsub_1098_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF800000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1099_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFFC00000
|
|
|
|
test_fmsub_1099_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFFC00000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1100_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF400000
|
|
|
|
test_fmsub_1100_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x43CFFFFFFF400000
|
|
#_ REGISTER_OUT cr 0x08000000
|
|
|
|
test_fmsub_1101_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1101_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1102_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1102_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1103_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1103_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1104_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1104_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1105_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1105_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1106_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1106_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1107_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1107_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1108_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1108_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1109_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1109_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1110_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1110_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1111_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1111_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1112_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1112_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1113_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1113_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1114_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1114_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1115_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1115_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1116_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1116_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1117_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1117_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1118_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1118_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1119_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1119_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1120_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1120_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1121_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1121_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1122_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1122_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1123_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1123_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1124_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1124_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1125_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1125_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1126_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1126_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1127_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1127_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1128_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1128_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1129_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1129_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1130_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1130_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1131_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1131_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1132_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1132_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1133_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1133_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1134_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1134_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1135_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1135_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1136_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1136_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1137_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1137_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1138_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1138_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1139_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1139_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1140_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1140_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1141_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1141_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1142_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1142_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1143_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1143_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1144_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1144_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1145_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1145_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1146_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1146_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1147_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1147_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1148_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1148_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1149_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1149_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1150_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1150_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1151_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1151_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1152_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1152_cr_GEN:
|
|
#_ REGISTER_IN f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1153_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1153_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1154_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1154_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1155_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1155_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1156_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1156_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1157_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1157_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1158_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1158_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1159_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1159_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1160_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1160_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1161_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1161_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1162_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1162_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1163_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1163_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1164_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1164_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1165_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1165_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1166_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1166_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1167_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1167_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1168_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1168_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1169_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1169_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1170_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1170_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1171_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1171_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1172_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1172_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1173_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1173_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1174_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1174_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1175_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1175_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1176_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1176_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1177_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1177_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1178_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1178_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1179_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1179_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1180_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1180_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1181_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1181_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1182_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1182_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1183_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1183_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1184_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1184_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1185_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1185_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1186_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1186_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1187_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1187_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1188_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1188_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1189_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1189_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1190_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1190_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1191_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1191_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1192_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1192_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1193_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1193_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1194_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1194_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1195_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1195_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1196_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1196_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1197_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1197_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1198_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1198_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1199_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1199_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1200_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1200_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1201_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1201_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1202_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1202_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1203_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1203_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1204_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1204_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1205_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1205_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1206_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1206_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1207_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1207_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1208_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1208_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1209_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1209_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1210_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1210_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1211_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1211_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1212_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1212_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1213_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1213_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1214_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1214_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1215_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1215_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1216_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1216_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1217_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1217_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1218_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1218_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1219_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1219_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1220_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1220_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1221_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1221_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1222_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1222_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1223_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1223_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1224_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1224_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1225_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1225_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1226_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1226_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1227_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1227_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1228_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1228_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1229_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1229_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1230_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1230_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1231_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1231_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1232_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1232_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1233_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1233_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1234_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1234_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1235_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1235_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1236_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1236_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1237_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1237_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1238_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1238_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1239_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1239_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1240_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1240_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1241_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1241_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1242_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1242_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1243_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1243_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1244_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1244_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1245_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1245_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1246_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1246_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1247_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1247_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1248_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1248_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1249_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1249_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1250_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1250_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1251_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1251_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1252_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1252_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1253_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1253_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1254_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1254_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1255_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1255_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1256_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1256_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1257_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1257_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1258_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1258_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1259_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1259_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1260_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1260_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1261_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1261_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1262_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1262_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1263_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1263_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1264_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1264_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1265_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1265_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1266_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1266_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1267_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1267_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1268_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1268_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1269_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1269_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1270_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1270_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1271_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1271_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1272_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1272_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1273_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1273_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1274_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1274_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1275_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1275_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1276_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1276_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1277_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1277_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1278_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1278_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1279_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1279_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1280_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1280_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1281_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1281_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1282_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1282_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1283_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1283_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1284_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1284_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1285_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1285_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1286_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1286_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1287_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1287_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1288_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1288_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1289_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1289_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1290_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1290_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1291_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1291_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1292_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1292_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1293_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1293_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1294_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1294_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1295_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1295_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1296_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1296_cr_GEN:
|
|
#_ REGISTER_IN f1 0x7FF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0x7FF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1297_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1297_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1298_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1298_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1299_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1299_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1300_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1300_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1301_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1301_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1302_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1302_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1303_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1303_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1304_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1304_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1305_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1305_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1306_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1306_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1307_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1307_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1308_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1308_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1309_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1309_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1310_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1310_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1311_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1311_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1312_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1312_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1313_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1313_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1314_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1314_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1315_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1315_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1316_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1316_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1317_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1317_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1318_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1318_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1319_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1319_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1320_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1320_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1321_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1321_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1322_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1322_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1323_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1323_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1324_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1324_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1325_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1325_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1326_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1326_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1327_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1327_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1328_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1328_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1329_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1329_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1330_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1330_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1331_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1331_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1332_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1332_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1333_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1333_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1334_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1334_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1335_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1335_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1336_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1336_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1337_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1337_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1338_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1338_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1339_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1339_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1340_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1340_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1341_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1341_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1342_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1342_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1343_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1343_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1344_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1344_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1345_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1345_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1346_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1346_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1347_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1347_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1348_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1348_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1349_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1349_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1350_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1350_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1351_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1351_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1352_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1352_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1353_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1353_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1354_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1354_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1355_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1355_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1356_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1356_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1357_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1357_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1358_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1358_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1359_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1359_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1360_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1360_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1361_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1361_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1362_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1362_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1363_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1363_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1364_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1364_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1365_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1365_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1366_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1366_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1367_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1367_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1368_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1368_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1369_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1369_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1370_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1370_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1371_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1371_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1372_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1372_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1373_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1373_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1374_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1374_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1375_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1375_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1376_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1376_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1377_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1377_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1378_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1378_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1379_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1379_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1380_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1380_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1381_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1381_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1382_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1382_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1383_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1383_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1384_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1384_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1385_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1385_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1386_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1386_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1387_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1387_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1388_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1388_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1389_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1389_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1390_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1390_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1391_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1391_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1392_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1392_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1393_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1393_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1394_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1394_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1395_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1395_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1396_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1396_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1397_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1397_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1398_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1398_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1399_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1399_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1400_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1400_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1401_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
|
|
test_fmsub_1401_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1402_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1402_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1403_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1403_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1404_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1404_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1405_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1405_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1406_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1406_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1407_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1407_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1408_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1408_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1409_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1409_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1410_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1410_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1411_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1411_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1412_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1412_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1413_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
|
|
test_fmsub_1413_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1414_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
|
|
test_fmsub_1414_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0x7FF0000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1415_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1415_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1416_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1416_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1417_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1417_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1418_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1418_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1419_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1419_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1420_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1420_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1421_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1421_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1422_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1422_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1423_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1423_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1424_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1424_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1425_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1425_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1426_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1426_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1427_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1427_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1428_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1428_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1429_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1429_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1430_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1430_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1431_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1431_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1432_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1432_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1433_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1433_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1434_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1434_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1435_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1435_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1436_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1436_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1437_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1437_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1438_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1438_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1439_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1439_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1440_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1440_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF0000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF0000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1441_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1441_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1442_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1442_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1443_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1443_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1444_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1444_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1445_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1445_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1446_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1446_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1447_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1447_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1448_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1448_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1449_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1449_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1450_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1450_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1451_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1451_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1452_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1452_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1453_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1453_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1454_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1454_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1455_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1455_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1456_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1456_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1457_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1457_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1458_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1458_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1459_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1459_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1460_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1460_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1461_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1461_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1462_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1462_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1463_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1463_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1464_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1464_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1465_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1465_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1466_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1466_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1467_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1467_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1468_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1468_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1469_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1469_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1470_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1470_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1471_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1471_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1472_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1472_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1473_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1473_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1474_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1474_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1475_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1475_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1476_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1476_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1477_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1477_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1478_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1478_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1479_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1479_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1480_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1480_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1481_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1481_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1482_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1482_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1483_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1483_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1484_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1484_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1485_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1485_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1486_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1486_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1487_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1487_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1488_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1488_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1489_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1489_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1490_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1490_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1491_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1491_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1492_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1492_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1493_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1493_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1494_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1494_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1495_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1495_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1496_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1496_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1497_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1497_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1498_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1498_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1499_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1499_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1500_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1500_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1501_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1501_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1502_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1502_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1503_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1503_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1504_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1504_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1505_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1505_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1506_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1506_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1507_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1507_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1508_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1508_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1509_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1509_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1510_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1510_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1511_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1511_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1512_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1512_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1513_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1513_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1514_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1514_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1515_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1515_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1516_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1516_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1517_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1517_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1518_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1518_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1519_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1519_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1520_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1520_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1521_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1521_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1522_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1522_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1523_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1523_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1524_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1524_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1525_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1525_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1526_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1526_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1527_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1527_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1528_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1528_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1529_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1529_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1530_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1530_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1531_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1531_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1532_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1532_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1533_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1533_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1534_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1534_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1535_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1535_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1536_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1536_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1537_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1537_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1538_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1538_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1539_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1539_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1540_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1540_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1541_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1541_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1542_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1542_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1543_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1543_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1544_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1544_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1545_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1545_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1546_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1546_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1547_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1547_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1548_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1548_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1549_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1549_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1550_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1550_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1551_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1551_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1552_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1552_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1553_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1553_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1554_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1554_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1555_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1555_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1556_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1556_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1557_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1557_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1558_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1558_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1559_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1559_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1560_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1560_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1561_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1561_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1562_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1562_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1563_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1563_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1564_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1564_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1565_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1565_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1566_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1566_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1567_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1567_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1568_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1568_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1569_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1569_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1570_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1570_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1571_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1571_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x00000000
|
|
|
|
test_fmsub_1572_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1572_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1573_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1573_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1574_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1574_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1575_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1575_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1576_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1576_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1577_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1577_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1578_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1578_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1579_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1579_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1580_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1580_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1581_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1581_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1582_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1582_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1583_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1583_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1584_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
|
|
test_fmsub_1584_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF8000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF8000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFF8000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1585_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1585_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1586_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1586_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1587_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1587_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1588_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1588_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1589_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1589_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1590_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1590_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1591_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1591_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1592_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1592_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1593_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1593_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1594_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1594_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1595_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1595_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1596_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1596_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1597_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1597_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1598_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1598_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1599_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1599_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1600_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1600_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1601_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1601_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1602_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1602_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1603_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1603_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1604_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1604_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1605_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1605_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1606_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1606_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1607_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1607_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1608_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1608_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x8000000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x8000000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1609_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1609_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1610_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1610_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1611_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1611_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1612_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1612_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1613_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1613_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1614_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1614_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1615_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1615_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1616_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1616_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1617_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1617_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1618_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1618_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1619_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1619_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1620_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1620_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x0000000000000001
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x0000000000000001
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1621_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1621_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1622_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1622_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1623_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1623_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1624_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1624_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1625_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1625_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1626_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1626_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1627_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1627_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1628_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1628_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1629_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1629_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1630_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1630_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1631_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1631_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1632_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1632_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1633_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1633_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1634_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1634_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1635_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1635_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1636_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1636_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1637_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1637_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1638_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1638_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1639_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1639_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1640_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1640_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1641_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1641_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1642_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1642_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1643_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1643_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1644_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1644_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x3FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x3FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1645_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1645_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1646_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1646_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1647_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1647_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1648_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1648_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1649_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1649_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1650_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1650_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1651_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1651_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1652_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1652_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1653_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1653_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1654_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1654_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1655_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1655_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1656_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1656_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xBFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xBFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1657_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1657_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1658_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1658_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1659_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1659_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1660_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1660_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1661_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1661_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1662_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1662_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1663_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1663_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1664_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1664_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1665_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1665_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1666_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1666_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1667_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1667_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1668_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1668_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xC1E0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xC1E0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1669_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1669_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1670_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1670_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1671_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1671_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1672_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1672_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1673_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1673_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1674_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1674_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1675_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1675_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1676_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1676_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1677_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1677_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1678_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1678_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1679_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1679_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1680_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1680_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1681_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1681_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1682_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1682_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1683_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1683_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1684_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1684_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1685_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1685_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1686_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1686_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1687_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1687_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1688_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1688_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1689_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1689_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1690_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1690_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1691_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1691_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1692_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1692_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0x7FF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0x7FF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1693_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1693_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1694_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1694_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1695_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1695_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1696_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1696_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1697_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1697_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1698_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1698_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1699_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1699_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1700_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1700_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1701_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1701_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1702_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1702_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1703_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1703_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1704_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1704_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF0000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF0000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1705_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1705_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1706_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1706_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1707_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1707_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1708_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1708_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1709_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1709_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1710_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1710_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1711_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1711_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1712_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1712_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1713_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1713_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1714_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1714_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1715_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1715_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1716_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1716_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF8000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF8000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1717_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1717_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1718_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1718_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x8000000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x8000000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1719_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1719_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x0000000000000001
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x0000000000000001
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1720_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1720_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x000FFFFFFFFFFFFF
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x000FFFFFFFFFFFFF
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1721_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1721_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x3FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x3FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1722_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1722_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xBFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xBFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1723_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1723_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xC1E0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xC1E0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1724_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1724_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x41DFFFFFFFC00000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x41DFFFFFFFC00000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1725_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1725_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0x7FF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0x7FF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1726_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1726_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF0000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF0000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1727_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1727_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF8000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF8000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|
|
test_fmsub_1728_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
|
|
test_fmsub_1728_cr_GEN:
|
|
#_ REGISTER_IN f1 0xFFF4000000000000
|
|
#_ REGISTER_IN f2 0xFFF4000000000000
|
|
#_ REGISTER_IN f3 0xFFF4000000000000
|
|
fmsub. f4, f1, f2, f3
|
|
blr
|
|
#_ REGISTER_OUT f1 0xFFF4000000000000
|
|
#_ REGISTER_OUT f2 0xFFF4000000000000
|
|
#_ REGISTER_OUT f3 0xFFF4000000000000
|
|
#_ REGISTER_OUT f4 0xFFFC000000000000
|
|
#_ REGISTER_OUT cr 0x0A000000
|
|
|