5851 lines
225 KiB
ArmAsm
5851 lines
225 KiB
ArmAsm
test_vandc_1_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_2_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_3_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_4_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
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#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_5_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_6_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
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#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_7_GEN:
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#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
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vandc v3, v1, v2
|
|
blr
|
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#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
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test_vandc_8_GEN:
|
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#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
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#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
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vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_9_GEN:
|
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#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
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#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_10_GEN:
|
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#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
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#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
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vandc v3, v1, v2
|
|
blr
|
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#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
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#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_11_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
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#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_12_GEN:
|
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#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
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vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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|
|
|
test_vandc_13_GEN:
|
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#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
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vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_14_GEN:
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#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
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vandc v3, v1, v2
|
|
blr
|
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#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
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test_vandc_15_GEN:
|
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#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
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vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
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#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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|
|
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test_vandc_16_GEN:
|
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#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
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vandc v3, v1, v2
|
|
blr
|
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#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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|
|
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test_vandc_17_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
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vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
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#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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|
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test_vandc_18_GEN:
|
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#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
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vandc v3, v1, v2
|
|
blr
|
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#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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|
|
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test_vandc_19_GEN:
|
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#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
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vandc v3, v1, v2
|
|
blr
|
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#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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|
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test_vandc_20_GEN:
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#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
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vandc v3, v1, v2
|
|
blr
|
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#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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|
|
|
test_vandc_21_GEN:
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#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
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vandc v3, v1, v2
|
|
blr
|
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#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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|
|
|
test_vandc_22_GEN:
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#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
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vandc v3, v1, v2
|
|
blr
|
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#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_23_GEN:
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#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
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vandc v3, v1, v2
|
|
blr
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#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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|
|
|
test_vandc_24_GEN:
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#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
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vandc v3, v1, v2
|
|
blr
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#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_25_GEN:
|
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#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_26_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
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#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
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#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
|
|
|
test_vandc_27_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
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#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
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|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
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#_ REGISTER_OUT v3 [00000000, 00000001, 00000001, 00000001]
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|
|
|
test_vandc_28_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
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#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_29_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
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#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
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|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_30_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
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#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_31_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
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#_ REGISTER_OUT v3 [00000001, 00000001, 00000000, 00000000]
|
|
|
|
test_vandc_32_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
|
|
|
test_vandc_33_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
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|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_34_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
|
|
|
test_vandc_35_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
|
|
|
test_vandc_36_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00000001, 00000000, 00000001, 00000001]
|
|
|
|
test_vandc_37_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000000, 00000000]
|
|
|
|
test_vandc_38_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
|
|
|
test_vandc_39_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_40_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000000, 00000000]
|
|
|
|
test_vandc_41_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000000, 00000000]
|
|
|
|
test_vandc_42_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
|
|
|
test_vandc_43_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_44_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_45_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
|
|
|
test_vandc_46_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_47_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000001, 00000000, 00000000, 00000001]
|
|
|
|
test_vandc_48_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000001]
|
|
|
|
test_vandc_49_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000001, 00000000, 00000000, 00000001]
|
|
|
|
test_vandc_50_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_51_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
|
|
test_vandc_52_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [0000FFFE, FFFF0000, 00000000, FFFF0000]
|
|
|
|
test_vandc_53_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [0000FDFC, FBFA0000, 00000000, F3F20000]
|
|
|
|
test_vandc_54_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [0000FFF2, FFF20000, 00000000, FFF20000]
|
|
|
|
test_vandc_55_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [0000DDCC, BBAA0000, 00000000, 33220000]
|
|
|
|
test_vandc_56_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [000000FF, FFFF0000, 00000000, 00000000]
|
|
|
|
test_vandc_57_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [0000FBFB, FBFB0000, 00000000, FBFB0000]
|
|
|
|
test_vandc_58_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [0000F8F8, F8F80000, 00000000, F8F80000]
|
|
|
|
test_vandc_59_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [0000F7F7, F7F70000, 00000000, F7F70000]
|
|
|
|
test_vandc_60_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [0000EDED, EDED0000, 00000000, EDED0000]
|
|
|
|
test_vandc_61_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [0000A987, 789A0000, 00000000, AA990000]
|
|
|
|
test_vandc_62_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [0000FFFF, C03F0000, 00000000, C00C0000]
|
|
|
|
test_vandc_63_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [0000FFFF, 3EDF0000, 00000000, 3E8F0000]
|
|
|
|
test_vandc_64_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [0000FDFC, FBFA0000, 00000000, F3F20000]
|
|
|
|
test_vandc_65_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [0000EFEF, 7F700000, 00000000, 70000000]
|
|
|
|
test_vandc_66_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [0000FFFF, 403F0000, 00000000, 400C0000]
|
|
|
|
test_vandc_67_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [0000FFFF, BE5F0000, 00000000, BE0F0000]
|
|
|
|
test_vandc_68_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00003232, 32320000, 00000000, FBFE0000]
|
|
|
|
test_vandc_69_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000504, 03020000, 00000000, FBFA0000]
|
|
|
|
test_vandc_70_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000101, 01010000, 00000000, 01010000]
|
|
|
|
test_vandc_71_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000002, 00010000, 00000000, FFFD0000]
|
|
|
|
test_vandc_72_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000081, FFFD0000, 00000000, FFFC0000]
|
|
|
|
test_vandc_73_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000FEFE, 8F8F0000, 00000000, FFFF0000]
|
|
|
|
test_vandc_74_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [0000007F, FFFF0000, 00000000, FFFE0000]
|
|
|
|
test_vandc_75_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_76_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
|
|
test_vandc_77_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00010202, 04050606, 08090A0A, 0C0D0E0E]
|
|
|
|
test_vandc_78_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00010000, 00000607, 08090A0B, 00000E0F]
|
|
|
|
test_vandc_79_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00000202, 04000602, 08000A02, 0C000E02]
|
|
|
|
test_vandc_80_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_81_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00000003, 04050007, 00090A00, 00000E00]
|
|
|
|
test_vandc_82_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [00010203, 00010203, 08090A0B, 08090A0B]
|
|
|
|
test_vandc_83_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 08080808, 08080808]
|
|
|
|
test_vandc_84_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [00010203, 04050607, 00010203, 04050607]
|
|
|
|
test_vandc_85_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00010001, 04050405, 08090809, 0C0D0C0D]
|
|
|
|
test_vandc_86_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00010003, 00000406, 0809080B, 08090807]
|
|
|
|
test_vandc_87_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00010203, 00050607, 00010202, 000C0C0C]
|
|
|
|
test_vandc_88_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
|
|
test_vandc_89_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00010000, 00000000, 00090000, 00000000]
|
|
|
|
test_vandc_90_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00010203, 04000607, 00000000, 00000000]
|
|
|
|
test_vandc_91_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00010203, 00050607, 00010202, 000C0C0C]
|
|
|
|
test_vandc_92_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
|
|
test_vandc_93_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000202, 00000202, 00000202, 080C0C0C]
|
|
|
|
test_vandc_94_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 08080808, 08080808]
|
|
|
|
test_vandc_95_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
|
|
|
|
test_vandc_96_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00010002, 00010000, 08090A0A, 0C0D0E0C]
|
|
|
|
test_vandc_97_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000001, 04050606, 00010002, 0C0C0E0D]
|
|
|
|
test_vandc_98_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000202, 04050000, 00000000, 0C0D0E0F]
|
|
|
|
test_vandc_99_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000003, 04050600, 00010000, 0C0C0E0F]
|
|
|
|
test_vandc_100_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_101_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
|
|
test_vandc_102_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [000D000C, 000D000C, 000D000C, 000D000C]
|
|
|
|
test_vandc_103_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [000D0000, 0000000D, 000D000D, 0000000D]
|
|
|
|
test_vandc_104_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [000C000C, 00080008, 00040004, 00000000]
|
|
|
|
test_vandc_105_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [000C000C, 00080008, 00040004, 00000000]
|
|
|
|
test_vandc_106_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [0000000D, 000D000D, 000D0000, 00000000]
|
|
|
|
test_vandc_107_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [00090009, 00090009, 00090009, 00090009]
|
|
|
|
test_vandc_108_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [00080008, 00080008, 00080008, 00080008]
|
|
|
|
test_vandc_109_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [00050005, 00050005, 00050005, 00050005]
|
|
|
|
test_vandc_110_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
|
|
test_vandc_111_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00090005, 0008000C, 000D0009, 00090005]
|
|
|
|
test_vandc_112_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [000D000D, 000D000D, 00010000, 000C000C]
|
|
|
|
test_vandc_113_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
|
|
test_vandc_114_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [000D000C, 00080008, 000D0004, 00000000]
|
|
|
|
test_vandc_115_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [0005000D, 0000000D, 00000000, 00000000]
|
|
|
|
test_vandc_116_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [000D000D, 000D000D, 00010000, 000C000C]
|
|
|
|
test_vandc_117_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
|
|
test_vandc_118_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 000C000C]
|
|
|
|
test_vandc_119_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00040004, 00000000, 000C000C, 00080008]
|
|
|
|
test_vandc_120_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
|
|
|
|
test_vandc_121_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00010000, 00010000, 000D000C, 000D000C]
|
|
|
|
test_vandc_122_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000001, 000D000C, 00010000, 000C000D]
|
|
|
|
test_vandc_123_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000000C, 000D0000, 00000000, 000D000D]
|
|
|
|
test_vandc_124_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [0000000D, 000D0000, 00010000, 000C000D]
|
|
|
|
test_vandc_125_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_126_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
|
|
test_vandc_127_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00112232, 44556676, 8899AABA, CCDDEEFE]
|
|
|
|
test_vandc_128_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00110000, 00006677, 8899AABB, 0000EEFF]
|
|
|
|
test_vandc_129_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00102030, 40506070, 8090A0B0, C0D0E0F0]
|
|
|
|
test_vandc_130_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00102232, 44506672, 8890AAB2, CCD0EEF2]
|
|
|
|
test_vandc_131_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00000033, 44550077, 0099AA00, 0000EE00]
|
|
|
|
test_vandc_132_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [00112233, 40516273, 8899AABB, C8D9EAFB]
|
|
|
|
test_vandc_133_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [00102030, 40506070, 8898A8B8, C8D8E8F8]
|
|
|
|
test_vandc_134_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [00112233, 44556677, 8091A2B3, C4D5E6F7]
|
|
|
|
test_vandc_135_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00012021, 44456465, 8889A8A9, CCCDECED]
|
|
|
|
test_vandc_136_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00012003, 40102456, 889988BB, 88998877]
|
|
|
|
test_vandc_137_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00112233, 40156677, 80112232, C00CCCCC]
|
|
|
|
test_vandc_138_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00112233, 04556677, 8889AABB, 0C8DEEFF]
|
|
|
|
test_vandc_139_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00112030, 40506070, 8019A0B0, C0D0E0F0]
|
|
|
|
test_vandc_140_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00112223, 44506677, 80000000, 40000000]
|
|
|
|
test_vandc_141_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00112233, 40156677, 00112232, 400CCCCC]
|
|
|
|
test_vandc_142_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00112233, 04556677, 0819AABB, 8C0DEEFF]
|
|
|
|
test_vandc_143_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00102232, 00102232, 00102232, C8DCECFC]
|
|
|
|
test_vandc_144_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 8898A8B8, C8D8E8F8]
|
|
|
|
test_vandc_145_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
|
|
|
|
test_vandc_146_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00010002, 00010000, 8899AABA, CCDDEEFC]
|
|
|
|
test_vandc_147_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000001, 44556676, 00010082, CCDCEE7D]
|
|
|
|
test_vandc_148_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00002232, 04050000, 00000000, CCDDEEFF]
|
|
|
|
test_vandc_149_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000033, 44556600, 00010080, CCDCEE7F]
|
|
|
|
test_vandc_150_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_151_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
|
|
test_vandc_152_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FE, FFFF00FE]
|
|
|
|
test_vandc_153_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00FF0000, 0000FF00, FF0000FF, 000000FF]
|
|
|
|
test_vandc_154_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00FEFD00, 0000F900, F70000F4, F3F200F0]
|
|
|
|
test_vandc_155_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00F2FF00, 0000FF00, FF0000F2, FFF200F2]
|
|
|
|
test_vandc_156_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00EEDD00, 00009900, 77000044, 33220000]
|
|
|
|
test_vandc_157_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [00FBFB00, 0000FB00, FB0000FB, FBFB00FB]
|
|
|
|
test_vandc_158_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [00F8F800, 0000F800, F80000F8, F8F800F8]
|
|
|
|
test_vandc_159_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [00F7F700, 0000F700, F70000F7, F7F700F7]
|
|
|
|
test_vandc_160_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00EDED00, 0000ED00, ED0000ED, EDED00ED]
|
|
|
|
test_vandc_161_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00CBA900, 0000BC00, EE0000BB, AA990077]
|
|
|
|
test_vandc_162_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [007FFF00, 0000FF00, C0000032, C00C00CC]
|
|
|
|
test_vandc_163_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00DFFF00, 0000FF00, BE0000FF, 3E8F00FF]
|
|
|
|
test_vandc_164_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [007FFD00, 0000F900, 800000F4, F3F200F0]
|
|
|
|
test_vandc_165_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00F7EF00, 0000FF00, 80000000, 70000000]
|
|
|
|
test_vandc_166_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [007FFF00, 0000FF00, 40000032, 400C00CC]
|
|
|
|
test_vandc_167_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00DFFF00, 0000FF00, 3E0000FF, BE0F00FF]
|
|
|
|
test_vandc_168_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00323200, 00003200, 32000032, FBFE00FC]
|
|
|
|
test_vandc_169_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00060500, 00000100, FF0000FC, FBFA00F8]
|
|
|
|
test_vandc_170_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00010100, 00000100, 01000001, 01010001]
|
|
|
|
test_vandc_171_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00030000, 00000000, FF0000FE, FFFD00FC]
|
|
|
|
test_vandc_172_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00020000, 0000FF00, 00000082, FFFC007D]
|
|
|
|
test_vandc_173_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000FE00, 00000000, 00000000, FFFF00FF]
|
|
|
|
test_vandc_174_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 0000FF00, 00000080, FFFE007F]
|
|
|
|
test_vandc_175_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_176_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vandc_177_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vandc_178_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [04040000, 00000404, 04040404, 00000404]
|
|
|
|
test_vandc_179_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [04040404, 00000000, 04040404, 00000000]
|
|
|
|
test_vandc_180_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [04000400, 04000400, 04000400, 04000400]
|
|
|
|
test_vandc_181_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [04040404, 00000000, 04040404, 00000000]
|
|
|
|
test_vandc_182_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [04000004, 04040004, 00040400, 00000400]
|
|
|
|
test_vandc_183_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_184_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vandc_185_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vandc_186_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [04000004, 00000404, 04040400, 00000004]
|
|
|
|
test_vandc_187_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00040404, 00040404, 00000000, 00040404]
|
|
|
|
test_vandc_188_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vandc_189_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00040404, 00000000, 00040404, 00000000]
|
|
|
|
test_vandc_190_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [04040404, 04000404, 00000000, 00000000]
|
|
|
|
test_vandc_191_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00040404, 00040404, 00000000, 00040404]
|
|
|
|
test_vandc_192_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vandc_193_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00040404]
|
|
|
|
test_vandc_194_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [04040404, 00000000, 04040404, 00000000]
|
|
|
|
test_vandc_195_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_196_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 04040404, 04040404]
|
|
|
|
test_vandc_197_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 04040404, 00000000, 04040404]
|
|
|
|
test_vandc_198_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000404, 04040000, 00000000, 04040404]
|
|
|
|
test_vandc_199_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000004, 04040400, 00000000, 04040404]
|
|
|
|
test_vandc_200_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_201_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707]
|
|
|
|
test_vandc_202_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [07070706, 07070706, 07070706, 07070706]
|
|
|
|
test_vandc_203_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [07070000, 00000707, 07070707, 00000707]
|
|
|
|
test_vandc_204_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [07060504, 03020100, 07060504, 03020100]
|
|
|
|
test_vandc_205_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [07020702, 07020702, 07020702, 07020702]
|
|
|
|
test_vandc_206_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [07060504, 03020100, 07060504, 03020100]
|
|
|
|
test_vandc_207_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [07000007, 07070007, 00070700, 00000700]
|
|
|
|
test_vandc_208_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [03030303, 03030303, 03030303, 03030303]
|
|
|
|
test_vandc_209_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707]
|
|
|
|
test_vandc_210_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [05050505, 05050505, 05050505, 05050505]
|
|
|
|
test_vandc_211_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [05030107, 00020406, 06050403, 02010007]
|
|
|
|
test_vandc_212_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00070707, 00070707, 00030302, 00040404]
|
|
|
|
test_vandc_213_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [06070707, 06070707, 06070707, 06070707]
|
|
|
|
test_vandc_214_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00070504, 03020100, 00070504, 03020100]
|
|
|
|
test_vandc_215_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [07070707, 07000707, 00000000, 00000000]
|
|
|
|
test_vandc_216_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00070707, 00070707, 00030302, 00040404]
|
|
|
|
test_vandc_217_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [06070707, 06070707, 06070707, 06070707]
|
|
|
|
test_vandc_218_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [02020202, 02020202, 02020202, 03060504]
|
|
|
|
test_vandc_219_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [07060504, 03020100, 07060504, 03020100]
|
|
|
|
test_vandc_220_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
|
|
|
|
test_vandc_221_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00030002, 00010000, 07070706, 07050704]
|
|
|
|
test_vandc_222_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00020001, 07050706, 00030002, 07040705]
|
|
|
|
test_vandc_223_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000606, 07070000, 00000000, 07070707]
|
|
|
|
test_vandc_224_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000007, 07070700, 00010000, 07060707]
|
|
|
|
test_vandc_225_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_226_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
|
|
|
|
test_vandc_227_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
|
|
|
|
test_vandc_228_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [08080000, 00000808, 08080808, 00000808]
|
|
|
|
test_vandc_229_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 00000000, 00000000]
|
|
|
|
test_vandc_230_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [08000800, 08000800, 08000800, 08000800]
|
|
|
|
test_vandc_231_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 00000000, 00000000]
|
|
|
|
test_vandc_232_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [08000008, 08080008, 00080800, 00000800]
|
|
|
|
test_vandc_233_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
|
|
|
|
test_vandc_234_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
|
|
|
|
test_vandc_235_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
|
|
|
|
test_vandc_236_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [08080800, 08080808, 08080808, 08080800]
|
|
|
|
test_vandc_237_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00080808, 00080808, 00000000, 00080808]
|
|
|
|
test_vandc_238_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
|
|
|
|
test_vandc_239_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00080808, 08080808, 00080000, 00000000]
|
|
|
|
test_vandc_240_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [08000808, 08000808, 00000000, 00000000]
|
|
|
|
test_vandc_241_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00080808, 00080808, 00000000, 00080808]
|
|
|
|
test_vandc_242_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
|
|
|
|
test_vandc_243_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 08080808]
|
|
|
|
test_vandc_244_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 08080808, 08080808]
|
|
|
|
test_vandc_245_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_246_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 08080808, 08080808]
|
|
|
|
test_vandc_247_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 08080808, 00000000, 08080808]
|
|
|
|
test_vandc_248_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000808, 08080000, 00000000, 08080808]
|
|
|
|
test_vandc_249_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000008, 08080800, 00000000, 08080808]
|
|
|
|
test_vandc_250_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_251_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212]
|
|
|
|
test_vandc_252_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212]
|
|
|
|
test_vandc_253_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [12120000, 00001212, 12121212, 00001212]
|
|
|
|
test_vandc_254_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [12121010, 12121010, 12121010, 12121010]
|
|
|
|
test_vandc_255_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212]
|
|
|
|
test_vandc_256_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [12021000, 12021000, 12021000, 12021000]
|
|
|
|
test_vandc_257_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [12000012, 12120012, 00121200, 00001200]
|
|
|
|
test_vandc_258_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212]
|
|
|
|
test_vandc_259_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [10101010, 10101010, 10101010, 10101010]
|
|
|
|
test_vandc_260_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212]
|
|
|
|
test_vandc_261_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00020002, 10121012, 02100012, 02100012]
|
|
|
|
test_vandc_262_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00121212, 00121212, 00121212, 00000000]
|
|
|
|
test_vandc_263_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [12121212, 12121212, 12021212, 12021212]
|
|
|
|
test_vandc_264_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00121010, 12121010, 00121010, 12121010]
|
|
|
|
test_vandc_265_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [12120202, 12101212, 00000000, 10000000]
|
|
|
|
test_vandc_266_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00121212, 00121212, 00121212, 00000000]
|
|
|
|
test_vandc_267_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12021212]
|
|
|
|
test_vandc_268_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121010]
|
|
|
|
test_vandc_269_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [02020000, 02020000, 12121010, 12121010]
|
|
|
|
test_vandc_270_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_271_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00020002, 00000000, 12121212, 12101210]
|
|
|
|
test_vandc_272_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00020000, 12101212, 00020002, 12101210]
|
|
|
|
test_vandc_273_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00001212, 02020000, 00000000, 12121212]
|
|
|
|
test_vandc_274_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000012, 12121200, 00000000, 12121212]
|
|
|
|
test_vandc_275_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_276_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788]
|
|
|
|
test_vandc_277_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [12345678, 87654320, 11223344, 55667788]
|
|
|
|
test_vandc_278_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [12340000, 00004321, 11223344, 00007788]
|
|
|
|
test_vandc_279_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [12345478, 83604120, 11223144, 51627180]
|
|
|
|
test_vandc_280_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [12305670, 87604320, 11223340, 55627780]
|
|
|
|
test_vandc_281_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [12245448, 83200100, 11221144, 11221100]
|
|
|
|
test_vandc_282_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [12000078, 87650021, 00223300, 00007700]
|
|
|
|
test_vandc_283_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [12305278, 83614321, 11223340, 51627388]
|
|
|
|
test_vandc_284_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [10305078, 80604020, 10203040, 50607088]
|
|
|
|
test_vandc_285_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [12345670, 87654321, 11223344, 55667780]
|
|
|
|
test_vandc_286_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00244468, 85654121, 01202144, 45646588]
|
|
|
|
test_vandc_287_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00345678, 80254321, 00223300, 40044488]
|
|
|
|
test_vandc_288_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [12145678, 06454321, 10023344, 14067788]
|
|
|
|
test_vandc_289_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00345478, 83604120, 00223144, 51627180]
|
|
|
|
test_vandc_290_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [12344668, 07604321, 00000000, 50000000]
|
|
|
|
test_vandc_291_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00345678, 00254321, 00223300, 40044488]
|
|
|
|
test_vandc_292_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [12145678, 86454321, 10023344, 14067788]
|
|
|
|
test_vandc_293_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [12301230, 02200220, 10223200, 51667588]
|
|
|
|
test_vandc_294_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [02040400, 03000100, 11223144, 51627188]
|
|
|
|
test_vandc_295_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 01010101, 01000100, 01000100]
|
|
|
|
test_vandc_296_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00010000, 11223344, 55647788]
|
|
|
|
test_vandc_297_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 87654320, 00020000, 55647708]
|
|
|
|
test_vandc_298_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00005678, 87050000, 00000000, 55667788]
|
|
|
|
test_vandc_299_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000078, 87654300, 00000000, 55667708]
|
|
|
|
test_vandc_300_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_301_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
|
|
test_vandc_302_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCC, 3FF33332]
|
|
|
|
test_vandc_303_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [3F800000, 00000000, 3F8CCCCD, 00003333]
|
|
|
|
test_vandc_304_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [3F800000, 3BC00000, 3784C4C4, 33F23130]
|
|
|
|
test_vandc_305_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F80CCC0, 3FF23332]
|
|
|
|
test_vandc_306_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [3F800000, 3B800000, 37044444, 33221100]
|
|
|
|
test_vandc_307_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [3F000000, 3FC00000, 008CCC00, 00003300]
|
|
|
|
test_vandc_308_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [3B800000, 3BC00000, 3B88C8C9, 3BF33333]
|
|
|
|
test_vandc_309_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [38800000, 38C00000, 3888C8C8, 38F03030]
|
|
|
|
test_vandc_310_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [37800000, 37C00000, 3784C4C5, 37F33333]
|
|
|
|
test_vandc_311_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [2D800000, 2DC00000, 2D8CCCCD, 2DE12121]
|
|
|
|
test_vandc_312_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [2D800000, 38800000, 2E8CCC89, 2A910033]
|
|
|
|
test_vandc_313_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [3E800000, 3EC00000, 3E8CCCCD, 3E833333]
|
|
|
|
test_vandc_314_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000000, 3BC00000, 000CC4C4, 33F23130]
|
|
|
|
test_vandc_315_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [3F800000, 3F400000, 00000000, 30000000]
|
|
|
|
test_vandc_316_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_317_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [3E800000, 3E400000, 3E0CCCCD, 3E033333]
|
|
|
|
test_vandc_318_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [32000000, 32000000, 32000000, 3BF23130]
|
|
|
|
test_vandc_319_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [07000000, 03000000, 3F8CCCCC, 3BF23130]
|
|
|
|
test_vandc_320_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [01000000, 01000000, 01000001, 01010101]
|
|
|
|
test_vandc_321_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 3F8CCCCC, 3FF13330]
|
|
|
|
test_vandc_322_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 3FC00000, 00000080, 3FF03331]
|
|
|
|
test_vandc_323_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000000, 0F800000, 00000000, 3FF33333]
|
|
|
|
test_vandc_324_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 3FC00000, 00000080, 3FF23333]
|
|
|
|
test_vandc_325_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_326_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
|
|
|
|
test_vandc_327_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
|
|
|
|
test_vandc_328_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [41200000, 00000000, 41700000, 00000000]
|
|
|
|
test_vandc_329_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
|
|
|
|
test_vandc_330_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
|
|
|
|
test_vandc_331_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [41200000, 81200000, 41600000, 01200000]
|
|
|
|
test_vandc_332_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [41000000, C1200000, 00700000, 00000000]
|
|
|
|
test_vandc_333_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
|
|
|
|
test_vandc_334_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [40200000, C0200000, 40700000, C0700000]
|
|
|
|
test_vandc_335_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
|
|
|
|
test_vandc_336_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [41200000, C1200000, 41600000, C1600000]
|
|
|
|
test_vandc_337_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [41000000, 40000000, 40500000, 80100000]
|
|
|
|
test_vandc_338_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [40200000, C0200000, 40700000, C0000000]
|
|
|
|
test_vandc_339_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00200000, C1200000, 00700000, C1700000]
|
|
|
|
test_vandc_340_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [41200000, 41200000, 00000000, 40000000]
|
|
|
|
test_vandc_341_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [40200000, 40200000, 40700000, 40000000]
|
|
|
|
test_vandc_342_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00000000, 80000000, 00500000, 80000000]
|
|
|
|
test_vandc_343_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00200000, 00200000, 00300000, C1700000]
|
|
|
|
test_vandc_344_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [01000000, 01000000, 41700000, C1700000]
|
|
|
|
test_vandc_345_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [01000000, 01000000, 01000000, 01000000]
|
|
|
|
test_vandc_346_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 41700000, C1700000]
|
|
|
|
test_vandc_347_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, C1200000, 00000000, C1700000]
|
|
|
|
test_vandc_348_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000000, 81000000, 00000000, C1700000]
|
|
|
|
test_vandc_349_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, C1200000, 00000000, C1700000]
|
|
|
|
test_vandc_350_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_351_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
|
|
test_vandc_352_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [7F800202, 04050606, 7F800A0A, 0C0D0E0E]
|
|
|
|
test_vandc_353_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [7F800000, 00000607, 7F800A0B, 00000E0F]
|
|
|
|
test_vandc_354_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [7F800000, 00000000, 77800000, 00000000]
|
|
|
|
test_vandc_355_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [7F800202, 04000602, 7F800A02, 0C000E02]
|
|
|
|
test_vandc_356_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [7F800000, 00000000, 77000000, 00000000]
|
|
|
|
test_vandc_357_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [7F000003, 04050007, 00800A00, 00000E00]
|
|
|
|
test_vandc_358_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [7B800203, 00010203, 7B800A0B, 08090A0B]
|
|
|
|
test_vandc_359_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [78800000, 00000000, 78800808, 08080808]
|
|
|
|
test_vandc_360_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [77800203, 04050607, 77800203, 04050607]
|
|
|
|
test_vandc_361_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [6D800001, 04050405, 6D800809, 0C0D0C0D]
|
|
|
|
test_vandc_362_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [6D800003, 00000406, 6E80080B, 08090807]
|
|
|
|
test_vandc_363_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [40000203, 00050607, 40000202, 000C0C0C]
|
|
|
|
test_vandc_364_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [3E800203, 04050607, 3E800A0B, 0C0D0E0F]
|
|
|
|
test_vandc_365_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [7F800203, 04000607, 00000000, 00000000]
|
|
|
|
test_vandc_366_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [40000203, 00050607, 40000202, 000C0C0C]
|
|
|
|
test_vandc_367_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [3E800203, 04050607, 3E000A0B, 0C0D0E0F]
|
|
|
|
test_vandc_368_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [32000202, 00000202, 32000202, 080C0C0C]
|
|
|
|
test_vandc_369_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [07000000, 00000000, 7F800808, 08080808]
|
|
|
|
test_vandc_370_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [01000001, 00010001, 01000001, 00010001]
|
|
|
|
test_vandc_371_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000002, 00010000, 7F800A0A, 0C0D0E0C]
|
|
|
|
test_vandc_372_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000001, 04050606, 00000002, 0C0C0E0D]
|
|
|
|
test_vandc_373_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000202, 04050000, 00000000, 0C0D0E0F]
|
|
|
|
test_vandc_374_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000003, 04050600, 00000000, 0C0C0E0F]
|
|
|
|
test_vandc_375_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_376_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
|
|
test_vandc_377_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFE, 8FFFFFFE]
|
|
|
|
test_vandc_378_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [80080000, 00000000, 7FFFFFFF, 0000FFFF]
|
|
|
|
test_vandc_379_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [80081010, 808A0000, 77F6F5F4, 83F2F1F0]
|
|
|
|
test_vandc_380_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [80001010, 80820000, 7FF2FFF2, 8FF2FFF2]
|
|
|
|
test_vandc_381_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [80081000, 808A0000, 77665544, 03221100]
|
|
|
|
test_vandc_382_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [80000010, 808F0000, 00FFFF00, 0000FF00]
|
|
|
|
test_vandc_383_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [80081010, 808B0000, 7BFBFBFB, 8BFBFBFB]
|
|
|
|
test_vandc_384_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [80081010, 80880000, 78F8F8F8, 88F8F8F8]
|
|
|
|
test_vandc_385_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [80001010, 80870000, 77F7F7F7, 87F7F7F7]
|
|
|
|
test_vandc_386_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [80080000, 808D0000, 6DEDEDED, 8DEDEDED]
|
|
|
|
test_vandc_387_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [80080000, 008A0000, 6EDDCCBB, 8A998877]
|
|
|
|
test_vandc_388_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [80081010, 800F0000, 40733332, 800CCCCC]
|
|
|
|
test_vandc_389_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [80081010, 008F0000, 3E8FFFFF, 0E8FFFFF]
|
|
|
|
test_vandc_390_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [80081010, 808A0000, 007FF5F4, 83F2F1F0]
|
|
|
|
test_vandc_391_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00081010, 000F0000, 40733332, 000CCCCC]
|
|
|
|
test_vandc_392_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00081010, 800F0000, 3E5FFFFF, 8E0FFFFF]
|
|
|
|
test_vandc_393_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00001010, 00020000, 32323232, 8BFEFDFC]
|
|
|
|
test_vandc_394_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00020000, 7FFEFDFC, 8BFAF9F8]
|
|
|
|
test_vandc_395_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00010000, 01010101, 01010101]
|
|
|
|
test_vandc_396_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00010000, 7FFFFFFE, 8FFDFFFC]
|
|
|
|
test_vandc_397_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 808D0000, 00030082, 8FFCFF7D]
|
|
|
|
test_vandc_398_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00001010, 808F0000, 00000000, 8FFFFFFF]
|
|
|
|
test_vandc_399_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000010, 808F0000, 00010080, 8FFEFF7F]
|
|
|
|
test_vandc_400_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_401_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
|
|
test_vandc_402_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCC, BFF33332]
|
|
|
|
test_vandc_403_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [BF800000, 00000000, BF8CCCCD, 00003333]
|
|
|
|
test_vandc_404_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [BF800000, BBC00000, B784C4C4, B3F23130]
|
|
|
|
test_vandc_405_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [BF800000, BFC00000, BF80CCC0, BFF23332]
|
|
|
|
test_vandc_406_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [BF800000, BB800000, 37044444, 33221100]
|
|
|
|
test_vandc_407_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [BF000000, BFC00000, 008CCC00, 00003300]
|
|
|
|
test_vandc_408_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [BB800000, BBC00000, BB88C8C9, BBF33333]
|
|
|
|
test_vandc_409_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [B8800000, B8C00000, B888C8C8, B8F03030]
|
|
|
|
test_vandc_410_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [B7800000, B7C00000, B784C4C5, B7F33333]
|
|
|
|
test_vandc_411_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [AD800000, ADC00000, AD8CCCCD, ADE12121]
|
|
|
|
test_vandc_412_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [AD800000, 38800000, AE8CCC89, AA910033]
|
|
|
|
test_vandc_413_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
|
|
|
|
test_vandc_414_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [BE800000, 3EC00000, BE8CCCCD, 3E833333]
|
|
|
|
test_vandc_415_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [80000000, BBC00000, 800CC4C4, B3F23130]
|
|
|
|
test_vandc_416_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [3F800000, 3F400000, 80000000, 30000000]
|
|
|
|
test_vandc_417_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [3E800000, BE400000, 3E0CCCCD, BE033333]
|
|
|
|
test_vandc_418_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [32000000, 32000000, 32000000, BBF23130]
|
|
|
|
test_vandc_419_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [07000000, 03000000, BF8CCCCC, BBF23130]
|
|
|
|
test_vandc_420_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [01000000, 01000000, 01000001, 01010101]
|
|
|
|
test_vandc_421_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, BF8CCCCC, BFF13330]
|
|
|
|
test_vandc_422_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, BFC00000, 00000080, BFF03331]
|
|
|
|
test_vandc_423_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000000, 8F800000, 00000000, BFF33333]
|
|
|
|
test_vandc_424_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, BFC00000, 00000080, BFF23333]
|
|
|
|
test_vandc_425_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_426_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
|
|
test_vandc_427_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
|
|
test_vandc_428_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [C1200000, 00000000, C1A00000, 00000000]
|
|
|
|
test_vandc_429_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
|
|
test_vandc_430_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
|
|
test_vandc_431_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [C1200000, 01A00000, 41200000, 01200000]
|
|
|
|
test_vandc_432_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [C1000000, 41A00000, 00A00000, 00000000]
|
|
|
|
test_vandc_433_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
|
|
test_vandc_434_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [C0200000, 40A00000, C0A00000, 40F00000]
|
|
|
|
test_vandc_435_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
|
|
test_vandc_436_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41E00000]
|
|
|
|
test_vandc_437_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [C1000000, 40800000, C0800000, 00900000]
|
|
|
|
test_vandc_438_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [C0200000, 40200000, C0200000, 40000000]
|
|
|
|
test_vandc_439_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [80000000, 00800000, 80800000, 00800000]
|
|
|
|
test_vandc_440_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [80200000, 41A00000, 80200000, 41F00000]
|
|
|
|
test_vandc_441_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [41200000, 41200000, 80000000, 40000000]
|
|
|
|
test_vandc_442_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [40200000, 40200000, 40200000, 40000000]
|
|
|
|
test_vandc_443_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00200000, 00200000, 00200000, 41F00000]
|
|
|
|
test_vandc_444_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [01000000, 01000000, C1A00000, 41F00000]
|
|
|
|
test_vandc_445_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [01000000, 01000000, 01000000, 01000000]
|
|
|
|
test_vandc_446_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, C1A00000, 41F00000]
|
|
|
|
test_vandc_447_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 41A00000, 00000000, 41F00000]
|
|
|
|
test_vandc_448_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000000, 01800000, 00000000, 41F00000]
|
|
|
|
test_vandc_449_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 41A00000, 00000000, 41F00000]
|
|
|
|
test_vandc_450_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_451_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
|
|
test_vandc_452_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [CDCDCDCC, CDCDCDCC, CDCDCDCC, 04010202]
|
|
|
|
test_vandc_453_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [CDCD0000, 0000CDCD, CDCDCDCD, 00000203]
|
|
|
|
test_vandc_454_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [CDCCCDCC, C9C8C9C8, C5C4C5C4, 00000000]
|
|
|
|
test_vandc_455_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [CDC0CDC0, CDC0CDC0, CDC0CDC0, 04000202]
|
|
|
|
test_vandc_456_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [CDCCCDCC, 89888988, 45444544, 00000000]
|
|
|
|
test_vandc_457_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [CD0000CD, CDCD00CD, 00CDCD00, 00000200]
|
|
|
|
test_vandc_458_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [C9C9C9C9, C9C9C9C9, C9C9C9C9, 00010203]
|
|
|
|
test_vandc_459_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [C8C8C8C8, C8C8C8C8, C8C8C8C8, 00000000]
|
|
|
|
test_vandc_460_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [C5C5C5C5, C5C5C5C5, C5C5C5C5, 04010203]
|
|
|
|
test_vandc_461_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010001]
|
|
|
|
test_vandc_462_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [CDC98985, 48888CCC, CCCDCC89, 00010003]
|
|
|
|
test_vandc_463_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [C04DCDCD, C00DCDCD, C0410100, 00000000]
|
|
|
|
test_vandc_464_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [8CCDCDCD, 0CCDCDCD, 8C8DCDCD, 04010203]
|
|
|
|
test_vandc_465_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [804DCDCC, C9C8C9C8, 804DC5C4, 00000000]
|
|
|
|
test_vandc_466_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [4DC5CDCD, 4D40CDCD, 80000000, 00000000]
|
|
|
|
test_vandc_467_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [404DCDCD, 400DCDCD, 40410100, 00000000]
|
|
|
|
test_vandc_468_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [0CCDCDCD, 8C4DCDCD, 0C4DCDCD, 04010203]
|
|
|
|
test_vandc_469_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [05040504, 01000100, CDCCCDCC, 00000000]
|
|
|
|
test_vandc_470_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 00010001]
|
|
|
|
test_vandc_471_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00010000, 00010000, CDCDCDCC, 04010200]
|
|
|
|
test_vandc_472_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000081, CDCDCD4C, 00010080, 04000201]
|
|
|
|
test_vandc_473_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000CCCC, 8D8D0000, 00000000, 04010203]
|
|
|
|
test_vandc_474_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [0000004D, CDCDCD80, 00010080, 04000203]
|
|
|
|
test_vandc_475_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_476_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
|
|
test_vandc_477_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [F8F9FAFA, FCFDFEFE, 00010202, 04050606]
|
|
|
|
test_vandc_478_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [F8F90000, 0000FEFF, 00010203, 00000607]
|
|
|
|
test_vandc_479_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [F8F8F8F8, F8F8F8F8, 00000000, 00000000]
|
|
|
|
test_vandc_480_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [F8F0FAF2, FCF0FEF2, 00000202, 04000602]
|
|
|
|
test_vandc_481_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [F8E8D8C8, B8A89888, 00000000, 00000000]
|
|
|
|
test_vandc_482_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [F80000FB, FCFD00FF, 00010200, 00000600]
|
|
|
|
test_vandc_483_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [F8F9FAFB, F8F9FAFB, 00010203, 00010203]
|
|
|
|
test_vandc_484_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [F8F8F8F8, F8F8F8F8, 00000000, 00000000]
|
|
|
|
test_vandc_485_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, 00010203, 04050607]
|
|
|
|
test_vandc_486_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [E8E9E8E9, ECEDECED, 00010001, 04050405]
|
|
|
|
test_vandc_487_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [E8C9A883, 7898BCDE, 00010003, 00010007]
|
|
|
|
test_vandc_488_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [C079FAFB, C03DFEFF, 00010202, 00040404]
|
|
|
|
test_vandc_489_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [B8D9FAFB, 3CDDFEFF, 00010203, 04050607]
|
|
|
|
test_vandc_490_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [8079F8F8, F8F8F8F8, 00010000, 00000000]
|
|
|
|
test_vandc_491_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [78F1EAEB, 7C70FEFF, 00000000, 00000000]
|
|
|
|
test_vandc_492_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [4079FAFB, 403DFEFF, 00010202, 00040404]
|
|
|
|
test_vandc_493_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [38D9FAFB, BC5DFEFF, 00010203, 04050607]
|
|
|
|
test_vandc_494_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [30303232, 30303232, 00000202, 00040404]
|
|
|
|
test_vandc_495_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
|
|
|
|
test_vandc_496_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00010002, 00010000, 00010202, 04050604]
|
|
|
|
test_vandc_497_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000081, FCFDFE7E, 00010002, 04040605]
|
|
|
|
test_vandc_498_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000FAFA, 8C8D0000, 00000000, 04050607]
|
|
|
|
test_vandc_499_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [0000007B, FCFDFE80, 00010000, 04040607]
|
|
|
|
test_vandc_500_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_501_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
|
|
test_vandc_502_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
|
|
test_vandc_503_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [FEFE0000, 0000FEFE, FEFEFEFE, 0000FEFE]
|
|
|
|
test_vandc_504_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FEFEFCFC, FAFAF8F8, F6F6F4F4, F2F2F0F0]
|
|
|
|
test_vandc_505_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [FEF2FEF2, FEF2FEF2, FEF2FEF2, FEF2FEF2]
|
|
|
|
test_vandc_506_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FEEEDCCC, BAAA9888, 76665444, 32221000]
|
|
|
|
test_vandc_507_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FE0000FE, FEFE00FE, 00FEFE00, 0000FE00]
|
|
|
|
test_vandc_508_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [FAFAFAFA, FAFAFAFA, FAFAFAFA, FAFAFAFA]
|
|
|
|
test_vandc_509_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [F8F8F8F8, F8F8F8F8, F8F8F8F8, F8F8F8F8]
|
|
|
|
test_vandc_510_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [F6F6F6F6, F6F6F6F6, F6F6F6F6, F6F6F6F6]
|
|
|
|
test_vandc_511_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [ECECECEC, ECECECEC, ECECECEC, ECECECEC]
|
|
|
|
test_vandc_512_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [ECCAA886, 789ABCDE, EEDCCCBA, AA988876]
|
|
|
|
test_vandc_513_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [C07EFEFE, C03EFEFE, C0723232, C00CCCCC]
|
|
|
|
test_vandc_514_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [BEDEFEFE, 3EDEFEFE, BE8EFEFE, 3E8EFEFE]
|
|
|
|
test_vandc_515_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [807EFCFC, FAFAF8F8, 807EF4F4, F2F2F0F0]
|
|
|
|
test_vandc_516_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [7EF6EEEE, 7E70FEFE, 80000000, 70000000]
|
|
|
|
test_vandc_517_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [407EFEFE, 403EFEFE, 40723232, 400CCCCC]
|
|
|
|
test_vandc_518_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [3EDEFEFE, BE5EFEFE, 3E5EFEFE, BE0EFEFE]
|
|
|
|
test_vandc_519_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [32323232, 32323232, 32323232, FAFEFCFC]
|
|
|
|
test_vandc_520_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [06060404, 02020000, FEFEFCFC, FAFAF8F8]
|
|
|
|
test_vandc_521_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00020002, 00000000, FEFEFEFE, FEFCFEFC]
|
|
|
|
test_vandc_522_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00020080, FEFCFE7E, 00020082, FEFCFE7C]
|
|
|
|
test_vandc_523_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000FEFE, 8E8E0000, 00000000, FEFEFEFE]
|
|
|
|
test_vandc_524_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [0000007E, FEFEFE80, 00000080, FEFEFE7E]
|
|
|
|
test_vandc_525_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_526_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
|
|
test_vandc_527_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FFFCFFFC, FFFEFFFE, 00000000, 00020002]
|
|
|
|
test_vandc_528_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [FFFC0000, 0000FFFF, 00000001, 00000003]
|
|
|
|
test_vandc_529_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFFCFDFC, FBFAF9F8, 00000000, 00020000]
|
|
|
|
test_vandc_530_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [FFF0FFF0, FFF2FFF2, 00000000, 00020002]
|
|
|
|
test_vandc_531_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FFECDDCC, BBAA9988, 00000000, 00020000]
|
|
|
|
test_vandc_532_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FF0000FD, FFFE00FF, 00000000, 00000000]
|
|
|
|
test_vandc_533_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [FBF8FBF9, FBFAFBFB, 00000001, 00020003]
|
|
|
|
test_vandc_534_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [F8F8F8F8, F8F8F8F8, 00000000, 00000000]
|
|
|
|
test_vandc_535_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [F7F4F7F5, F7F6F7F7, 00000001, 00020003]
|
|
|
|
test_vandc_536_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [EDECEDED, EDECEDED, 00000001, 00000001]
|
|
|
|
test_vandc_537_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [EDC8A985, 789ABCDE, 00000001, 00000003]
|
|
|
|
test_vandc_538_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [C07CFFFD, C03EFFFF, 00000000, 00000000]
|
|
|
|
test_vandc_539_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [BEDCFFFD, 3EDEFFFF, 00000001, 00020003]
|
|
|
|
test_vandc_540_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [807CFDFC, FBFAF9F8, 00000000, 00020000]
|
|
|
|
test_vandc_541_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [7FF4EFED, 7F70FFFF, 00000000, 00000000]
|
|
|
|
test_vandc_542_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [407CFFFD, 403EFFFF, 00000000, 00000000]
|
|
|
|
test_vandc_543_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [3EDCFFFD, BE5EFFFF, 00000001, 00020003]
|
|
|
|
test_vandc_544_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [32303230, 32323232, 00000000, 00020000]
|
|
|
|
test_vandc_545_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [07040504, 03020100, 00000000, 00020000]
|
|
|
|
test_vandc_546_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [01000101, 01000101, 00000001, 00000001]
|
|
|
|
test_vandc_547_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000081, FFFCFF7E, 00000000, 00000001]
|
|
|
|
test_vandc_548_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000FEFC, 8F8E0000, 00000000, 00020003]
|
|
|
|
test_vandc_549_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [0000007D, FFFEFF80, 00000000, 00020003]
|
|
|
|
test_vandc_550_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_551_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
|
|
test_vandc_552_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FFFDFF7E, 00020080, FFFCFF7C, 00030082]
|
|
|
|
test_vandc_553_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [FFFD0000, 00000081, FFFCFF7D, 00000082]
|
|
|
|
test_vandc_554_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFFCFD7C, 00020080, F7F4F574, 00020080]
|
|
|
|
test_vandc_555_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [FFF0FF72, 00020080, FFF0FF70, 00020082]
|
|
|
|
test_vandc_556_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FFECDD4C, 00020080, 77645544, 00020000]
|
|
|
|
test_vandc_557_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FF00007E, 00020081, 00FCFF00, 00000000]
|
|
|
|
test_vandc_558_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [FBF9FB7A, 00020081, FBF8FB79, 00030082]
|
|
|
|
test_vandc_559_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [F8F8F878, 00000080, F8F8F878, 00000080]
|
|
|
|
test_vandc_560_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [F7F5F776, 00020081, F7F4F775, 00030082]
|
|
|
|
test_vandc_561_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [EDEDED6C, 00000081, EDECED6D, 00010080]
|
|
|
|
test_vandc_562_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [EDC9A906, 00020080, EEDCCC39, 00010002]
|
|
|
|
test_vandc_563_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [C07DFF7E, 00020081, C0703330, 00000080]
|
|
|
|
test_vandc_564_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [BEDDFF7E, 00020081, BE8CFF7D, 00030082]
|
|
|
|
test_vandc_565_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [807DFD7C, 00020080, 807CF574, 00020080]
|
|
|
|
test_vandc_566_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [7FF5EF6E, 00000081, 80000000, 00000000]
|
|
|
|
test_vandc_567_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [407DFF7E, 00020081, 40703330, 00000080]
|
|
|
|
test_vandc_568_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [3EDDFF7E, 00020081, 3E5CFF7D, 00030082]
|
|
|
|
test_vandc_569_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [32303232, 00020000, 32303230, 00020080]
|
|
|
|
test_vandc_570_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [07040504, 00020000, FFFCFD7C, 00020080]
|
|
|
|
test_vandc_571_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [01010100, 00000001, 01000101, 00010000]
|
|
|
|
test_vandc_572_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00010002, 00000000, FFFCFF7C, 00010080]
|
|
|
|
test_vandc_573_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000FE7E, 00020000, 00000000, 00030082]
|
|
|
|
test_vandc_574_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [0000007E, 00020080, 00000000, 00020002]
|
|
|
|
test_vandc_575_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_576_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
|
|
test_vandc_577_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FFFF0100, 7070FFFE, FFFFFFFE, 00000000]
|
|
|
|
test_vandc_578_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [FFFF0000, 0000FFFF, FFFFFFFF, 00000000]
|
|
|
|
test_vandc_579_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFFE0100, 7070F9F8, F7F6F5F4, 00000000]
|
|
|
|
test_vandc_580_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [FFF20100, 7070FFF2, FFF2FFF2, 00000000]
|
|
|
|
test_vandc_581_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FFEE0100, 30209988, 77665544, 00000000]
|
|
|
|
test_vandc_582_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FF000001, 707000FF, 00FFFF00, 00000000]
|
|
|
|
test_vandc_583_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [FBFB0101, 7070FBFB, FBFBFBFB, 00000000]
|
|
|
|
test_vandc_584_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [F8F80000, 7070F8F8, F8F8F8F8, 00000000]
|
|
|
|
test_vandc_585_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [F7F70101, 7070F7F7, F7F7F7F7, 00000000]
|
|
|
|
test_vandc_586_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [EDED0101, 6060EDED, EDEDEDED, 00000000]
|
|
|
|
test_vandc_587_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [EDCB0101, 7010BCDE, EEDDCCBB, 00000000]
|
|
|
|
test_vandc_588_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [C07F0101, 4030FFFF, C0733332, 00000000]
|
|
|
|
test_vandc_589_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [BEDF0101, 3050FFFF, BE8FFFFF, 00000000]
|
|
|
|
test_vandc_590_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [807F0100, 7070F9F8, 807FF5F4, 00000000]
|
|
|
|
test_vandc_591_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [7FF70101, 7070FFFF, 80000000, 00000000]
|
|
|
|
test_vandc_592_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [407F0101, 4030FFFF, 40733332, 00000000]
|
|
|
|
test_vandc_593_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [3EDF0101, 3050FFFF, 3E5FFFFF, 00000000]
|
|
|
|
test_vandc_594_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [32320000, 30303232, 32323232, 00000000]
|
|
|
|
test_vandc_595_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [07060100, 00000100, FFFEFDFC, 00000000]
|
|
|
|
test_vandc_596_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [01010101, 00000101, 01010101, 00000000]
|
|
|
|
test_vandc_597_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00030000, 00000000, FFFFFFFE, 00000000]
|
|
|
|
test_vandc_598_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00020001, 7070FF7E, 00030082, 00000000]
|
|
|
|
test_vandc_599_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000001, 7070FF80, 00010080, 00000000]
|
|
|
|
test_vandc_600_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_601_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
|
|
test_vandc_602_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FFFFFF80, 0000007E, FFFEFF7E, 00010080]
|
|
|
|
test_vandc_603_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [FFFF0000, 0000007F, FFFEFF7F, 00000080]
|
|
|
|
test_vandc_604_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFFEFD80, 00000078, F7F6F574, 00000080]
|
|
|
|
test_vandc_605_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [FFF2FF80, 00000072, FFF2FF72, 00000080]
|
|
|
|
test_vandc_606_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FFEEDD80, 00000008, 77665544, 00000000]
|
|
|
|
test_vandc_607_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FF000080, 0000007F, 00FEFF00, 00000000]
|
|
|
|
test_vandc_608_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [FBFBFB80, 0000007B, FBFAFB7B, 00010080]
|
|
|
|
test_vandc_609_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [F8F8F880, 00000078, F8F8F878, 00000080]
|
|
|
|
test_vandc_610_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [F7F7F780, 00000077, F7F6F777, 00010080]
|
|
|
|
test_vandc_611_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [EDEDED80, 0000006D, EDECED6D, 00010080]
|
|
|
|
test_vandc_612_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [EDCBA980, 0000005E, EEDCCC3B, 00010000]
|
|
|
|
test_vandc_613_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [C07FFF80, 0000007F, C0723332, 00000080]
|
|
|
|
test_vandc_614_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [BEDFFF80, 0000007F, BE8EFF7F, 00010080]
|
|
|
|
test_vandc_615_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [807FFD80, 00000078, 807EF574, 00000080]
|
|
|
|
test_vandc_616_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [7FF7EF80, 0000007F, 80000000, 00000000]
|
|
|
|
test_vandc_617_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [407FFF80, 0000007F, 40723332, 00000080]
|
|
|
|
test_vandc_618_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [3EDFFF80, 0000007F, 3E5EFF7F, 00010080]
|
|
|
|
test_vandc_619_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [32323200, 00000032, 32323232, 00000080]
|
|
|
|
test_vandc_620_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [07060500, 00000000, FFFEFD7C, 00000080]
|
|
|
|
test_vandc_621_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [01010100, 00000001, 01000101, 00010000]
|
|
|
|
test_vandc_622_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00030000, 00000000, FFFEFF7E, 00010080]
|
|
|
|
test_vandc_623_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00020080, 0000007E, 00020002, 00000000]
|
|
|
|
test_vandc_624_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000FE80, 00000000, 00000000, 00010080]
|
|
|
|
test_vandc_625_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vandc_626_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
|
|
test_vandc_627_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
|
|
|
|
test_vandc_628_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [FFFF0000, 0000FFFF, FFFFFFFF, 0000FFFF]
|
|
|
|
test_vandc_629_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFFEFDFC, FBFAF9F8, F7F6F5F4, F3F2F1F0]
|
|
|
|
test_vandc_630_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [FFF2FFF2, FFF2FFF2, FFF2FFF2, FFF2FFF2]
|
|
|
|
test_vandc_631_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FFEEDDCC, BBAA9988, 77665544, 33221100]
|
|
|
|
test_vandc_632_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FF0000FF, FFFF00FF, 00FFFF00, 0000FF00]
|
|
|
|
test_vandc_633_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [FBFBFBFB, FBFBFBFB, FBFBFBFB, FBFBFBFB]
|
|
|
|
test_vandc_634_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [F8F8F8F8, F8F8F8F8, F8F8F8F8, F8F8F8F8]
|
|
|
|
test_vandc_635_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [F7F7F7F7, F7F7F7F7, F7F7F7F7, F7F7F7F7]
|
|
|
|
test_vandc_636_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [EDEDEDED, EDEDEDED, EDEDEDED, EDEDEDED]
|
|
|
|
test_vandc_637_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [EDCBA987, 789ABCDE, EEDDCCBB, AA998877]
|
|
|
|
test_vandc_638_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [C07FFFFF, C03FFFFF, C0733332, C00CCCCC]
|
|
|
|
test_vandc_639_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [BEDFFFFF, 3EDFFFFF, BE8FFFFF, 3E8FFFFF]
|
|
|
|
test_vandc_640_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [807FFDFC, FBFAF9F8, 807FF5F4, F3F2F1F0]
|
|
|
|
test_vandc_641_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [7FF7EFEF, 7F70FFFF, 80000000, 70000000]
|
|
|
|
test_vandc_642_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [407FFFFF, 403FFFFF, 40733332, 400CCCCC]
|
|
|
|
test_vandc_643_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [3EDFFFFF, BE5FFFFF, 3E5FFFFF, BE0FFFFF]
|
|
|
|
test_vandc_644_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [32323232, 32323232, 32323232, FBFEFDFC]
|
|
|
|
test_vandc_645_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [07060504, 03020100, FFFEFDFC, FBFAF9F8]
|
|
|
|
test_vandc_646_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
|
|
|
|
test_vandc_647_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00030002, 00010000, FFFFFFFE, FFFDFFFC]
|
|
|
|
test_vandc_648_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00020081, FFFDFF7E, 00030082, FFFCFF7D]
|
|
|
|
test_vandc_649_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000FEFE, 8F8F0000, 00000000, FFFFFFFF]
|
|
|
|
test_vandc_650_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vandc v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [0000007F, FFFFFF80, 00010080, FFFEFF7F]
|
|
|