5851 lines
226 KiB
ArmAsm
5851 lines
226 KiB
ArmAsm
test_vavgsb_1_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
|
|
|
test_vavgsb_2_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vavgsb_3_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00010102, 02030304, 04050506, 06070708]
|
|
|
|
test_vavgsb_4_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00070007, 00070007, 00070007, 00070007]
|
|
|
|
test_vavgsb_5_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [0009111A, 222B333C, C4CDD5DE, E6EFF700]
|
|
|
|
test_vavgsb_6_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vavgsb_7_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [02020202, 02020202, 02020202, 02020202]
|
|
|
|
test_vavgsb_8_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vavgsb_9_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vavgsb_10_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [09090909, 09090909, 09090909, 09090909]
|
|
|
|
test_vavgsb_11_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [091A2B3C, C4332211, 09111A22, 2B333CC4]
|
|
|
|
test_vavgsb_12_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [20C00000, 20E00000, 20C6E6E7, 20FA1A1A]
|
|
|
|
test_vavgsb_13_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [21100000, E1100000, 21380000, E1380000]
|
|
|
|
test_vavgsb_14_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [40C00102, 02030304, 40C00506, 06070708]
|
|
|
|
test_vavgsb_15_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [C0040808, C0C80000, 40000000, C8000000]
|
|
|
|
test_vavgsb_16_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [E0C00000, E0E00000, E0C6E6E7, E0FA1A1A]
|
|
|
|
test_vavgsb_17_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [E1100000, 21D00000, E1D00000, 21F80000]
|
|
|
|
test_vavgsb_18_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
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#_ REGISTER_OUT v3 [E7E7E7E7, E7E7E7E7, E7E7E7E7, 02010102]
|
|
|
|
test_vavgsb_19_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [FCFDFDFE, FEFFFF00, 00010102, 02030304]
|
|
|
|
test_vavgsb_20_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
|
|
test_vavgsb_21_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00FE00FF, 00FF0000, 00000001, 00010002]
|
|
|
|
test_vavgsb_22_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00FF003F, 000100C1, 00FE003F, 000200C1]
|
|
|
|
test_vavgsb_23_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000101, 38380000, 00000000, 00000000]
|
|
|
|
test_vavgsb_24_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [000000C0, 00000040, 00FF0040, 000100C0]
|
|
|
|
test_vavgsb_25_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vavgsb_26_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
|
|
|
test_vavgsb_27_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000001, 00000001, 00000001]
|
|
|
|
test_vavgsb_28_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00010102, 02030304, 04050506, 06070708]
|
|
|
|
test_vavgsb_29_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00070007, 00070007, 00070007, 00070007]
|
|
|
|
test_vavgsb_30_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [0009111A, 222B333C, C4CDD5DE, E6EFF700]
|
|
|
|
test_vavgsb_31_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000000, 00000000]
|
|
|
|
test_vavgsb_32_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [02020203, 02020203, 02020203, 02020203]
|
|
|
|
test_vavgsb_33_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vavgsb_34_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [04040405, 04040405, 04040405, 04040405]
|
|
|
|
test_vavgsb_35_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [0909090A, 0909090A, 0909090A, 0909090A]
|
|
|
|
test_vavgsb_36_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [091A2B3D, C4332211, 09111A23, 2B333CC5]
|
|
|
|
test_vavgsb_37_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [20C00001, 20E00001, 20C6E6E7, 20FA1A1A]
|
|
|
|
test_vavgsb_38_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [21100001, E1100001, 21380001, E1380001]
|
|
|
|
test_vavgsb_39_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [40C00102, 02030304, 40C00506, 06070708]
|
|
|
|
test_vavgsb_40_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [C0040809, C0C80001, 40000000, C8000000]
|
|
|
|
test_vavgsb_41_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [E0C00001, E0E00001, E0C6E6E7, E0FA1A1A]
|
|
|
|
test_vavgsb_42_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [E1100001, 21D00001, E1D00001, 21F80001]
|
|
|
|
test_vavgsb_43_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [E7E7E7E7, E7E7E7E7, E7E7E7E7, 02010102]
|
|
|
|
test_vavgsb_44_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [FCFDFDFE, FEFFFF00, 00010102, 02030304]
|
|
|
|
test_vavgsb_45_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [FFFFFF00, FFFFFF00, FFFFFF00, FFFFFF00]
|
|
|
|
test_vavgsb_46_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00FE00FF, 00FF0000, 00000001, 00010002]
|
|
|
|
test_vavgsb_47_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00FF0040, 000100C1, 00FE003F, 000200C2]
|
|
|
|
test_vavgsb_48_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000101, 38380000, 00000000, 00000001]
|
|
|
|
test_vavgsb_49_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [000000C1, 00000040, 00FF0040, 000100C1]
|
|
|
|
test_vavgsb_50_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vavgsb_51_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vavgsb_52_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00000000, 00000001, 00000001, 00000001]
|
|
|
|
test_vavgsb_53_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00010101, 02020304, 04050506, 06060708]
|
|
|
|
test_vavgsb_54_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00070006, 00060007, 00070007, 00060007]
|
|
|
|
test_vavgsb_55_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00091119, 222A333C, C4CDD5DE, E6EEF700]
|
|
|
|
test_vavgsb_56_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [0000FF00, 00000000, 00000000, FFFF0000]
|
|
|
|
test_vavgsb_57_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [02020202, 02020202, 02020202, 02020202]
|
|
|
|
test_vavgsb_58_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [04040303, 03030404, 04040404, 03030404]
|
|
|
|
test_vavgsb_59_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vavgsb_60_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [09090909, 09090909, 09090909, 09090909]
|
|
|
|
test_vavgsb_61_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [091A2B3C, C3322211, 09111A22, 2A333CC4]
|
|
|
|
test_vavgsb_62_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [20C00000, 1FE00000, 20C6E6E7, 1FF91A1A]
|
|
|
|
test_vavgsb_63_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [21100000, E0100000, 21380000, E0380000]
|
|
|
|
test_vavgsb_64_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [40C00101, 02020304, 40C00506, 06060708]
|
|
|
|
test_vavgsb_65_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [C0040808, C0C70000, 40000000, C7FF0000]
|
|
|
|
test_vavgsb_66_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [E0C00000, DFE00000, E0C6E6E7, DFF91A1A]
|
|
|
|
test_vavgsb_67_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [E1100000, 20D00000, E1D00000, 20F80000]
|
|
|
|
test_vavgsb_68_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [E7E7E6E6, E6E6E7E7, E7E7E7E7, 02000102]
|
|
|
|
test_vavgsb_69_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [FCFDFDFD, FEFEFF00, 00010102, 02020304]
|
|
|
|
test_vavgsb_70_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
|
|
test_vavgsb_71_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00FEFFFE, FFFF0000, 00000001, 00010002]
|
|
|
|
test_vavgsb_72_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00FFFF3F, 000100C1, 00FE003F, 000100C1]
|
|
|
|
test_vavgsb_73_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000000, 38380000, 00000000, 00000000]
|
|
|
|
test_vavgsb_74_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [0000FFC0, 00000040, 00FF0040, 000000C0]
|
|
|
|
test_vavgsb_75_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
|
|
test_vavgsb_76_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00010102, 02030304, 04050506, 06070708]
|
|
|
|
test_vavgsb_77_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00010102, 02030304, 04050506, 06070708]
|
|
|
|
test_vavgsb_78_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00010101, 02020304, 04050506, 06060708]
|
|
|
|
test_vavgsb_79_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00070108, 0209030A, 040B050C, 060D070E]
|
|
|
|
test_vavgsb_80_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [0009121B, 242D363F, C8D1DAE3, ECF5FE07]
|
|
|
|
test_vavgsb_81_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00000102, 02030304, 04050505, 06060707]
|
|
|
|
test_vavgsb_82_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [02030304, 04050506, 06070708, 0809090A]
|
|
|
|
test_vavgsb_83_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [04040505, 06060707, 08080909, 0A0A0B0B]
|
|
|
|
test_vavgsb_84_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [04050506, 06070708, 0809090A, 0A0B0B0C]
|
|
|
|
test_vavgsb_85_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [090A0A0B, 0B0C0C0D, 0D0E0E0F, 0F101011]
|
|
|
|
test_vavgsb_86_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [091B2C3E, C6352514, 0D161F28, 313A43CC]
|
|
|
|
test_vavgsb_87_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [20C10102, 22E30304, 24CBEBEC, 26002121]
|
|
|
|
test_vavgsb_88_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [21110102, E3130304, 253D0506, E73F0708]
|
|
|
|
test_vavgsb_89_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [40C10203, 04050607, 44C50A0B, 0C0D0E0F]
|
|
|
|
test_vavgsb_90_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [C005090A, C2CA0304, 44040505, CE060707]
|
|
|
|
test_vavgsb_91_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [E0C10102, E2E30304, E4CBEBEC, E6002121]
|
|
|
|
test_vavgsb_92_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [E1110102, 23D30304, E5D50506, 27FF0708]
|
|
|
|
test_vavgsb_93_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [E7E7E8E8, E9E9EAEA, EBEBECEC, 08070809]
|
|
|
|
test_vavgsb_94_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [FCFDFEFF, 00010203, 04050607, 08090A0B]
|
|
|
|
test_vavgsb_95_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [FF000001, 01020203, 03040405, 05060607]
|
|
|
|
test_vavgsb_96_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00FF0100, 02020303, 04050506, 06080709]
|
|
|
|
test_vavgsb_97_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00FF0141, 020403C4, 04030544, 060807C9]
|
|
|
|
test_vavgsb_98_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000202, 3A3B0303, 04040505, 06070708]
|
|
|
|
test_vavgsb_99_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [000001C2, 02030343, 04040545, 060707C8]
|
|
|
|
test_vavgsb_100_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000101, 02020303, 04040505, 06060707]
|
|
|
|
test_vavgsb_101_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00070007, 00070007, 00070007, 00070007]
|
|
|
|
test_vavgsb_102_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00070007, 00070007, 00070007, 00070007]
|
|
|
|
test_vavgsb_103_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00070006, 00060007, 00070007, 00060007]
|
|
|
|
test_vavgsb_104_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00070108, 0209030A, 040B050C, 060D070E]
|
|
|
|
test_vavgsb_105_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [000F1120, 22313342, C4D3D5E4, E6F5F706]
|
|
|
|
test_vavgsb_106_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00060007, 00070007, 00070006, 00060006]
|
|
|
|
test_vavgsb_107_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [02090209, 02090209, 02090209, 02090209]
|
|
|
|
test_vavgsb_108_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [040A040A, 040A040A, 040A040A, 040A040A]
|
|
|
|
test_vavgsb_109_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [040B040B, 040B040B, 040B040B, 040B040B]
|
|
|
|
test_vavgsb_110_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [09100910, 09100910, 09100910, 09100910]
|
|
|
|
test_vavgsb_111_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [09212B43, C4392217, 09181A29, 2B3A3CCB]
|
|
|
|
test_vavgsb_112_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [20C70007, 20E70007, 20CDE6ED, 20001A20]
|
|
|
|
test_vavgsb_113_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [21170007, E1170007, 213F0007, E13F0007]
|
|
|
|
test_vavgsb_114_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [40C70108, 0209030A, 40C7050C, 060D070E]
|
|
|
|
test_vavgsb_115_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [C00B080F, C0CE0007, 40060006, C8060006]
|
|
|
|
test_vavgsb_116_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [E0C70007, E0E70007, E0CDE6ED, E0001A20]
|
|
|
|
test_vavgsb_117_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [E1170007, 21D70007, E1D70007, 21FF0007]
|
|
|
|
test_vavgsb_118_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [E7EDE7ED, E7EDE7ED, E7EDE7ED, 02070108]
|
|
|
|
test_vavgsb_119_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [FC03FD04, FE05FF06, 00070108, 0209030A]
|
|
|
|
test_vavgsb_120_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [FF06FF06, FF06FF06, FF06FF06, FF06FF06]
|
|
|
|
test_vavgsb_121_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00050005, 00060006, 00070007, 00080008]
|
|
|
|
test_vavgsb_122_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00050046, 000800C7, 00050045, 000800C8]
|
|
|
|
test_vavgsb_123_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00060107, 383F0006, 00060006, 00070007]
|
|
|
|
test_vavgsb_124_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [000600C7, 00070046, 00060046, 000700C7]
|
|
|
|
test_vavgsb_125_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00060006, 00060006, 00060006, 00060006]
|
|
|
|
test_vavgsb_126_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [0009111A, 222B333C, C4CDD5DE, E6EFF700]
|
|
|
|
test_vavgsb_127_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [0009111A, 222B333C, C4CDD5DE, E6EFF700]
|
|
|
|
test_vavgsb_128_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00091119, 222A333C, C4CDD5DE, E6EEF700]
|
|
|
|
test_vavgsb_129_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [0009121B, 242D363F, C8D1DAE3, ECF5FE07]
|
|
|
|
test_vavgsb_130_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [000F1120, 22313342, C4D3D5E4, E6F5F706]
|
|
|
|
test_vavgsb_131_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [0008111A, 222B333C, C4CDD5DD, E6EEF7FF]
|
|
|
|
test_vavgsb_132_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [020B131C, 242D353E, C6CFD7E0, E8F1F902]
|
|
|
|
test_vavgsb_133_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [040C151D, 262E373F, C8D0D9E1, EAF2FB03]
|
|
|
|
test_vavgsb_134_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [040D151E, 262F3740, C8D1D9E2, EAF3FB04]
|
|
|
|
test_vavgsb_135_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [09121A23, 2B343C45, CDD6DEE7, EFF80009]
|
|
|
|
test_vavgsb_136_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [09233C56, E65D554C, CDDEEF00, 112233C4]
|
|
|
|
test_vavgsb_137_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [20C9111A, 420B333C, E493BBC4, 06E81119]
|
|
|
|
test_vavgsb_138_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [2119111A, 033B333C, E505D5DE, C727F700]
|
|
|
|
test_vavgsb_139_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [40C9121B, 242D363F, 048DDAE3, ECF5FE07]
|
|
|
|
test_vavgsb_140_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [C00D1922, E2F2333C, 04CCD5DD, AEEEF7FF]
|
|
|
|
test_vavgsb_141_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [E0C9111A, 020B333C, A493BBC4, C6E81119]
|
|
|
|
test_vavgsb_142_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [E119111A, 43FB333C, A59DD5DE, 07E7F700]
|
|
|
|
test_vavgsb_143_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [E7EFF800, 09111A22, ABB3BCC4, E8EFF801]
|
|
|
|
test_vavgsb_144_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [FC050E17, 2029323B, C4CDD6DF, E8F1FA03]
|
|
|
|
test_vavgsb_145_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [FF081019, 212A323B, C3CCD4DD, E5EEF6FF]
|
|
|
|
test_vavgsb_146_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00071118, 222A333B, C4CDD5DE, E6F0F701]
|
|
|
|
test_vavgsb_147_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00071159, 222C33FC, C4CBD51C, E6F0F7C1]
|
|
|
|
test_vavgsb_148_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0008121A, 5A63333B, C4CCD5DD, E6EFF700]
|
|
|
|
test_vavgsb_149_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [000811DA, 222B337B, C4CCD51D, E6EFF7C0]
|
|
|
|
test_vavgsb_150_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00081119, 222A333B, C4CCD5DD, E6EEF7FF]
|
|
|
|
test_vavgsb_151_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vavgsb_152_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000000, 00000000]
|
|
|
|
test_vavgsb_153_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [0000FF00, 00000000, 00000000, FFFF0000]
|
|
|
|
test_vavgsb_154_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000102, 02030304, 04050505, 06060707]
|
|
|
|
test_vavgsb_155_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00060007, 00070007, 00070006, 00060006]
|
|
|
|
test_vavgsb_156_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [0008111A, 222B333C, C4CDD5DD, E6EEF7FF]
|
|
|
|
test_vavgsb_157_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [02020202, 02020202, 02020202, 02020202]
|
|
|
|
test_vavgsb_158_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [04030304, 04040304, 03040403, 03030403]
|
|
|
|
test_vavgsb_159_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vavgsb_160_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [09090909, 09090909, 09090909, 09090909]
|
|
|
|
test_vavgsb_161_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [091A2B3C, C4332111, 08111A22, 2A333CC4]
|
|
|
|
test_vavgsb_162_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [20C00000, 20E00000, 1FC6E6E6, 1FF91A19]
|
|
|
|
test_vavgsb_163_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [21100000, E1100000, 20380000, E0380000]
|
|
|
|
test_vavgsb_164_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [40C00102, 02030304, 3FC00505, 06060707]
|
|
|
|
test_vavgsb_165_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [C0040808, C0C80000, 3F0000FF, C7FF00FF]
|
|
|
|
test_vavgsb_166_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [E0C00000, E0E00000, DFC6E6E6, DFF91A19]
|
|
|
|
test_vavgsb_167_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [E1100000, 21D00000, E0D00000, 20F80000]
|
|
|
|
test_vavgsb_168_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [E7E6E6E7, E7E7E6E7, E6E7E7E6, 02000101]
|
|
|
|
test_vavgsb_169_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [FCFCFDFE, FEFFFF00, 00010101, 02020303]
|
|
|
|
test_vavgsb_170_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
|
|
test_vavgsb_171_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00FEFFFF, 00FFFF00, 00000000, 00010001]
|
|
|
|
test_vavgsb_172_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00FEFF3F, 000100C1, FFFE003E, 000100C1]
|
|
|
|
test_vavgsb_173_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00FF0001, 3838FF00, FF0000FF, 00000000]
|
|
|
|
test_vavgsb_174_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00FFFFC0, 00000040, FFFF003F, 000000C0]
|
|
|
|
test_vavgsb_175_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
|
|
test_vavgsb_176_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [02020202, 02020202, 02020202, 02020202]
|
|
|
|
test_vavgsb_177_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [02020203, 02020203, 02020203, 02020203]
|
|
|
|
test_vavgsb_178_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [02020202, 02020202, 02020202, 02020202]
|
|
|
|
test_vavgsb_179_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [02030304, 04050506, 06070708, 0809090A]
|
|
|
|
test_vavgsb_180_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [02090209, 02090209, 02090209, 02090209]
|
|
|
|
test_vavgsb_181_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [020B131C, 242D353E, C6CFD7E0, E8F1F902]
|
|
|
|
test_vavgsb_182_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [02020202, 02020202, 02020202, 02020202]
|
|
|
|
test_vavgsb_183_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [06060606, 06060606, 06060606, 06060606]
|
|
|
|
test_vavgsb_184_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [06060606, 06060606, 06060606, 06060606]
|
|
|
|
test_vavgsb_185_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [0B0B0B0B, 0B0B0B0B, 0B0B0B0B, 0B0B0B0B]
|
|
|
|
test_vavgsb_186_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [0B1C2D3E, C6352413, 0B131C24, 2D353EC6]
|
|
|
|
test_vavgsb_187_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [22C20202, 22E20202, 22C8E8E9, 22FC1C1C]
|
|
|
|
test_vavgsb_188_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [23120202, E3120202, 233A0202, E33A0202]
|
|
|
|
test_vavgsb_189_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [42C20304, 04050506, 42C20708, 0809090A]
|
|
|
|
test_vavgsb_190_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [C2060A0A, C2CA0202, 42020202, CA020202]
|
|
|
|
test_vavgsb_191_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [E2C20202, E2E20202, E2C8E8E9, E2FC1C1C]
|
|
|
|
test_vavgsb_192_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [E3120202, 23D20202, E3D20202, 23FA0202]
|
|
|
|
test_vavgsb_193_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [E9E9E9E9, E9E9E9E9, E9E9E9E9, 04030304]
|
|
|
|
test_vavgsb_194_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [FEFFFF00, 00010102, 02030304, 04050506]
|
|
|
|
test_vavgsb_195_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
|
|
|
|
test_vavgsb_196_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [02000201, 02010202, 02020203, 02030204]
|
|
|
|
test_vavgsb_197_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [02010241, 020302C3, 02000241, 020402C3]
|
|
|
|
test_vavgsb_198_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [02020303, 3A3A0202, 02020202, 02020202]
|
|
|
|
test_vavgsb_199_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [020202C2, 02020242, 02010242, 020302C2]
|
|
|
|
test_vavgsb_200_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [02020202, 02020202, 02020202, 02020202]
|
|
|
|
test_vavgsb_201_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vavgsb_202_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vavgsb_203_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [04040303, 03030404, 04040404, 03030404]
|
|
|
|
test_vavgsb_204_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [04040505, 06060707, 08080909, 0A0A0B0B]
|
|
|
|
test_vavgsb_205_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [040A040A, 040A040A, 040A040A, 040A040A]
|
|
|
|
test_vavgsb_206_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [040C151D, 262E373F, C8D0D9E1, EAF2FB03]
|
|
|
|
test_vavgsb_207_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [04030304, 04040304, 03040403, 03030403]
|
|
|
|
test_vavgsb_208_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [06060606, 06060606, 06060606, 06060606]
|
|
|
|
test_vavgsb_209_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
|
|
|
|
test_vavgsb_210_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [0D0D0D0D, 0D0D0D0D, 0D0D0D0D, 0D0D0D0D]
|
|
|
|
test_vavgsb_211_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [0D1E2F40, C7362514, 0C151D26, 2E373FC8]
|
|
|
|
test_vavgsb_212_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [23C40404, 23E40404, 23CAEAEA, 23FD1D1D]
|
|
|
|
test_vavgsb_213_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [24140404, E4140404, 243C0404, E43C0404]
|
|
|
|
test_vavgsb_214_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [43C40505, 06060707, 43C40909, 0A0A0B0B]
|
|
|
|
test_vavgsb_215_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [C4080C0C, C4CB0404, 43030303, CB030303]
|
|
|
|
test_vavgsb_216_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [E3C40404, E3E40404, E3CAEAEA, E3FD1D1D]
|
|
|
|
test_vavgsb_217_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [E4140404, 24D40404, E4D40404, 24FC0404]
|
|
|
|
test_vavgsb_218_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [EAEAEAEA, EAEAEAEA, EAEAEAEA, 06040505]
|
|
|
|
test_vavgsb_219_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000101, 02020303, 04040505, 06060707]
|
|
|
|
test_vavgsb_220_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [03030303, 03030303, 03030303, 03030303]
|
|
|
|
test_vavgsb_221_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [03020302, 03030303, 04040404, 04050405]
|
|
|
|
test_vavgsb_222_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [03020343, 040504C4, 03020342, 040504C5]
|
|
|
|
test_vavgsb_223_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [03030404, 3C3C0303, 03030303, 04040404]
|
|
|
|
test_vavgsb_224_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [030303C4, 04040443, 03030343, 040404C4]
|
|
|
|
test_vavgsb_225_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [03030303, 03030303, 03030303, 03030303]
|
|
|
|
test_vavgsb_226_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vavgsb_227_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [04040405, 04040405, 04040405, 04040405]
|
|
|
|
test_vavgsb_228_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vavgsb_229_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [04050506, 06070708, 0809090A, 0A0B0B0C]
|
|
|
|
test_vavgsb_230_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [040B040B, 040B040B, 040B040B, 040B040B]
|
|
|
|
test_vavgsb_231_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [040D151E, 262F3740, C8D1D9E2, EAF3FB04]
|
|
|
|
test_vavgsb_232_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vavgsb_233_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [06060606, 06060606, 06060606, 06060606]
|
|
|
|
test_vavgsb_234_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
|
|
|
|
test_vavgsb_235_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [0D0D0D0D, 0D0D0D0D, 0D0D0D0D, 0D0D0D0D]
|
|
|
|
test_vavgsb_236_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [0D1E2F40, C8372615, 0D151E26, 2F3740C8]
|
|
|
|
test_vavgsb_237_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [24C40404, 24E40404, 24CAEAEB, 24FE1E1E]
|
|
|
|
test_vavgsb_238_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [25140404, E5140404, 253C0404, E53C0404]
|
|
|
|
test_vavgsb_239_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [44C40506, 06070708, 44C4090A, 0A0B0B0C]
|
|
|
|
test_vavgsb_240_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [C4080C0C, C4CC0404, 44040404, CC040404]
|
|
|
|
test_vavgsb_241_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [E4C40404, E4E40404, E4CAEAEB, E4FE1E1E]
|
|
|
|
test_vavgsb_242_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [E5140404, 25D40404, E5D40404, 25FC0404]
|
|
|
|
test_vavgsb_243_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [EBEBEBEB, EBEBEBEB, EBEBEBEB, 06050506]
|
|
|
|
test_vavgsb_244_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00010102, 02030304, 04050506, 06070708]
|
|
|
|
test_vavgsb_245_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [03030303, 03030303, 03030303, 03030303]
|
|
|
|
test_vavgsb_246_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [04020403, 04030404, 04040405, 04050406]
|
|
|
|
test_vavgsb_247_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [04030443, 040504C5, 04020443, 040604C5]
|
|
|
|
test_vavgsb_248_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [04040505, 3C3C0404, 04040404, 04040404]
|
|
|
|
test_vavgsb_249_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [040404C4, 04040444, 04030444, 040504C4]
|
|
|
|
test_vavgsb_250_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vavgsb_251_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [09090909, 09090909, 09090909, 09090909]
|
|
|
|
test_vavgsb_252_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [0909090A, 0909090A, 0909090A, 0909090A]
|
|
|
|
test_vavgsb_253_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [09090909, 09090909, 09090909, 09090909]
|
|
|
|
test_vavgsb_254_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [090A0A0B, 0B0C0C0D, 0D0E0E0F, 0F101011]
|
|
|
|
test_vavgsb_255_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [09100910, 09100910, 09100910, 09100910]
|
|
|
|
test_vavgsb_256_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [09121A23, 2B343C45, CDD6DEE7, EFF80009]
|
|
|
|
test_vavgsb_257_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [09090909, 09090909, 09090909, 09090909]
|
|
|
|
test_vavgsb_258_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [0B0B0B0B, 0B0B0B0B, 0B0B0B0B, 0B0B0B0B]
|
|
|
|
test_vavgsb_259_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [0D0D0D0D, 0D0D0D0D, 0D0D0D0D, 0D0D0D0D]
|
|
|
|
test_vavgsb_260_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [0D0D0D0D, 0D0D0D0D, 0D0D0D0D, 0D0D0D0D]
|
|
|
|
test_vavgsb_261_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [12233445, CD3C2B1A, 121A232B, 343C45CD]
|
|
|
|
test_vavgsb_262_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [29C90909, 29E90909, 29CFEFF0, 29032323]
|
|
|
|
test_vavgsb_263_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [2A190909, EA190909, 2A410909, EA410909]
|
|
|
|
test_vavgsb_264_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [49C90A0B, 0B0C0C0D, 49C90E0F, 0F101011]
|
|
|
|
test_vavgsb_265_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [C90D1111, C9D10909, 49090909, D1090909]
|
|
|
|
test_vavgsb_266_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [E9C90909, E9E90909, E9CFEFF0, E9032323]
|
|
|
|
test_vavgsb_267_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [EA190909, 2AD90909, EAD90909, 2A010909]
|
|
|
|
test_vavgsb_268_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [F0F0F0F0, F0F0F0F0, F0F0F0F0, 0B0A0A0B]
|
|
|
|
test_vavgsb_269_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [05060607, 07080809, 090A0A0B, 0B0C0C0D]
|
|
|
|
test_vavgsb_270_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
|
|
|
|
test_vavgsb_271_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [09070908, 09080909, 0909090A, 090A090B]
|
|
|
|
test_vavgsb_272_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [09080948, 090A09CA, 09070948, 090B09CA]
|
|
|
|
test_vavgsb_273_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [09090A0A, 41410909, 09090909, 09090909]
|
|
|
|
test_vavgsb_274_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [090909C9, 09090949, 09080949, 090A09C9]
|
|
|
|
test_vavgsb_275_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [09090909, 09090909, 09090909, 09090909]
|
|
|
|
test_vavgsb_276_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [091A2B3C, C4332211, 09111A22, 2B333CC4]
|
|
|
|
test_vavgsb_277_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [091A2B3D, C4332211, 09111A23, 2B333CC5]
|
|
|
|
test_vavgsb_278_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [091A2B3C, C3322211, 09111A22, 2A333CC4]
|
|
|
|
test_vavgsb_279_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [091B2C3E, C6352514, 0D161F28, 313A43CC]
|
|
|
|
test_vavgsb_280_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [09212B43, C4392217, 09181A29, 2B3A3CCB]
|
|
|
|
test_vavgsb_281_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [09233C56, E65D554C, CDDEEF00, 112233C4]
|
|
|
|
test_vavgsb_282_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [091A2B3C, C4332111, 08111A22, 2A333CC4]
|
|
|
|
test_vavgsb_283_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [0B1C2D3E, C6352413, 0B131C24, 2D353EC6]
|
|
|
|
test_vavgsb_284_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [0D1E2F40, C7362514, 0C151D26, 2E373FC8]
|
|
|
|
test_vavgsb_285_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [0D1E2F40, C8372615, 0D151E26, 2F3740C8]
|
|
|
|
test_vavgsb_286_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [12233445, CD3C2B1A, 121A232B, 343C45CD]
|
|
|
|
test_vavgsb_287_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [29DA2B3C, E3132211, 28D70009, 4A2D55DE]
|
|
|
|
test_vavgsb_288_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [2A2A2B3C, A4432211, 29491A22, 0B6B3CC4]
|
|
|
|
test_vavgsb_289_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [49DA2C3E, C6352514, 48D11F28, 313A43CC]
|
|
|
|
test_vavgsb_290_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [C91E3344, 84FA2211, 48111922, F2333BC4]
|
|
|
|
test_vavgsb_291_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [E9DA2B3C, A3132211, E8D70009, 0A2D55DE]
|
|
|
|
test_vavgsb_292_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [EA2A2B3C, E4032211, E9E11A22, 4B2B3CC4]
|
|
|
|
test_vavgsb_293_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [F0011223, AA1908F7, EFF80009, 2D343DC6]
|
|
|
|
test_vavgsb_294_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [0517283A, C2312110, 09121B24, 2D363FC8]
|
|
|
|
test_vavgsb_295_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [08192A3B, C3322110, 08101921, 2A323BC3]
|
|
|
|
test_vavgsb_296_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [09182B3B, C3322110, 09111A23, 2B343CC6]
|
|
|
|
test_vavgsb_297_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [09192B7B, C43422D1, 080F1961, 2B353C85]
|
|
|
|
test_vavgsb_298_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [091A2C3D, FC6B2110, 08111922, 2B333CC4]
|
|
|
|
test_vavgsb_299_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [091A2BFC, C4332250, 08101962, 2B343C84]
|
|
|
|
test_vavgsb_300_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [091A2B3C, C3322110, 08111922, 2A333BC4]
|
|
|
|
test_vavgsb_301_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [20C00000, 20E00000, 20C6E6E7, 20FA1A1A]
|
|
|
|
test_vavgsb_302_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [20C00001, 20E00001, 20C6E6E7, 20FA1A1A]
|
|
|
|
test_vavgsb_303_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [20C00000, 1FE00000, 20C6E6E7, 1FF91A1A]
|
|
|
|
test_vavgsb_304_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [20C10102, 22E30304, 24CBEBEC, 26002121]
|
|
|
|
test_vavgsb_305_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [20C70007, 20E70007, 20CDE6ED, 20001A20]
|
|
|
|
test_vavgsb_306_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [20C9111A, 420B333C, E493BBC4, 06E81119]
|
|
|
|
test_vavgsb_307_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [20C00000, 20E00000, 1FC6E6E6, 1FF91A19]
|
|
|
|
test_vavgsb_308_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [22C20202, 22E20202, 22C8E8E9, 22FC1C1C]
|
|
|
|
test_vavgsb_309_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [23C40404, 23E40404, 23CAEAEA, 23FD1D1D]
|
|
|
|
test_vavgsb_310_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [24C40404, 24E40404, 24CAEAEB, 24FE1E1E]
|
|
|
|
test_vavgsb_311_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [29C90909, 29E90909, 29CFEFF0, 29032323]
|
|
|
|
test_vavgsb_312_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [29DA2B3C, E3132211, 28D70009, 4A2D55DE]
|
|
|
|
test_vavgsb_313_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [40D00000, 00F00000, 40FEE6E7, 00321A1A]
|
|
|
|
test_vavgsb_314_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [5F800102, 22E30304, 5F86EBEC, 26002121]
|
|
|
|
test_vavgsb_315_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [E0C40808, E0A80000, 5FC6E6E6, E7F91919]
|
|
|
|
test_vavgsb_316_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [FF800000, FFC00000, FF8CCCCD, FFF33333]
|
|
|
|
test_vavgsb_317_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00D00000, 40B00000, 0096E6E7, 40F21A1A]
|
|
|
|
test_vavgsb_318_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [06A7E7E7, 06C7E7E7, 06ADCDCD, 22FA1B1B]
|
|
|
|
test_vavgsb_319_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [1CBDFDFE, 1EDFFF00, 20C7E7E8, 22FC1D1D]
|
|
|
|
test_vavgsb_320_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [1FBFFFFF, 1FDFFFFF, 1FC5E5E6, 1FF91919]
|
|
|
|
test_vavgsb_321_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [1FBE00FF, 1FDF0000, 20C6E6E7, 20FB1A1B]
|
|
|
|
test_vavgsb_322_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [1FBF003F, 20E100C1, 1FC4E625, 20FB1ADB]
|
|
|
|
test_vavgsb_323_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [1FC00101, 58180000, 1FC6E6E6, 20FA1A1A]
|
|
|
|
test_vavgsb_324_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [1FC000C0, 20E00040, 1FC5E626, 20FA1ADA]
|
|
|
|
test_vavgsb_325_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [1FC00000, 1FE00000, 1FC6E6E6, 1FF91919]
|
|
|
|
test_vavgsb_326_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [21100000, E1100000, 21380000, E1380000]
|
|
|
|
test_vavgsb_327_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [21100001, E1100001, 21380001, E1380001]
|
|
|
|
test_vavgsb_328_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [21100000, E0100000, 21380000, E0380000]
|
|
|
|
test_vavgsb_329_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [21110102, E3130304, 253D0506, E73F0708]
|
|
|
|
test_vavgsb_330_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [21170007, E1170007, 213F0007, E13F0007]
|
|
|
|
test_vavgsb_331_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [2119111A, 033B333C, E505D5DE, C727F700]
|
|
|
|
test_vavgsb_332_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [21100000, E1100000, 20380000, E0380000]
|
|
|
|
test_vavgsb_333_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [23120202, E3120202, 233A0202, E33A0202]
|
|
|
|
test_vavgsb_334_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [24140404, E4140404, 243C0404, E43C0404]
|
|
|
|
test_vavgsb_335_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [25140404, E5140404, 253C0404, E53C0404]
|
|
|
|
test_vavgsb_336_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [2A190909, EA190909, 2A410909, EA410909]
|
|
|
|
test_vavgsb_337_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [2A2A2B3C, A4432211, 29491A22, 0B6B3CC4]
|
|
|
|
test_vavgsb_338_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [40D00000, 00F00000, 40FEE6E7, 00321A1A]
|
|
|
|
test_vavgsb_339_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [60D00102, E3130304, 60F80506, E73F0708]
|
|
|
|
test_vavgsb_340_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [E1140808, A1D80000, 60380000, A8380000]
|
|
|
|
test_vavgsb_341_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00D00000, C0F00000, 00FEE6E7, C0321A1A]
|
|
|
|
test_vavgsb_342_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [01200000, 01E00000, 01080000, 01300000]
|
|
|
|
test_vavgsb_343_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [07F7E7E7, C7F7E7E7, 071FE7E7, E3390102]
|
|
|
|
test_vavgsb_344_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [1D0DFDFE, DF0FFF00, 21390102, E33B0304]
|
|
|
|
test_vavgsb_345_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [200FFFFF, E00FFFFF, 2037FFFF, E037FFFF]
|
|
|
|
test_vavgsb_346_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [200E00FF, E00F0000, 21380001, E1390002]
|
|
|
|
test_vavgsb_347_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [200F003F, E11100C1, 2036003F, E13A00C1]
|
|
|
|
test_vavgsb_348_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [20100101, 19480000, 20380000, E1380000]
|
|
|
|
test_vavgsb_349_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [201000C0, E1100040, 20370040, E13900C0]
|
|
|
|
test_vavgsb_350_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [20100000, E0100000, 20380000, E0380000]
|
|
|
|
test_vavgsb_351_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [40C00102, 02030304, 40C00506, 06070708]
|
|
|
|
test_vavgsb_352_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [40C00102, 02030304, 40C00506, 06070708]
|
|
|
|
test_vavgsb_353_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [40C00101, 02020304, 40C00506, 06060708]
|
|
|
|
test_vavgsb_354_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [40C10203, 04050607, 44C50A0B, 0C0D0E0F]
|
|
|
|
test_vavgsb_355_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [40C70108, 0209030A, 40C7050C, 060D070E]
|
|
|
|
test_vavgsb_356_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [40C9121B, 242D363F, 048DDAE3, ECF5FE07]
|
|
|
|
test_vavgsb_357_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [40C00102, 02030304, 3FC00505, 06060707]
|
|
|
|
test_vavgsb_358_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [42C20304, 04050506, 42C20708, 0809090A]
|
|
|
|
test_vavgsb_359_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [43C40505, 06060707, 43C40909, 0A0A0B0B]
|
|
|
|
test_vavgsb_360_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [44C40506, 06070708, 44C4090A, 0A0B0B0C]
|
|
|
|
test_vavgsb_361_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [49C90A0B, 0B0C0C0D, 49C90E0F, 0F101011]
|
|
|
|
test_vavgsb_362_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [49DA2C3E, C6352514, 48D11F28, 313A43CC]
|
|
|
|
test_vavgsb_363_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [5F800102, 22E30304, 5F86EBEC, 26002121]
|
|
|
|
test_vavgsb_364_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [60D00102, E3130304, 60F80506, E73F0708]
|
|
|
|
test_vavgsb_365_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00C4090A, C2CA0304, 7FC00505, CE060707]
|
|
|
|
test_vavgsb_366_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [1F800102, E2E30304, 1F86EBEC, E6002121]
|
|
|
|
test_vavgsb_367_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [20D00102, 23D30304, 20900506, 27FF0708]
|
|
|
|
test_vavgsb_368_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [26A7E8E8, E9E9EAEA, 26A7ECEC, 08070809]
|
|
|
|
test_vavgsb_369_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [3CBDFEFF, 00010203, 40C10607, 08090A0B]
|
|
|
|
test_vavgsb_370_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [3FBF0001, 01020203, 3FBF0405, 05060607]
|
|
|
|
test_vavgsb_371_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [3FBE0100, 02020303, 40C00506, 06080709]
|
|
|
|
test_vavgsb_372_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [3FBF0141, 020403C4, 3FBE0544, 060807C9]
|
|
|
|
test_vavgsb_373_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [3FC00202, 3A3B0303, 3FC00505, 06070708]
|
|
|
|
test_vavgsb_374_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [3FC001C2, 02030343, 3FBF0545, 060707C8]
|
|
|
|
test_vavgsb_375_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [3FC00101, 02020303, 3FC00505, 06060707]
|
|
|
|
test_vavgsb_376_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [C0040808, C0C80000, 40000000, C8000000]
|
|
|
|
test_vavgsb_377_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [C0040809, C0C80001, 40000000, C8000000]
|
|
|
|
test_vavgsb_378_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [C0040808, C0C70000, 40000000, C7FF0000]
|
|
|
|
test_vavgsb_379_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [C005090A, C2CA0304, 44040505, CE060707]
|
|
|
|
test_vavgsb_380_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [C00B080F, C0CE0007, 40060006, C8060006]
|
|
|
|
test_vavgsb_381_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [C00D1922, E2F2333C, 04CCD5DD, AEEEF7FF]
|
|
|
|
test_vavgsb_382_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [C0040808, C0C80000, 3F0000FF, C7FF00FF]
|
|
|
|
test_vavgsb_383_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [C2060A0A, C2CA0202, 42020202, CA020202]
|
|
|
|
test_vavgsb_384_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [C4080C0C, C4CB0404, 43030303, CB030303]
|
|
|
|
test_vavgsb_385_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [C4080C0C, C4CC0404, 44040404, CC040404]
|
|
|
|
test_vavgsb_386_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [C90D1111, C9D10909, 49090909, D1090909]
|
|
|
|
test_vavgsb_387_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [C91E3344, 84FA2211, 48111922, F2333BC4]
|
|
|
|
test_vavgsb_388_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [E0C40808, E0A80000, 5FC6E6E6, E7F91919]
|
|
|
|
test_vavgsb_389_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [E1140808, A1D80000, 60380000, A8380000]
|
|
|
|
test_vavgsb_390_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00C4090A, C2CA0304, 7FC00505, CE060707]
|
|
|
|
test_vavgsb_391_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [A0C40808, A0A80000, 1FC6E6E6, A7F91919]
|
|
|
|
test_vavgsb_392_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [A1140808, E1980000, 20D00000, E8F80000]
|
|
|
|
test_vavgsb_393_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [A7EBEFEF, A7AEE7E7, 26E6E6E6, CA000101]
|
|
|
|
test_vavgsb_394_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [BC010506, BEC6FF00, 40000101, CA020303]
|
|
|
|
test_vavgsb_395_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [BF030707, BFC7FFFF, 3FFFFFFF, C7FFFFFF]
|
|
|
|
test_vavgsb_396_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [C0020807, C0C70000, 40000000, C8010001]
|
|
|
|
test_vavgsb_397_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [C0030847, C0C900C1, 3FFEFF3E, C80100C1]
|
|
|
|
test_vavgsb_398_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [C0040909, F8000000, 3FFFFFFF, C8000000]
|
|
|
|
test_vavgsb_399_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [C00408C8, C0C80040, 3FFFFF3F, C80000C0]
|
|
|
|
test_vavgsb_400_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [C0040808, C0C70000, 3FFFFFFF, C7FFFFFF]
|
|
|
|
test_vavgsb_401_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [E0C00000, E0E00000, E0C6E6E7, E0FA1A1A]
|
|
|
|
test_vavgsb_402_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [E0C00001, E0E00001, E0C6E6E7, E0FA1A1A]
|
|
|
|
test_vavgsb_403_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [E0C00000, DFE00000, E0C6E6E7, DFF91A1A]
|
|
|
|
test_vavgsb_404_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [E0C10102, E2E30304, E4CBEBEC, E6002121]
|
|
|
|
test_vavgsb_405_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [E0C70007, E0E70007, E0CDE6ED, E0001A20]
|
|
|
|
test_vavgsb_406_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [E0C9111A, 020B333C, A493BBC4, C6E81119]
|
|
|
|
test_vavgsb_407_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [E0C00000, E0E00000, DFC6E6E6, DFF91A19]
|
|
|
|
test_vavgsb_408_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [E2C20202, E2E20202, E2C8E8E9, E2FC1C1C]
|
|
|
|
test_vavgsb_409_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [E3C40404, E3E40404, E3CAEAEA, E3FD1D1D]
|
|
|
|
test_vavgsb_410_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [E4C40404, E4E40404, E4CAEAEB, E4FE1E1E]
|
|
|
|
test_vavgsb_411_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [E9C90909, E9E90909, E9CFEFF0, E9032323]
|
|
|
|
test_vavgsb_412_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [E9DA2B3C, A3132211, E8D70009, 0A2D55DE]
|
|
|
|
test_vavgsb_413_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [FF800000, FFC00000, FF8CCCCD, FFF33333]
|
|
|
|
test_vavgsb_414_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00D00000, C0F00000, 00FEE6E7, C0321A1A]
|
|
|
|
test_vavgsb_415_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [1F800102, E2E30304, 1F86EBEC, E6002121]
|
|
|
|
test_vavgsb_416_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [A0C40808, A0A80000, 1FC6E6E6, A7F91919]
|
|
|
|
test_vavgsb_417_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [C0D00000, 00B00000, C096E6E7, 00F21A1A]
|
|
|
|
test_vavgsb_418_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [C6A7E7E7, C6C7E7E7, C6ADCDCD, E2FA1B1B]
|
|
|
|
test_vavgsb_419_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [DCBDFDFE, DEDFFF00, E0C7E7E8, E2FC1D1D]
|
|
|
|
test_vavgsb_420_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [DFBFFFFF, DFDFFFFF, DFC5E5E6, DFF91919]
|
|
|
|
test_vavgsb_421_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [DFBE00FF, DFDF0000, E0C6E6E7, E0FB1A1B]
|
|
|
|
test_vavgsb_422_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [DFBF003F, E0E100C1, DFC4E625, E0FB1ADB]
|
|
|
|
test_vavgsb_423_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [DFC00101, 18180000, DFC6E6E6, E0FA1A1A]
|
|
|
|
test_vavgsb_424_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [DFC000C0, E0E00040, DFC5E626, E0FA1ADA]
|
|
|
|
test_vavgsb_425_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [DFC00000, DFE00000, DFC6E6E6, DFF91919]
|
|
|
|
test_vavgsb_426_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [E1100000, 21D00000, E1D00000, 21F80000]
|
|
|
|
test_vavgsb_427_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [E1100001, 21D00001, E1D00001, 21F80001]
|
|
|
|
test_vavgsb_428_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [E1100000, 20D00000, E1D00000, 20F80000]
|
|
|
|
test_vavgsb_429_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [E1110102, 23D30304, E5D50506, 27FF0708]
|
|
|
|
test_vavgsb_430_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [E1170007, 21D70007, E1D70007, 21FF0007]
|
|
|
|
test_vavgsb_431_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [E119111A, 43FB333C, A59DD5DE, 07E7F700]
|
|
|
|
test_vavgsb_432_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [E1100000, 21D00000, E0D00000, 20F80000]
|
|
|
|
test_vavgsb_433_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [E3120202, 23D20202, E3D20202, 23FA0202]
|
|
|
|
test_vavgsb_434_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [E4140404, 24D40404, E4D40404, 24FC0404]
|
|
|
|
test_vavgsb_435_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [E5140404, 25D40404, E5D40404, 25FC0404]
|
|
|
|
test_vavgsb_436_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [EA190909, 2AD90909, EAD90909, 2A010909]
|
|
|
|
test_vavgsb_437_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [EA2A2B3C, E4032211, E9E11A22, 4B2B3CC4]
|
|
|
|
test_vavgsb_438_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00D00000, 40B00000, 0096E6E7, 40F21A1A]
|
|
|
|
test_vavgsb_439_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [01200000, 01E00000, 01080000, 01300000]
|
|
|
|
test_vavgsb_440_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [20D00102, 23D30304, 20900506, 27FF0708]
|
|
|
|
test_vavgsb_441_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [A1140808, E1980000, 20D00000, E8F80000]
|
|
|
|
test_vavgsb_442_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [C0D00000, 00B00000, C096E6E7, 00F21A1A]
|
|
|
|
test_vavgsb_443_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [C7F7E7E7, 07B7E7E7, C7B7E7E7, 23F90102]
|
|
|
|
test_vavgsb_444_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [DD0DFDFE, 1FCFFF00, E1D10102, 23FB0304]
|
|
|
|
test_vavgsb_445_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [E00FFFFF, 20CFFFFF, E0CFFFFF, 20F7FFFF]
|
|
|
|
test_vavgsb_446_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [E00E00FF, 20CF0000, E1D00001, 21F90002]
|
|
|
|
test_vavgsb_447_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [E00F003F, 21D100C1, E0CE003F, 21FA00C1]
|
|
|
|
test_vavgsb_448_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [E0100101, 59080000, E0D00000, 21F80000]
|
|
|
|
test_vavgsb_449_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [E01000C0, 21D00040, E0CF0040, 21F900C0]
|
|
|
|
test_vavgsb_450_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [E0100000, 20D00000, E0D00000, 20F80000]
|
|
|
|
test_vavgsb_451_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [E7E7E7E7, E7E7E7E7, E7E7E7E7, 02010102]
|
|
|
|
test_vavgsb_452_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [E7E7E7E7, E7E7E7E7, E7E7E7E7, 02010102]
|
|
|
|
test_vavgsb_453_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [E7E7E6E6, E6E6E7E7, E7E7E7E7, 02000102]
|
|
|
|
test_vavgsb_454_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [E7E7E8E8, E9E9EAEA, EBEBECEC, 08070809]
|
|
|
|
test_vavgsb_455_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [E7EDE7ED, E7EDE7ED, E7EDE7ED, 02070108]
|
|
|
|
test_vavgsb_456_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [E7EFF800, 09111A22, ABB3BCC4, E8EFF801]
|
|
|
|
test_vavgsb_457_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [E7E6E6E7, E7E7E6E7, E6E7E7E6, 02000101]
|
|
|
|
test_vavgsb_458_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [E9E9E9E9, E9E9E9E9, E9E9E9E9, 04030304]
|
|
|
|
test_vavgsb_459_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [EAEAEAEA, EAEAEAEA, EAEAEAEA, 06040505]
|
|
|
|
test_vavgsb_460_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [EBEBEBEB, EBEBEBEB, EBEBEBEB, 06050506]
|
|
|
|
test_vavgsb_461_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [F0F0F0F0, F0F0F0F0, F0F0F0F0, 0B0A0A0B]
|
|
|
|
test_vavgsb_462_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [F0011223, AA1908F7, EFF80009, 2D343DC6]
|
|
|
|
test_vavgsb_463_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [06A7E7E7, 06C7E7E7, 06ADCDCD, 22FA1B1B]
|
|
|
|
test_vavgsb_464_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [07F7E7E7, C7F7E7E7, 071FE7E7, E3390102]
|
|
|
|
test_vavgsb_465_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [26A7E8E8, E9E9EAEA, 26A7ECEC, 08070809]
|
|
|
|
test_vavgsb_466_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [A7EBEFEF, A7AEE7E7, 26E6E6E6, CA000101]
|
|
|
|
test_vavgsb_467_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [C6A7E7E7, C6C7E7E7, C6ADCDCD, E2FA1B1B]
|
|
|
|
test_vavgsb_468_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [C7F7E7E7, 07B7E7E7, C7B7E7E7, 23F90102]
|
|
|
|
test_vavgsb_469_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [E3E3E4E4, E5E5E6E6, E7E7E8E8, 04030405]
|
|
|
|
test_vavgsb_470_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [E6E6E6E6, E6E6E6E6, E6E6E6E6, 01000001]
|
|
|
|
test_vavgsb_471_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [E6E5E6E5, E6E6E6E6, E7E7E7E7, 02020103]
|
|
|
|
test_vavgsb_472_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [E6E5E626, E7E8E7A7, E6E5E625, 020201C3]
|
|
|
|
test_vavgsb_473_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [E6E6E7E7, 1F1FE6E6, E6E6E6E6, 02010102]
|
|
|
|
test_vavgsb_474_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [E6E6E6A7, E7E7E726, E6E6E626, 020101C2]
|
|
|
|
test_vavgsb_475_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [E6E6E6E6, E6E6E6E6, E6E6E6E6, 02000101]
|
|
|
|
test_vavgsb_476_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FCFDFDFE, FEFFFF00, 00010102, 02030304]
|
|
|
|
test_vavgsb_477_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FCFDFDFE, FEFFFF00, 00010102, 02030304]
|
|
|
|
test_vavgsb_478_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [FCFDFDFD, FEFEFF00, 00010102, 02020304]
|
|
|
|
test_vavgsb_479_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FCFDFEFF, 00010203, 04050607, 08090A0B]
|
|
|
|
test_vavgsb_480_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [FC03FD04, FE05FF06, 00070108, 0209030A]
|
|
|
|
test_vavgsb_481_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FC050E17, 2029323B, C4CDD6DF, E8F1FA03]
|
|
|
|
test_vavgsb_482_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FCFCFDFE, FEFFFF00, 00010101, 02020303]
|
|
|
|
test_vavgsb_483_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [FEFFFF00, 00010102, 02030304, 04050506]
|
|
|
|
test_vavgsb_484_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [00000101, 02020303, 04040505, 06060707]
|
|
|
|
test_vavgsb_485_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [00010102, 02030304, 04050506, 06070708]
|
|
|
|
test_vavgsb_486_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [05060607, 07080809, 090A0A0B, 0B0C0C0D]
|
|
|
|
test_vavgsb_487_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [0517283A, C2312110, 09121B24, 2D363FC8]
|
|
|
|
test_vavgsb_488_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [1CBDFDFE, 1EDFFF00, 20C7E7E8, 22FC1D1D]
|
|
|
|
test_vavgsb_489_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [1D0DFDFE, DF0FFF00, 21390102, E33B0304]
|
|
|
|
test_vavgsb_490_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [3CBDFEFF, 00010203, 40C10607, 08090A0B]
|
|
|
|
test_vavgsb_491_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [BC010506, BEC6FF00, 40000101, CA020303]
|
|
|
|
test_vavgsb_492_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [DCBDFDFE, DEDFFF00, E0C7E7E8, E2FC1D1D]
|
|
|
|
test_vavgsb_493_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [DD0DFDFE, 1FCFFF00, E1D10102, 23FB0304]
|
|
|
|
test_vavgsb_494_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [E3E3E4E4, E5E5E6E6, E7E7E8E8, 04030405]
|
|
|
|
test_vavgsb_495_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [FBFCFCFD, FDFEFEFF, FF000001, 01020203]
|
|
|
|
test_vavgsb_496_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [FCFBFDFC, FEFEFFFF, 00010102, 02040305]
|
|
|
|
test_vavgsb_497_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [FCFBFD3D, FE00FFC0, 00FF0140, 020403C5]
|
|
|
|
test_vavgsb_498_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [FCFCFEFE, 3637FFFF, 00000101, 02030304]
|
|
|
|
test_vavgsb_499_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [FCFCFDBE, FEFFFF3F, 00000141, 020303C4]
|
|
|
|
test_vavgsb_500_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [FCFCFDFD, FEFEFFFF, 00000101, 02020303]
|
|
|
|
test_vavgsb_501_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
|
|
test_vavgsb_502_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FFFFFF00, FFFFFF00, FFFFFF00, FFFFFF00]
|
|
|
|
test_vavgsb_503_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
|
|
test_vavgsb_504_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FF000001, 01020203, 03040405, 05060607]
|
|
|
|
test_vavgsb_505_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [FF06FF06, FF06FF06, FF06FF06, FF06FF06]
|
|
|
|
test_vavgsb_506_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FF081019, 212A323B, C3CCD4DD, E5EEF6FF]
|
|
|
|
test_vavgsb_507_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
|
|
test_vavgsb_508_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
|
|
|
|
test_vavgsb_509_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [03030303, 03030303, 03030303, 03030303]
|
|
|
|
test_vavgsb_510_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [03030303, 03030303, 03030303, 03030303]
|
|
|
|
test_vavgsb_511_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
|
|
|
|
test_vavgsb_512_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [08192A3B, C3322110, 08101921, 2A323BC3]
|
|
|
|
test_vavgsb_513_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [1FBFFFFF, 1FDFFFFF, 1FC5E5E6, 1FF91919]
|
|
|
|
test_vavgsb_514_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [200FFFFF, E00FFFFF, 2037FFFF, E037FFFF]
|
|
|
|
test_vavgsb_515_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [3FBF0001, 01020203, 3FBF0405, 05060607]
|
|
|
|
test_vavgsb_516_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [BF030707, BFC7FFFF, 3FFFFFFF, C7FFFFFF]
|
|
|
|
test_vavgsb_517_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [DFBFFFFF, DFDFFFFF, DFC5E5E6, DFF91919]
|
|
|
|
test_vavgsb_518_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [E00FFFFF, 20CFFFFF, E0CFFFFF, 20F7FFFF]
|
|
|
|
test_vavgsb_519_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [E6E6E6E6, E6E6E6E6, E6E6E6E6, 01000001]
|
|
|
|
test_vavgsb_520_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [FBFCFCFD, FDFEFEFF, FF000001, 01020203]
|
|
|
|
test_vavgsb_521_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [FFFDFFFE, FFFEFFFF, FFFFFF00, FF00FF01]
|
|
|
|
test_vavgsb_522_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [FFFEFF3E, FF00FFC0, FFFDFF3E, FF01FFC0]
|
|
|
|
test_vavgsb_523_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFF0000, 3737FFFF, FFFFFFFF, FFFFFFFF]
|
|
|
|
test_vavgsb_524_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [FFFFFFBF, FFFFFF3F, FFFEFF3F, FF00FFBF]
|
|
|
|
test_vavgsb_525_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
|
|
test_vavgsb_526_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00FE00FF, 00FF0000, 00000001, 00010002]
|
|
|
|
test_vavgsb_527_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00FE00FF, 00FF0000, 00000001, 00010002]
|
|
|
|
test_vavgsb_528_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00FEFFFE, FFFF0000, 00000001, 00010002]
|
|
|
|
test_vavgsb_529_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00FF0100, 02020303, 04050506, 06080709]
|
|
|
|
test_vavgsb_530_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00050005, 00060006, 00070007, 00080008]
|
|
|
|
test_vavgsb_531_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00071118, 222A333B, C4CDD5DE, E6F0F701]
|
|
|
|
test_vavgsb_532_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00FEFFFF, 00FFFF00, 00000000, 00010001]
|
|
|
|
test_vavgsb_533_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [02000201, 02010202, 02020203, 02030204]
|
|
|
|
test_vavgsb_534_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [03020302, 03030303, 04040404, 04050405]
|
|
|
|
test_vavgsb_535_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [04020403, 04030404, 04040405, 04050406]
|
|
|
|
test_vavgsb_536_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [09070908, 09080909, 0909090A, 090A090B]
|
|
|
|
test_vavgsb_537_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [09182B3B, C3322110, 09111A23, 2B343CC6]
|
|
|
|
test_vavgsb_538_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [1FBE00FF, 1FDF0000, 20C6E6E7, 20FB1A1B]
|
|
|
|
test_vavgsb_539_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [200E00FF, E00F0000, 21380001, E1390002]
|
|
|
|
test_vavgsb_540_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [3FBE0100, 02020303, 40C00506, 06080709]
|
|
|
|
test_vavgsb_541_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [C0020807, C0C70000, 40000000, C8010001]
|
|
|
|
test_vavgsb_542_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [DFBE00FF, DFDF0000, E0C6E6E7, E0FB1A1B]
|
|
|
|
test_vavgsb_543_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [E00E00FF, 20CF0000, E1D00001, 21F90002]
|
|
|
|
test_vavgsb_544_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [E6E5E6E5, E6E6E6E6, E7E7E7E7, 02020103]
|
|
|
|
test_vavgsb_545_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [FCFBFDFC, FEFEFFFF, 00010102, 02040305]
|
|
|
|
test_vavgsb_546_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [FFFDFFFE, FFFEFFFF, FFFFFF00, FF00FF01]
|
|
|
|
test_vavgsb_547_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [FFFDFF3E, 000000C0, 00FE003F, 000300C3]
|
|
|
|
test_vavgsb_548_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFE00FF, 3837FFFF, 00000000, 00010002]
|
|
|
|
test_vavgsb_549_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [FFFEFFBF, 00FF003F, 00FF0040, 000200C2]
|
|
|
|
test_vavgsb_550_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [FFFEFFFE, FFFFFFFF, 00000000, 00010001]
|
|
|
|
test_vavgsb_551_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00FF003F, 000100C1, 00FE003F, 000200C1]
|
|
|
|
test_vavgsb_552_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00FF0040, 000100C1, 00FE003F, 000200C2]
|
|
|
|
test_vavgsb_553_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00FFFF3F, 000100C1, 00FE003F, 000100C1]
|
|
|
|
test_vavgsb_554_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00FF0141, 020403C4, 04030544, 060807C9]
|
|
|
|
test_vavgsb_555_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00050046, 000800C7, 00050045, 000800C8]
|
|
|
|
test_vavgsb_556_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00071159, 222C33FC, C4CBD51C, E6F0F7C1]
|
|
|
|
test_vavgsb_557_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00FEFF3F, 000100C1, FFFE003E, 000100C1]
|
|
|
|
test_vavgsb_558_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [02010241, 020302C3, 02000241, 020402C3]
|
|
|
|
test_vavgsb_559_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [03020343, 040504C4, 03020342, 040504C5]
|
|
|
|
test_vavgsb_560_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [04030443, 040504C5, 04020443, 040604C5]
|
|
|
|
test_vavgsb_561_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [09080948, 090A09CA, 09070948, 090B09CA]
|
|
|
|
test_vavgsb_562_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [09192B7B, C43422D1, 080F1961, 2B353C85]
|
|
|
|
test_vavgsb_563_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [1FBF003F, 20E100C1, 1FC4E625, 20FB1ADB]
|
|
|
|
test_vavgsb_564_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [200F003F, E11100C1, 2036003F, E13A00C1]
|
|
|
|
test_vavgsb_565_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [3FBF0141, 020403C4, 3FBE0544, 060807C9]
|
|
|
|
test_vavgsb_566_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [C0030847, C0C900C1, 3FFEFF3E, C80100C1]
|
|
|
|
test_vavgsb_567_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [DFBF003F, E0E100C1, DFC4E625, E0FB1ADB]
|
|
|
|
test_vavgsb_568_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [E00F003F, 21D100C1, E0CE003F, 21FA00C1]
|
|
|
|
test_vavgsb_569_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [E6E5E626, E7E8E7A7, E6E5E625, 020201C3]
|
|
|
|
test_vavgsb_570_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [FCFBFD3D, FE00FFC0, 00FF0140, 020403C5]
|
|
|
|
test_vavgsb_571_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [FFFEFF3E, FF00FFC0, FFFDFF3E, FF01FFC0]
|
|
|
|
test_vavgsb_572_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [FFFDFF3E, 000000C0, 00FE003F, 000300C3]
|
|
|
|
test_vavgsb_573_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFE0040, 383900C0, FFFEFF3E, 000200C1]
|
|
|
|
test_vavgsb_574_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [FFFEFFFF, 00010000, FFFDFF7E, 00020081]
|
|
|
|
test_vavgsb_575_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [FFFEFF3F, 000100C0, FFFEFF3E, 000100C1]
|
|
|
|
test_vavgsb_576_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00000101, 38380000, 00000000, 00000000]
|
|
|
|
test_vavgsb_577_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00000101, 38380000, 00000000, 00000001]
|
|
|
|
test_vavgsb_578_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, 38380000, 00000000, 00000000]
|
|
|
|
test_vavgsb_579_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000202, 3A3B0303, 04040505, 06070708]
|
|
|
|
test_vavgsb_580_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00060107, 383F0006, 00060006, 00070007]
|
|
|
|
test_vavgsb_581_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [0008121A, 5A63333B, C4CCD5DD, E6EFF700]
|
|
|
|
test_vavgsb_582_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00FF0001, 3838FF00, FF0000FF, 00000000]
|
|
|
|
test_vavgsb_583_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [02020303, 3A3A0202, 02020202, 02020202]
|
|
|
|
test_vavgsb_584_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [03030404, 3C3C0303, 03030303, 04040404]
|
|
|
|
test_vavgsb_585_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [04040505, 3C3C0404, 04040404, 04040404]
|
|
|
|
test_vavgsb_586_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [09090A0A, 41410909, 09090909, 09090909]
|
|
|
|
test_vavgsb_587_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [091A2C3D, FC6B2110, 08111922, 2B333CC4]
|
|
|
|
test_vavgsb_588_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [1FC00101, 58180000, 1FC6E6E6, 20FA1A1A]
|
|
|
|
test_vavgsb_589_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [20100101, 19480000, 20380000, E1380000]
|
|
|
|
test_vavgsb_590_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [3FC00202, 3A3B0303, 3FC00505, 06070708]
|
|
|
|
test_vavgsb_591_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [C0040909, F8000000, 3FFFFFFF, C8000000]
|
|
|
|
test_vavgsb_592_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [DFC00101, 18180000, DFC6E6E6, E0FA1A1A]
|
|
|
|
test_vavgsb_593_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [E0100101, 59080000, E0D00000, 21F80000]
|
|
|
|
test_vavgsb_594_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [E6E6E7E7, 1F1FE6E6, E6E6E6E6, 02010102]
|
|
|
|
test_vavgsb_595_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [FCFCFEFE, 3637FFFF, 00000101, 02030304]
|
|
|
|
test_vavgsb_596_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [FFFF0000, 3737FFFF, FFFFFFFF, FFFFFFFF]
|
|
|
|
test_vavgsb_597_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [FFFE00FF, 3837FFFF, 00000000, 00010002]
|
|
|
|
test_vavgsb_598_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [FFFE0040, 383900C0, FFFEFF3E, 000200C1]
|
|
|
|
test_vavgsb_599_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [FFFF00C1, 3838003F, FFFFFF3F, 000100C0]
|
|
|
|
test_vavgsb_600_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [FFFF0000, 3838FFFF, FFFFFFFF, 00000000]
|
|
|
|
test_vavgsb_601_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [000000C0, 00000040, 00FF0040, 000100C0]
|
|
|
|
test_vavgsb_602_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [000000C1, 00000040, 00FF0040, 000100C1]
|
|
|
|
test_vavgsb_603_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [0000FFC0, 00000040, 00FF0040, 000000C0]
|
|
|
|
test_vavgsb_604_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [000001C2, 02030343, 04040545, 060707C8]
|
|
|
|
test_vavgsb_605_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [000600C7, 00070046, 00060046, 000700C7]
|
|
|
|
test_vavgsb_606_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [000811DA, 222B337B, C4CCD51D, E6EFF7C0]
|
|
|
|
test_vavgsb_607_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00FFFFC0, 00000040, FFFF003F, 000000C0]
|
|
|
|
test_vavgsb_608_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [020202C2, 02020242, 02010242, 020302C2]
|
|
|
|
test_vavgsb_609_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [030303C4, 04040443, 03030343, 040404C4]
|
|
|
|
test_vavgsb_610_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [040404C4, 04040444, 04030444, 040504C4]
|
|
|
|
test_vavgsb_611_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [090909C9, 09090949, 09080949, 090A09C9]
|
|
|
|
test_vavgsb_612_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [091A2BFC, C4332250, 08101962, 2B343C84]
|
|
|
|
test_vavgsb_613_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [1FC000C0, 20E00040, 1FC5E626, 20FA1ADA]
|
|
|
|
test_vavgsb_614_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [201000C0, E1100040, 20370040, E13900C0]
|
|
|
|
test_vavgsb_615_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [3FC001C2, 02030343, 3FBF0545, 060707C8]
|
|
|
|
test_vavgsb_616_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [C00408C8, C0C80040, 3FFFFF3F, C80000C0]
|
|
|
|
test_vavgsb_617_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [DFC000C0, E0E00040, DFC5E626, E0FA1ADA]
|
|
|
|
test_vavgsb_618_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [E01000C0, 21D00040, E0CF0040, 21F900C0]
|
|
|
|
test_vavgsb_619_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [E6E6E6A7, E7E7E726, E6E6E626, 020101C2]
|
|
|
|
test_vavgsb_620_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [FCFCFDBE, FEFFFF3F, 00000141, 020303C4]
|
|
|
|
test_vavgsb_621_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [FFFFFFBF, FFFFFF3F, FFFEFF3F, FF00FFBF]
|
|
|
|
test_vavgsb_622_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [FFFEFFBF, 00FF003F, 00FF0040, 000200C2]
|
|
|
|
test_vavgsb_623_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [FFFEFFFF, 00010000, FFFDFF7E, 00020081]
|
|
|
|
test_vavgsb_624_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFF00C1, 3838003F, FFFFFF3F, 000100C0]
|
|
|
|
test_vavgsb_625_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [FFFFFFC0, 0000003F, FFFFFF3F, 000000C0]
|
|
|
|
test_vavgsb_626_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vavgsb_627_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vavgsb_628_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
|
|
test_vavgsb_629_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000101, 02020303, 04040505, 06060707]
|
|
|
|
test_vavgsb_630_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00060006, 00060006, 00060006, 00060006]
|
|
|
|
test_vavgsb_631_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00081119, 222A333B, C4CCD5DD, E6EEF7FF]
|
|
|
|
test_vavgsb_632_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
|
|
test_vavgsb_633_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [02020202, 02020202, 02020202, 02020202]
|
|
|
|
test_vavgsb_634_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [03030303, 03030303, 03030303, 03030303]
|
|
|
|
test_vavgsb_635_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vavgsb_636_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [09090909, 09090909, 09090909, 09090909]
|
|
|
|
test_vavgsb_637_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
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|
#_ REGISTER_OUT v3 [091A2B3C, C3322110, 08111922, 2A333BC4]
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|
|
|
test_vavgsb_638_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [1FC00000, 1FE00000, 1FC6E6E6, 1FF91919]
|
|
|
|
test_vavgsb_639_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [20100000, E0100000, 20380000, E0380000]
|
|
|
|
test_vavgsb_640_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [3FC00101, 02020303, 3FC00505, 06060707]
|
|
|
|
test_vavgsb_641_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [C0040808, C0C70000, 3FFFFFFF, C7FFFFFF]
|
|
|
|
test_vavgsb_642_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [DFC00000, DFE00000, DFC6E6E6, DFF91919]
|
|
|
|
test_vavgsb_643_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [E0100000, 20D00000, E0D00000, 20F80000]
|
|
|
|
test_vavgsb_644_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [E6E6E6E6, E6E6E6E6, E6E6E6E6, 02000101]
|
|
|
|
test_vavgsb_645_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [FCFCFDFD, FEFEFFFF, 00000101, 02020303]
|
|
|
|
test_vavgsb_646_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
|
|
test_vavgsb_647_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [FFFEFFFE, FFFFFFFF, 00000000, 00010001]
|
|
|
|
test_vavgsb_648_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [FFFEFF3F, 000100C0, FFFEFF3E, 000100C1]
|
|
|
|
test_vavgsb_649_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFF0000, 3838FFFF, FFFFFFFF, 00000000]
|
|
|
|
test_vavgsb_650_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vavgsb v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [FFFFFFC0, 0000003F, FFFFFF3F, 000000C0]
|
|
|