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Xenia-Canary/src/xenia/cpu/ppc/testing/instr__gen_vor.s
Dr. Chat 54582cc823 Generated tests from Rick
2019-04-04 18:13:11 -05:00

5851 lines
222 KiB
ArmAsm
Raw Blame History

test_vor_1_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
test_vor_2_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
test_vor_3_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_vor_4_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
test_vor_5_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
test_vor_6_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
test_vor_7_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
test_vor_8_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707]
test_vor_9_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
test_vor_10_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212]
test_vor_11_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788]
test_vor_12_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
test_vor_13_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
test_vor_14_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
test_vor_15_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
test_vor_16_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333]
test_vor_17_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000]
test_vor_18_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
test_vor_19_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
test_vor_20_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
test_vor_21_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
test_vor_22_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
test_vor_23_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
test_vor_24_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
test_vor_25_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_26_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
test_vor_27_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0001, 00000001, FFFF0001]
test_vor_28_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_vor_29_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
test_vor_30_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
test_vor_31_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [00FFFF01, 0000FF01, FF0000FF, FFFF00FF]
test_vor_32_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [04040405, 04040405, 04040405, 04040405]
test_vor_33_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707]
test_vor_34_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [08080809, 08080809, 08080809, 08080809]
test_vor_35_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [12121213, 12121213, 12121213, 12121213]
test_vor_36_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [12345679, 87654321, 11223345, 55667789]
test_vor_37_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [3F800001, 3FC00001, 3F8CCCCD, 3FF33333]
test_vor_38_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [41200001, C1200001, 41700001, C1700001]
test_vor_39_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
test_vor_40_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [80081011, 808F0001, 7FFFFFFF, 8FFFFFFF]
test_vor_41_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [BF800001, BFC00001, BF8CCCCD, BFF33333]
test_vor_42_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [C1200001, 41A00001, C1A00001, 41F00001]
test_vor_43_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
test_vor_44_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
test_vor_45_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FEFEFEFF, FEFEFEFF, FEFEFEFF, FEFEFEFF]
test_vor_46_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
test_vor_47_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFDFF7F, 00020081, FFFCFF7D, 00030083]
test_vor_48_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000001]
test_vor_49_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFF81, 0000007F, FFFEFF7F, 00010081]
test_vor_50_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_51_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
test_vor_52_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0001, 00000001, FFFF0001]
test_vor_53_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [0001FFFF, FFFF0607, 08090A0B, FFFF0E0F]
test_vor_54_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [000DFFFF, FFFF000D, 000D000D, FFFF000D]
test_vor_55_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [0011FFFF, FFFF6677, 8899AABB, FFFFEEFF]
test_vor_56_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [00FFFFFF, FFFFFF00, FF0000FF, FFFF00FF]
test_vor_57_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [0404FFFF, FFFF0404, 04040404, FFFF0404]
test_vor_58_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [0707FFFF, FFFF0707, 07070707, FFFF0707]
test_vor_59_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [0808FFFF, FFFF0808, 08080808, FFFF0808]
test_vor_60_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [1212FFFF, FFFF1212, 12121212, FFFF1212]
test_vor_61_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [1234FFFF, FFFF4321, 11223344, FFFF7788]
test_vor_62_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [3F80FFFF, FFFF0000, 3F8CCCCD, FFFF3333]
test_vor_63_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [4120FFFF, FFFF0000, 41700000, FFFF0000]
test_vor_64_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7F80FFFF, FFFF0607, 7F800A0B, FFFF0E0F]
test_vor_65_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [8008FFFF, FFFF0000, 7FFFFFFF, FFFFFFFF]
test_vor_66_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [BF80FFFF, FFFF0000, BF8CCCCD, FFFF3333]
test_vor_67_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [C120FFFF, FFFF0000, C1A00000, FFFF0000]
test_vor_68_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [CDCDFFFF, FFFFCDCD, CDCDCDCD, FFFF0203]
test_vor_69_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [F8F9FFFF, FFFFFEFF, 00010203, FFFF0607]
test_vor_70_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FEFEFFFF, FFFFFEFE, FEFEFEFE, FFFFFEFE]
test_vor_71_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFCFFFF, FFFFFFFF, 00000001, FFFF0003]
test_vor_72_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFDFFFF, FFFF0081, FFFCFF7D, FFFF0082]
test_vor_73_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF0000]
test_vor_74_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFF007F, FFFEFF7F, FFFF0080]
test_vor_75_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_76_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_vor_77_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_vor_78_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [0001FFFF, FFFF0607, 08090A0B, FFFF0E0F]
test_vor_79_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [000D020F, 040D060F, 080D0A0F, 0C0D0E0F]
test_vor_80_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
test_vor_81_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [00FFFF03, 0405FF07, FF090AFF, FFFF0EFF]
test_vor_82_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [04050607, 04050607, 0C0D0E0F, 0C0D0E0F]
test_vor_83_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [07070707, 07070707, 0F0F0F0F, 0F0F0F0F]
test_vor_84_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [08090A0B, 0C0D0E0F, 08090A0B, 0C0D0E0F]
test_vor_85_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [12131213, 16171617, 1A1B1A1B, 1E1F1E1F]
test_vor_86_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [1235567B, 87654727, 192B3B4F, 5D6F7F8F]
test_vor_87_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [3F810203, 3FC50607, 3F8DCECF, 3FFF3F3F]
test_vor_88_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [41210203, C5250607, 49790A0B, CD7D0E0F]
test_vor_89_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7F810203, 04050607, 7F890A0B, 0C0D0E0F]
test_vor_90_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [80091213, 848F0607, 7FFFFFFF, 8FFFFFFF]
test_vor_91_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [BF810203, BFC50607, BF8DCECF, BFFF3F3F]
test_vor_92_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [C1210203, 45A50607, C9A90A0B, 4DFD0E0F]
test_vor_93_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [CDCDCFCF, CDCDCFCF, CDCDCFCF, 0C0D0E0F]
test_vor_94_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 08090A0B, 0C0D0E0F]
test_vor_95_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FEFFFEFF, FEFFFEFF, FEFFFEFF, FEFFFEFF]
test_vor_96_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFDFFFF, FFFFFFFF, 08090A0B, 0C0F0E0F]
test_vor_97_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFDFF7F, 04070687, FFFDFF7F, 0C0F0E8F]
test_vor_98_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFF0303, 7475FFFF, FFFFFFFF, 0C0D0E0F]
test_vor_99_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFF83, 0405067F, FFFFFF7F, 0C0D0E8F]
test_vor_100_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_101_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
test_vor_102_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
test_vor_103_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [000DFFFF, FFFF000D, 000D000D, FFFF000D]
test_vor_104_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [000D020F, 040D060F, 080D0A0F, 0C0D0E0F]
test_vor_105_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [001D223F, 445D667F, 889DAABF, CCDDEEFF]
test_vor_106_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [00FFFF0D, 000DFF0D, FF0D00FF, FFFF00FF]
test_vor_107_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [040D040D, 040D040D, 040D040D, 040D040D]
test_vor_108_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [070F070F, 070F070F, 070F070F, 070F070F]
test_vor_109_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [080D080D, 080D080D, 080D080D, 080D080D]
test_vor_110_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [121F121F, 121F121F, 121F121F, 121F121F]
test_vor_111_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [123D567D, 876D432D, 112F334D, 556F778D]
test_vor_112_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [3F8D000D, 3FCD000D, 3F8DCCCD, 3FFF333F]
test_vor_113_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [412D000D, C12D000D, 417D000D, C17D000D]
test_vor_114_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7F8D020F, 040D060F, 7F8D0A0F, 0C0D0E0F]
test_vor_115_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [800D101D, 808F000D, 7FFFFFFF, 8FFFFFFF]
test_vor_116_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [BF8D000D, BFCD000D, BF8DCCCD, BFFF333F]
test_vor_117_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [C12D000D, 41AD000D, C1AD000D, 41FD000D]
test_vor_118_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 040D020F]
test_vor_119_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [F8FDFAFF, FCFDFEFF, 000D020F, 040D060F]
test_vor_120_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FEFFFEFF, FEFFFEFF, FEFFFEFF, FEFFFEFF]
test_vor_121_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFDFFFD, FFFFFFFF, 000D000D, 000F000F]
test_vor_122_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFDFF7F, 000F008D, FFFDFF7D, 000F008F]
test_vor_123_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFF010D, 707DFFFF, FFFFFFFF, 000D000D]
test_vor_124_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFF8D, 000D007F, FFFFFF7F, 000D008D]
test_vor_125_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_126_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
test_vor_127_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
test_vor_128_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [0011FFFF, FFFF6677, 8899AABB, FFFFEEFF]
test_vor_129_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
test_vor_130_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [001D223F, 445D667F, 889DAABF, CCDDEEFF]
test_vor_131_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [00FFFF33, 4455FF77, FF99AAFF, FFFFEEFF]
test_vor_132_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [04152637, 44556677, 8C9DAEBF, CCDDEEFF]
test_vor_133_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [07172737, 47576777, 8F9FAFBF, CFDFEFFF]
test_vor_134_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [08192A3B, 4C5D6E7F, 8899AABB, CCDDEEFF]
test_vor_135_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [12133233, 56577677, 9A9BBABB, DEDFFEFF]
test_vor_136_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [1235767B, C7756777, 99BBBBFF, DDFFFFFF]
test_vor_137_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [3F912233, 7FD56677, BF9DEEFF, FFFFFFFF]
test_vor_138_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [41312233, C5756677, C9F9AABB, CDFDEEFF]
test_vor_139_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7F912233, 44556677, FF99AABB, CCDDEEFF]
test_vor_140_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [80193233, C4DF6677, FFFFFFFF, CFFFFFFF]
test_vor_141_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [BF912233, FFD56677, BF9DEEFF, FFFFFFFF]
test_vor_142_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [C1312233, 45F56677, C9B9AABB, CDFDEEFF]
test_vor_143_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [CDDDEFFF, CDDDEFFF, CDDDEFFF, CCDDEEFF]
test_vor_144_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 8899AABB, CCDDEEFF]
test_vor_145_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FEFFFEFF, FEFFFEFF, FEFFFEFF, FEFFFEFF]
test_vor_146_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFDFFFF, FFFFFFFF, 8899AABB, CCDFEEFF]
test_vor_147_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFDFF7F, 445766F7, FFFDFFFF, CCDFEEFF]
test_vor_148_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFF2333, 7475FFFF, FFFFFFFF, CCDDEEFF]
test_vor_149_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFFB3, 4455667F, FFFFFFFF, CCDDEEFF]
test_vor_150_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_151_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
test_vor_152_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [00FFFF01, 0000FF01, FF0000FF, FFFF00FF]
test_vor_153_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [00FFFFFF, FFFFFF00, FF0000FF, FFFF00FF]
test_vor_154_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00FFFF03, 0405FF07, FF090AFF, FFFF0EFF]
test_vor_155_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [00FFFF0D, 000DFF0D, FF0D00FF, FFFF00FF]
test_vor_156_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [00FFFF33, 4455FF77, FF99AAFF, FFFFEEFF]
test_vor_157_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [04FFFF04, 0404FF04, FF0404FF, FFFF04FF]
test_vor_158_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [07FFFF07, 0707FF07, FF0707FF, FFFF07FF]
test_vor_159_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [08FFFF08, 0808FF08, FF0808FF, FFFF08FF]
test_vor_160_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [12FFFF12, 1212FF12, FF1212FF, FFFF12FF]
test_vor_161_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [12FFFF78, 8765FF21, FF2233FF, FFFF77FF]
test_vor_162_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [3FFFFF00, 3FC0FF00, FF8CCCFF, FFFF33FF]
test_vor_163_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [41FFFF00, C120FF00, FF7000FF, FFFF00FF]
test_vor_164_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7FFFFF03, 0405FF07, FF800AFF, FFFF0EFF]
test_vor_165_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [80FFFF10, 808FFF00, FFFFFFFF, FFFFFFFF]
test_vor_166_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [BFFFFF00, BFC0FF00, FF8CCCFF, FFFF33FF]
test_vor_167_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [C1FFFF00, 41A0FF00, FFA000FF, FFFF00FF]
test_vor_168_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [CDFFFFCD, CDCDFFCD, FFCDCDFF, FFFF02FF]
test_vor_169_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [F8FFFFFB, FCFDFFFF, FF0102FF, FFFF06FF]
test_vor_170_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FEFFFFFE, FEFEFFFE, FFFEFEFF, FFFFFEFF]
test_vor_171_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFFFFFD, FFFEFFFF, FF0000FF, FFFF00FF]
test_vor_172_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFFFF7E, 0002FF81, FFFCFFFF, FFFF00FF]
test_vor_173_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFFFF01, 7070FFFF, FFFFFFFF, FFFF00FF]
test_vor_174_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFF80, 0000FF7F, FFFEFFFF, FFFF00FF]
test_vor_175_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_176_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
test_vor_177_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [04040405, 04040405, 04040405, 04040405]
test_vor_178_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [0404FFFF, FFFF0404, 04040404, FFFF0404]
test_vor_179_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [04050607, 04050607, 0C0D0E0F, 0C0D0E0F]
test_vor_180_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [040D040D, 040D040D, 040D040D, 040D040D]
test_vor_181_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [04152637, 44556677, 8C9DAEBF, CCDDEEFF]
test_vor_182_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [04FFFF04, 0404FF04, FF0404FF, FFFF04FF]
test_vor_183_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707]
test_vor_184_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [0C0C0C0C, 0C0C0C0C, 0C0C0C0C, 0C0C0C0C]
test_vor_185_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [16161616, 16161616, 16161616, 16161616]
test_vor_186_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [1634567C, 87654725, 15263744, 5566778C]
test_vor_187_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [3F840404, 3FC40404, 3F8CCCCD, 3FF73737]
test_vor_188_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [45240404, C5240404, 45740404, C5740404]
test_vor_189_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7F840607, 04050607, 7F840E0F, 0C0D0E0F]
test_vor_190_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [840C1414, 848F0404, 7FFFFFFF, 8FFFFFFF]
test_vor_191_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [BF840404, BFC40404, BF8CCCCD, BFF73737]
test_vor_192_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [C5240404, 45A40404, C5A40404, 45F40404]
test_vor_193_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04050607]
test_vor_194_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FCFDFEFF, FCFDFEFF, 04050607, 04050607]
test_vor_195_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
test_vor_196_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 04040405, 04060407]
test_vor_197_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFDFF7E, 04060485, FFFCFF7D, 04070486]
test_vor_198_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFF0505, 7474FFFF, FFFFFFFF, 04040404]
test_vor_199_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFF84, 0404047F, FFFEFF7F, 04050484]
test_vor_200_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_201_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707]
test_vor_202_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707]
test_vor_203_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [0707FFFF, FFFF0707, 07070707, FFFF0707]
test_vor_204_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [07070707, 07070707, 0F0F0F0F, 0F0F0F0F]
test_vor_205_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [070F070F, 070F070F, 070F070F, 070F070F]
test_vor_206_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [07172737, 47576777, 8F9FAFBF, CFDFEFFF]
test_vor_207_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [07FFFF07, 0707FF07, FF0707FF, FFFF07FF]
test_vor_208_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707]
test_vor_209_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [0F0F0F0F, 0F0F0F0F, 0F0F0F0F, 0F0F0F0F]
test_vor_210_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [17171717, 17171717, 17171717, 17171717]
test_vor_211_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [1737577F, 87674727, 17273747, 5767778F]
test_vor_212_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [3F870707, 3FC70707, 3F8FCFCF, 3FF73737]
test_vor_213_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [47270707, C7270707, 47770707, C7770707]
test_vor_214_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7F870707, 07070707, 7F870F0F, 0F0F0F0F]
test_vor_215_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [870F1717, 878F0707, 7FFFFFFF, 8FFFFFFF]
test_vor_216_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [BF870707, BFC70707, BF8FCFCF, BFF73737]
test_vor_217_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [C7270707, 47A70707, C7A70707, 47F70707]
test_vor_218_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [CFCFCFCF, CFCFCFCF, CFCFCFCF, 07070707]
test_vor_219_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, 07070707, 07070707]
test_vor_220_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_221_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, 07070707, 07070707]
test_vor_222_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFFFF7F, 07070787, FFFFFF7F, 07070787]
test_vor_223_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFF0707, 7777FFFF, FFFFFFFF, 07070707]
test_vor_224_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFF87, 0707077F, FFFFFF7F, 07070787]
test_vor_225_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_226_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
test_vor_227_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [08080809, 08080809, 08080809, 08080809]
test_vor_228_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [0808FFFF, FFFF0808, 08080808, FFFF0808]
test_vor_229_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [08090A0B, 0C0D0E0F, 08090A0B, 0C0D0E0F]
test_vor_230_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [080D080D, 080D080D, 080D080D, 080D080D]
test_vor_231_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [08192A3B, 4C5D6E7F, 8899AABB, CCDDEEFF]
test_vor_232_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [08FFFF08, 0808FF08, FF0808FF, FFFF08FF]
test_vor_233_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [0C0C0C0C, 0C0C0C0C, 0C0C0C0C, 0C0C0C0C]
test_vor_234_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [0F0F0F0F, 0F0F0F0F, 0F0F0F0F, 0F0F0F0F]
test_vor_235_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [1A1A1A1A, 1A1A1A1A, 1A1A1A1A, 1A1A1A1A]
test_vor_236_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [1A3C5E78, 8F6D4B29, 192A3B4C, 5D6E7F88]
test_vor_237_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [3F880808, 3FC80808, 3F8CCCCD, 3FFB3B3B]
test_vor_238_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [49280808, C9280808, 49780808, C9780808]
test_vor_239_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7F880A0B, 0C0D0E0F, 7F880A0B, 0C0D0E0F]
test_vor_240_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [88081818, 888F0808, 7FFFFFFF, 8FFFFFFF]
test_vor_241_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [BF880808, BFC80808, BF8CCCCD, BFFB3B3B]
test_vor_242_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [C9280808, 49A80808, C9A80808, 49F80808]
test_vor_243_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 0C090A0B]
test_vor_244_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 08090A0B, 0C0D0E0F]
test_vor_245_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
test_vor_246_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 08080809, 080A080B]
test_vor_247_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFDFF7E, 080A0889, FFFCFF7D, 080B088A]
test_vor_248_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFF0909, 7878FFFF, FFFFFFFF, 08080808]
test_vor_249_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFF88, 0808087F, FFFEFF7F, 08090888]
test_vor_250_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_251_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212]
test_vor_252_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [12121213, 12121213, 12121213, 12121213]
test_vor_253_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [1212FFFF, FFFF1212, 12121212, FFFF1212]
test_vor_254_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [12131213, 16171617, 1A1B1A1B, 1E1F1E1F]
test_vor_255_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [121F121F, 121F121F, 121F121F, 121F121F]
test_vor_256_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [12133233, 56577677, 9A9BBABB, DEDFFEFF]
test_vor_257_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [12FFFF12, 1212FF12, FF1212FF, FFFF12FF]
test_vor_258_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [16161616, 16161616, 16161616, 16161616]
test_vor_259_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [17171717, 17171717, 17171717, 17171717]
test_vor_260_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [1A1A1A1A, 1A1A1A1A, 1A1A1A1A, 1A1A1A1A]
test_vor_261_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [1236567A, 97775333, 13323356, 5776779A]
test_vor_262_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [3F921212, 3FD21212, 3F9EDEDF, 3FF33333]
test_vor_263_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [53321212, D3321212, 53721212, D3721212]
test_vor_264_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7F921213, 16171617, 7F921A1B, 1E1F1E1F]
test_vor_265_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [921A1212, 929F1212, 7FFFFFFF, 9FFFFFFF]
test_vor_266_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [BF921212, BFD21212, BF9EDEDF, BFF33333]
test_vor_267_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [D3321212, 53B21212, D3B21212, 53F21212]
test_vor_268_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [DFDFDFDF, DFDFDFDF, DFDFDFDF, 16131213]
test_vor_269_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FAFBFAFB, FEFFFEFF, 12131213, 16171617]
test_vor_270_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
test_vor_271_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFEFFFF, FFFEFFFF, 12121213, 12121213]
test_vor_272_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFFFF7E, 12121293, FFFEFF7F, 12131292]
test_vor_273_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFF1313, 7272FFFF, FFFFFFFF, 12121212]
test_vor_274_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFF92, 1212127F, FFFEFF7F, 12131292]
test_vor_275_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_276_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788]
test_vor_277_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [12345679, 87654321, 11223345, 55667789]
test_vor_278_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [1234FFFF, FFFF4321, 11223344, FFFF7788]
test_vor_279_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [1235567B, 87654727, 192B3B4F, 5D6F7F8F]
test_vor_280_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [123D567D, 876D432D, 112F334D, 556F778D]
test_vor_281_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [1235767B, C7756777, 99BBBBFF, DDFFFFFF]
test_vor_282_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [12FFFF78, 8765FF21, FF2233FF, FFFF77FF]
test_vor_283_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [1634567C, 87654725, 15263744, 5566778C]
test_vor_284_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [1737577F, 87674727, 17273747, 5767778F]
test_vor_285_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [1A3C5E78, 8F6D4B29, 192A3B4C, 5D6E7F88]
test_vor_286_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [1236567A, 97775333, 13323356, 5776779A]
test_vor_287_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [3FB45678, BFE54321, 3FAEFFCD, 7FF777BB]
test_vor_288_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [53345678, C7654321, 51723344, D5767788]
test_vor_289_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7FB4567B, 87654727, 7FA23B4F, 5D6F7F8F]
test_vor_290_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [923C5678, 87EF4321, 7FFFFFFF, DFFFFFFF]
test_vor_291_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [BFB45678, BFE54321, BFAEFFCD, FFF777BB]
test_vor_292_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [D3345678, C7E54321, D1A23344, 55F67788]
test_vor_293_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [DFFDDFFD, CFEDCFED, DDEFFFCD, 5567778B]
test_vor_294_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FAFDFEFB, FFFDFFFF, 11233347, 5567778F]
test_vor_295_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FEFEFEFE, FFFFFFFF, FFFEFFFE, FFFEFFFE]
test_vor_296_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFFFFFF, 11223345, 5566778B]
test_vor_297_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFDFF7E, 876743A1, FFFEFF7D, 5567778A]
test_vor_298_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFF5779, F775FFFF, FFFFFFFF, 55667788]
test_vor_299_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFFF8, 8765437F, FFFEFF7F, 55677788]
test_vor_300_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_301_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
test_vor_302_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [3F800001, 3FC00001, 3F8CCCCD, 3FF33333]
test_vor_303_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [3F80FFFF, FFFF0000, 3F8CCCCD, FFFF3333]
test_vor_304_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [3F810203, 3FC50607, 3F8DCECF, 3FFF3F3F]
test_vor_305_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [3F8D000D, 3FCD000D, 3F8DCCCD, 3FFF333F]
test_vor_306_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [3F912233, 7FD56677, BF9DEEFF, FFFFFFFF]
test_vor_307_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [3FFFFF00, 3FC0FF00, FF8CCCFF, FFFF33FF]
test_vor_308_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [3F840404, 3FC40404, 3F8CCCCD, 3FF73737]
test_vor_309_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [3F870707, 3FC70707, 3F8FCFCF, 3FF73737]
test_vor_310_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [3F880808, 3FC80808, 3F8CCCCD, 3FFB3B3B]
test_vor_311_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [3F921212, 3FD21212, 3F9EDEDF, 3FF33333]
test_vor_312_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [3FB45678, BFE54321, 3FAEFFCD, 7FF777BB]
test_vor_313_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [7FA00000, FFE00000, 7FFCCCCD, FFF33333]
test_vor_314_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7F800203, 3FC50607, 7F8CCECF, 3FFF3F3F]
test_vor_315_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [BF881010, BFCF0000, 7FFFFFFF, BFFFFFFF]
test_vor_316_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333]
test_vor_317_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [FFA00000, 7FE00000, FFACCCCD, 7FF33333]
test_vor_318_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [FFCDCDCD, FFCDCDCD, FFCDCDCD, 3FF33333]
test_vor_319_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFF9FAFB, FFFDFEFF, 3F8DCECF, 3FF73737]
test_vor_320_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FFFEFEFE, FFFEFEFE, FFFEFEFF, FFFFFFFF]
test_vor_321_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 3F8CCCCD, 3FF33333]
test_vor_322_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFDFF7E, 3FC20081, FFFCFFFD, 3FF333B3]
test_vor_323_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFF0101, 7FF0FFFF, FFFFFFFF, 3FF33333]
test_vor_324_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFF80, 3FC0007F, FFFEFFFF, 3FF333B3]
test_vor_325_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_326_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
test_vor_327_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [41200001, C1200001, 41700001, C1700001]
test_vor_328_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [4120FFFF, FFFF0000, 41700000, FFFF0000]
test_vor_329_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [41210203, C5250607, 49790A0B, CD7D0E0F]
test_vor_330_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [412D000D, C12D000D, 417D000D, C17D000D]
test_vor_331_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [41312233, C5756677, C9F9AABB, CDFDEEFF]
test_vor_332_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [41FFFF00, C120FF00, FF7000FF, FFFF00FF]
test_vor_333_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [45240404, C5240404, 45740404, C5740404]
test_vor_334_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [47270707, C7270707, 47770707, C7770707]
test_vor_335_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [49280808, C9280808, 49780808, C9780808]
test_vor_336_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [53321212, D3321212, 53721212, D3721212]
test_vor_337_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [53345678, C7654321, 51723344, D5767788]
test_vor_338_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [7FA00000, FFE00000, 7FFCCCCD, FFF33333]
test_vor_339_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7FA00203, C5250607, 7FF00A0B, CD7D0E0F]
test_vor_340_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [C1281010, C1AF0000, 7FFFFFFF, CFFFFFFF]
test_vor_341_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [FFA00000, FFE00000, FFFCCCCD, FFF33333]
test_vor_342_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [C1200000, C1A00000, C1F00000, C1F00000]
test_vor_343_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [CDEDCDCD, CDEDCDCD, CDFDCDCD, C5710203]
test_vor_344_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [F9F9FAFB, FDFDFEFF, 41710203, C5750607]
test_vor_345_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FFFEFEFE, FFFEFEFE, FFFEFEFE, FFFEFEFE]
test_vor_346_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 41700001, C1720003]
test_vor_347_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFDFF7E, C1220081, FFFCFF7D, C1730082]
test_vor_348_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFF0101, F170FFFF, FFFFFFFF, C1700000]
test_vor_349_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFF80, C120007F, FFFEFF7F, C1710080]
test_vor_350_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_351_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
test_vor_352_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
test_vor_353_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [7F80FFFF, FFFF0607, 7F800A0B, FFFF0E0F]
test_vor_354_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7F810203, 04050607, 7F890A0B, 0C0D0E0F]
test_vor_355_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [7F8D020F, 040D060F, 7F8D0A0F, 0C0D0E0F]
test_vor_356_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [7F912233, 44556677, FF99AABB, CCDDEEFF]
test_vor_357_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [7FFFFF03, 0405FF07, FF800AFF, FFFF0EFF]
test_vor_358_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [7F840607, 04050607, 7F840E0F, 0C0D0E0F]
test_vor_359_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [7F870707, 07070707, 7F870F0F, 0F0F0F0F]
test_vor_360_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [7F880A0B, 0C0D0E0F, 7F880A0B, 0C0D0E0F]
test_vor_361_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [7F921213, 16171617, 7F921A1B, 1E1F1E1F]
test_vor_362_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [7FB4567B, 87654727, 7FA23B4F, 5D6F7F8F]
test_vor_363_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [7F800203, 3FC50607, 7F8CCECF, 3FFF3F3F]
test_vor_364_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [7FA00203, C5250607, 7FF00A0B, CD7D0E0F]
test_vor_365_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FF881213, 848F0607, 7FFFFFFF, 8FFFFFFF]
test_vor_366_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [FF800203, BFC50607, FF8CCECF, BFFF3F3F]
test_vor_367_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [FFA00203, 45A50607, FFA00A0B, 4DFD0E0F]
test_vor_368_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [FFCDCFCF, CDCDCFCF, FFCDCFCF, 0C0D0E0F]
test_vor_369_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFF9FAFB, FCFDFEFF, 7F810A0B, 0C0D0E0F]
test_vor_370_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FFFEFEFF, FEFFFEFF, FFFEFEFF, FEFFFEFF]
test_vor_371_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFCFFFF, FFFFFFFF, 7F800A0B, 0C0F0E0F]
test_vor_372_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFDFF7F, 04070687, FFFCFF7F, 0C0F0E8F]
test_vor_373_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFF0303, 7475FFFF, FFFFFFFF, 0C0D0E0F]
test_vor_374_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFF83, 0405067F, FFFEFF7F, 0C0D0E8F]
test_vor_375_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_376_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
test_vor_377_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [80081011, 808F0001, 7FFFFFFF, 8FFFFFFF]
test_vor_378_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [8008FFFF, FFFF0000, 7FFFFFFF, FFFFFFFF]
test_vor_379_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [80091213, 848F0607, 7FFFFFFF, 8FFFFFFF]
test_vor_380_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [800D101D, 808F000D, 7FFFFFFF, 8FFFFFFF]
test_vor_381_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [80193233, C4DF6677, FFFFFFFF, CFFFFFFF]
test_vor_382_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [80FFFF10, 808FFF00, FFFFFFFF, FFFFFFFF]
test_vor_383_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [840C1414, 848F0404, 7FFFFFFF, 8FFFFFFF]
test_vor_384_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [870F1717, 878F0707, 7FFFFFFF, 8FFFFFFF]
test_vor_385_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [88081818, 888F0808, 7FFFFFFF, 8FFFFFFF]
test_vor_386_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [921A1212, 929F1212, 7FFFFFFF, 9FFFFFFF]
test_vor_387_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [923C5678, 87EF4321, 7FFFFFFF, DFFFFFFF]
test_vor_388_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [BF881010, BFCF0000, 7FFFFFFF, BFFFFFFF]
test_vor_389_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [C1281010, C1AF0000, 7FFFFFFF, CFFFFFFF]
test_vor_390_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FF881213, 848F0607, 7FFFFFFF, 8FFFFFFF]
test_vor_391_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [BF881010, BFCF0000, FFFFFFFF, BFFFFFFF]
test_vor_392_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [C1281010, C1AF0000, FFFFFFFF, CFFFFFFF]
test_vor_393_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [CDCDDDDD, CDCFCDCD, FFFFFFFF, 8FFFFFFF]
test_vor_394_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [F8F9FAFB, FCFFFEFF, 7FFFFFFF, 8FFFFFFF]
test_vor_395_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FEFEFEFE, FEFFFEFE, FFFFFFFF, FFFFFFFF]
test_vor_396_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFFFFFF, 7FFFFFFF, 8FFFFFFF]
test_vor_397_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFDFF7E, 808F0081, FFFFFFFF, 8FFFFFFF]
test_vor_398_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFF1111, F0FFFFFF, FFFFFFFF, 8FFFFFFF]
test_vor_399_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFF90, 808F007F, FFFFFFFF, 8FFFFFFF]
test_vor_400_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_401_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333]
test_vor_402_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [BF800001, BFC00001, BF8CCCCD, BFF33333]
test_vor_403_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [BF80FFFF, FFFF0000, BF8CCCCD, FFFF3333]
test_vor_404_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [BF810203, BFC50607, BF8DCECF, BFFF3F3F]
test_vor_405_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [BF8D000D, BFCD000D, BF8DCCCD, BFFF333F]
test_vor_406_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [BF912233, FFD56677, BF9DEEFF, FFFFFFFF]
test_vor_407_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [BFFFFF00, BFC0FF00, FF8CCCFF, FFFF33FF]
test_vor_408_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [BF840404, BFC40404, BF8CCCCD, BFF73737]
test_vor_409_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [BF870707, BFC70707, BF8FCFCF, BFF73737]
test_vor_410_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [BF880808, BFC80808, BF8CCCCD, BFFB3B3B]
test_vor_411_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [BF921212, BFD21212, BF9EDEDF, BFF33333]
test_vor_412_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [BFB45678, BFE54321, BFAEFFCD, FFF777BB]
test_vor_413_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333]
test_vor_414_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [FFA00000, FFE00000, FFFCCCCD, FFF33333]
test_vor_415_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FF800203, BFC50607, FF8CCECF, BFFF3F3F]
test_vor_416_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [BF881010, BFCF0000, FFFFFFFF, BFFFFFFF]
test_vor_417_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [FFA00000, FFE00000, FFACCCCD, FFF33333]
test_vor_418_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [FFCDCDCD, FFCDCDCD, FFCDCDCD, BFF33333]
test_vor_419_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFF9FAFB, FFFDFEFF, BF8DCECF, BFF73737]
test_vor_420_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FFFEFEFE, FFFEFEFE, FFFEFEFF, FFFFFFFF]
test_vor_421_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, BF8CCCCD, BFF33333]
test_vor_422_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFDFF7E, BFC20081, FFFCFFFD, BFF333B3]
test_vor_423_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFF0101, FFF0FFFF, FFFFFFFF, BFF33333]
test_vor_424_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFF80, BFC0007F, FFFEFFFF, BFF333B3]
test_vor_425_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_426_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000]
test_vor_427_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [C1200001, 41A00001, C1A00001, 41F00001]
test_vor_428_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [C120FFFF, FFFF0000, C1A00000, FFFF0000]
test_vor_429_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [C1210203, 45A50607, C9A90A0B, 4DFD0E0F]
test_vor_430_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [C12D000D, 41AD000D, C1AD000D, 41FD000D]
test_vor_431_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [C1312233, 45F56677, C9B9AABB, CDFDEEFF]
test_vor_432_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [C1FFFF00, 41A0FF00, FFA000FF, FFFF00FF]
test_vor_433_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [C5240404, 45A40404, C5A40404, 45F40404]
test_vor_434_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [C7270707, 47A70707, C7A70707, 47F70707]
test_vor_435_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [C9280808, 49A80808, C9A80808, 49F80808]
test_vor_436_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [D3321212, 53B21212, D3B21212, 53F21212]
test_vor_437_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [D3345678, C7E54321, D1A23344, 55F67788]
test_vor_438_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [FFA00000, 7FE00000, FFACCCCD, 7FF33333]
test_vor_439_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [C1200000, C1A00000, C1F00000, C1F00000]
test_vor_440_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFA00203, 45A50607, FFA00A0B, 4DFD0E0F]
test_vor_441_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [C1281010, C1AF0000, FFFFFFFF, CFFFFFFF]
test_vor_442_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [FFA00000, FFE00000, FFACCCCD, FFF33333]
test_vor_443_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [CDEDCDCD, CDEDCDCD, CDEDCDCD, 45F10203]
test_vor_444_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [F9F9FAFB, FDFDFEFF, C1A10203, 45F50607]
test_vor_445_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FFFEFEFE, FFFEFEFE, FFFEFEFE, FFFEFEFE]
test_vor_446_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, C1A00001, 41F20003]
test_vor_447_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFDFF7E, 41A20081, FFFCFF7D, 41F30082]
test_vor_448_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFF0101, 71F0FFFF, FFFFFFFF, 41F00000]
test_vor_449_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFF80, 41A0007F, FFFEFF7F, 41F10080]
test_vor_450_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_451_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
test_vor_452_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
test_vor_453_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [CDCDFFFF, FFFFCDCD, CDCDCDCD, FFFF0203]
test_vor_454_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [CDCDCFCF, CDCDCFCF, CDCDCFCF, 0C0D0E0F]
test_vor_455_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 040D020F]
test_vor_456_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [CDDDEFFF, CDDDEFFF, CDDDEFFF, CCDDEEFF]
test_vor_457_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [CDFFFFCD, CDCDFFCD, FFCDCDFF, FFFF02FF]
test_vor_458_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04050607]
test_vor_459_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [CFCFCFCF, CFCFCFCF, CFCFCFCF, 07070707]
test_vor_460_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 0C090A0B]
test_vor_461_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [DFDFDFDF, DFDFDFDF, DFDFDFDF, 16131213]
test_vor_462_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [DFFDDFFD, CFEDCFED, DDEFFFCD, 5567778B]
test_vor_463_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [FFCDCDCD, FFCDCDCD, FFCDCDCD, 3FF33333]
test_vor_464_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [CDEDCDCD, CDEDCDCD, CDFDCDCD, C5710203]
test_vor_465_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFCDCFCF, CDCDCFCF, FFCDCFCF, 0C0D0E0F]
test_vor_466_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [CDCDDDDD, CDCFCDCD, FFFFFFFF, 8FFFFFFF]
test_vor_467_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [FFCDCDCD, FFCDCDCD, FFCDCDCD, BFF33333]
test_vor_468_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [CDEDCDCD, CDEDCDCD, CDEDCDCD, 45F10203]
test_vor_469_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FDFDFFFF, FDFDFFFF, CDCDCFCF, 04050607]
test_vor_470_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FEFFFEFF]
test_vor_471_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFDFFFD, FFFFFFFF, CDCDCDCD, 04030203]
test_vor_472_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFDFFFF, CDCFCDCD, FFFDFFFD, 04030283]
test_vor_473_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFFCDCD, FDFDFFFF, FFFFFFFF, 04010203]
test_vor_474_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFFCD, CDCDCDFF, FFFFFFFF, 04010283]
test_vor_475_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_476_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
test_vor_477_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
test_vor_478_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [F8F9FFFF, FFFFFEFF, 00010203, FFFF0607]
test_vor_479_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 08090A0B, 0C0D0E0F]
test_vor_480_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [F8FDFAFF, FCFDFEFF, 000D020F, 040D060F]
test_vor_481_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 8899AABB, CCDDEEFF]
test_vor_482_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [F8FFFFFB, FCFDFFFF, FF0102FF, FFFF06FF]
test_vor_483_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FCFDFEFF, FCFDFEFF, 04050607, 04050607]
test_vor_484_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, 07070707, 07070707]
test_vor_485_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 08090A0B, 0C0D0E0F]
test_vor_486_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [FAFBFAFB, FEFFFEFF, 12131213, 16171617]
test_vor_487_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [FAFDFEFB, FFFDFFFF, 11233347, 5567778F]
test_vor_488_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [FFF9FAFB, FFFDFEFF, 3F8DCECF, 3FF73737]
test_vor_489_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [F9F9FAFB, FDFDFEFF, 41710203, C5750607]
test_vor_490_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFF9FAFB, FCFDFEFF, 7F810A0B, 0C0D0E0F]
test_vor_491_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [F8F9FAFB, FCFFFEFF, 7FFFFFFF, 8FFFFFFF]
test_vor_492_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [FFF9FAFB, FFFDFEFF, BF8DCECF, BFF73737]
test_vor_493_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [F9F9FAFB, FDFDFEFF, C1A10203, 45F50607]
test_vor_494_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [FDFDFFFF, FDFDFFFF, CDCDCFCF, 04050607]
test_vor_495_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FEFFFEFF, FEFFFEFF, FEFFFEFF, FEFFFEFF]
test_vor_496_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFDFFFF, FFFFFFFF, 00010203, 04070607]
test_vor_497_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFDFFFF, FCFFFEFF, FFFDFF7F, 04070687]
test_vor_498_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFFFBFB, FCFDFFFF, FFFFFFFF, 04050607]
test_vor_499_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFFFB, FCFDFEFF, FFFFFF7F, 04050687]
test_vor_500_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_501_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
test_vor_502_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FEFEFEFF, FEFEFEFF, FEFEFEFF, FEFEFEFF]
test_vor_503_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FEFEFFFF, FFFFFEFE, FEFEFEFE, FFFFFEFE]
test_vor_504_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FEFFFEFF, FEFFFEFF, FEFFFEFF, FEFFFEFF]
test_vor_505_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FEFFFEFF, FEFFFEFF, FEFFFEFF, FEFFFEFF]
test_vor_506_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FEFFFEFF, FEFFFEFF, FEFFFEFF, FEFFFEFF]
test_vor_507_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FEFFFFFE, FEFEFFFE, FFFEFEFF, FFFFFEFF]
test_vor_508_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
test_vor_509_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_510_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
test_vor_511_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
test_vor_512_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [FEFEFEFE, FFFFFFFF, FFFEFFFE, FFFEFFFE]
test_vor_513_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [FFFEFEFE, FFFEFEFE, FFFEFEFF, FFFFFFFF]
test_vor_514_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [FFFEFEFE, FFFEFEFE, FFFEFEFE, FFFEFEFE]
test_vor_515_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFEFEFF, FEFFFEFF, FFFEFEFF, FEFFFEFF]
test_vor_516_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FEFEFEFE, FEFFFEFE, FFFFFFFF, FFFFFFFF]
test_vor_517_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [FFFEFEFE, FFFEFEFE, FFFEFEFF, FFFFFFFF]
test_vor_518_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [FFFEFEFE, FFFEFEFE, FFFEFEFE, FFFEFEFE]
test_vor_519_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FEFFFEFF]
test_vor_520_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FEFFFEFF, FEFFFEFF, FEFFFEFF, FEFFFEFF]
test_vor_521_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFEFFFF, FFFEFFFF, FEFEFEFF, FEFEFEFF]
test_vor_522_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFFFFFE, FEFEFEFF, FFFEFFFF, FEFFFEFE]
test_vor_523_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFFFFFF, FEFEFFFF, FFFFFFFF, FEFEFEFE]
test_vor_524_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFFFE, FEFEFEFF, FFFEFFFF, FEFFFEFE]
test_vor_525_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_526_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
test_vor_527_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
test_vor_528_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFCFFFF, FFFFFFFF, 00000001, FFFF0003]
test_vor_529_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFDFFFF, FFFFFFFF, 08090A0B, 0C0F0E0F]
test_vor_530_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFFDFFFD, FFFFFFFF, 000D000D, 000F000F]
test_vor_531_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFFDFFFF, FFFFFFFF, 8899AABB, CCDFEEFF]
test_vor_532_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FFFFFFFD, FFFEFFFF, FF0000FF, FFFF00FF]
test_vor_533_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 04040405, 04060407]
test_vor_534_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, 07070707, 07070707]
test_vor_535_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 08080809, 080A080B]
test_vor_536_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [FFFEFFFF, FFFEFFFF, 12121213, 12121213]
test_vor_537_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFFFFFF, 11223345, 5566778B]
test_vor_538_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 3F8CCCCD, 3FF33333]
test_vor_539_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 41700001, C1720003]
test_vor_540_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFCFFFF, FFFFFFFF, 7F800A0B, 0C0F0E0F]
test_vor_541_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFFFFFF, 7FFFFFFF, 8FFFFFFF]
test_vor_542_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, BF8CCCCD, BFF33333]
test_vor_543_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, C1A00001, 41F20003]
test_vor_544_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [FFFDFFFD, FFFFFFFF, CDCDCDCD, 04030203]
test_vor_545_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFFDFFFF, FFFFFFFF, 00010203, 04070607]
test_vor_546_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FFFEFFFF, FFFEFFFF, FEFEFEFF, FEFEFEFF]
test_vor_547_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFDFFFF, FFFEFFFF, FFFCFF7D, 00030083]
test_vor_548_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFFFFFD, FFFEFFFF, FFFFFFFF, 00020003]
test_vor_549_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFFFD, FFFEFFFF, FFFEFF7F, 00030083]
test_vor_550_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_551_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
test_vor_552_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFDFF7F, 00020081, FFFCFF7D, 00030083]
test_vor_553_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFDFFFF, FFFF0081, FFFCFF7D, FFFF0082]
test_vor_554_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFDFF7F, 04070687, FFFDFF7F, 0C0F0E8F]
test_vor_555_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFFDFF7F, 000F008D, FFFDFF7D, 000F008F]
test_vor_556_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFFDFF7F, 445766F7, FFFDFFFF, CCDFEEFF]
test_vor_557_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FFFFFF7E, 0002FF81, FFFCFFFF, FFFF00FF]
test_vor_558_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FFFDFF7E, 04060485, FFFCFF7D, 04070486]
test_vor_559_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [FFFFFF7F, 07070787, FFFFFF7F, 07070787]
test_vor_560_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FFFDFF7E, 080A0889, FFFCFF7D, 080B088A]
test_vor_561_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [FFFFFF7E, 12121293, FFFEFF7F, 12131292]
test_vor_562_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [FFFDFF7E, 876743A1, FFFEFF7D, 5567778A]
test_vor_563_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [FFFDFF7E, 3FC20081, FFFCFFFD, 3FF333B3]
test_vor_564_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [FFFDFF7E, C1220081, FFFCFF7D, C1730082]
test_vor_565_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFDFF7F, 04070687, FFFCFF7F, 0C0F0E8F]
test_vor_566_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FFFDFF7E, 808F0081, FFFFFFFF, 8FFFFFFF]
test_vor_567_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [FFFDFF7E, BFC20081, FFFCFFFD, BFF333B3]
test_vor_568_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [FFFDFF7E, 41A20081, FFFCFF7D, 41F30082]
test_vor_569_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [FFFDFFFF, CDCFCDCD, FFFDFFFD, 04030283]
test_vor_570_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFFDFFFF, FCFFFEFF, FFFDFF7F, 04070687]
test_vor_571_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FFFFFFFE, FEFEFEFF, FFFEFFFF, FEFFFEFE]
test_vor_572_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFDFFFF, FFFEFFFF, FFFCFF7D, 00030083]
test_vor_573_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFFFF7F, 7072FFFF, FFFFFFFF, 00030082]
test_vor_574_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFFFE, 000200FF, FFFEFF7F, 00030082]
test_vor_575_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_576_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
test_vor_577_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000001]
test_vor_578_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFF0000]
test_vor_579_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFF0303, 7475FFFF, FFFFFFFF, 0C0D0E0F]
test_vor_580_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFFF010D, 707DFFFF, FFFFFFFF, 000D000D]
test_vor_581_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFFF2333, 7475FFFF, FFFFFFFF, CCDDEEFF]
test_vor_582_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FFFFFF01, 7070FFFF, FFFFFFFF, FFFF00FF]
test_vor_583_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FFFF0505, 7474FFFF, FFFFFFFF, 04040404]
test_vor_584_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [FFFF0707, 7777FFFF, FFFFFFFF, 07070707]
test_vor_585_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FFFF0909, 7878FFFF, FFFFFFFF, 08080808]
test_vor_586_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [FFFF1313, 7272FFFF, FFFFFFFF, 12121212]
test_vor_587_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [FFFF5779, F775FFFF, FFFFFFFF, 55667788]
test_vor_588_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [FFFF0101, 7FF0FFFF, FFFFFFFF, 3FF33333]
test_vor_589_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [FFFF0101, F170FFFF, FFFFFFFF, C1700000]
test_vor_590_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFF0303, 7475FFFF, FFFFFFFF, 0C0D0E0F]
test_vor_591_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FFFF1111, F0FFFFFF, FFFFFFFF, 8FFFFFFF]
test_vor_592_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [FFFF0101, FFF0FFFF, FFFFFFFF, BFF33333]
test_vor_593_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [FFFF0101, 71F0FFFF, FFFFFFFF, 41F00000]
test_vor_594_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [FFFFCDCD, FDFDFFFF, FFFFFFFF, 04010203]
test_vor_595_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFFFFBFB, FCFDFFFF, FFFFFFFF, 04050607]
test_vor_596_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FFFFFFFF, FEFEFFFF, FFFFFFFF, FEFEFEFE]
test_vor_597_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFFFFFD, FFFEFFFF, FFFFFFFF, 00020003]
test_vor_598_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFFFF7F, 7072FFFF, FFFFFFFF, 00030082]
test_vor_599_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFF81, 7070FFFF, FFFFFFFF, 00010080]
test_vor_600_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_601_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
test_vor_602_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFFFF81, 0000007F, FFFEFF7F, 00010081]
test_vor_603_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFF007F, FFFEFF7F, FFFF0080]
test_vor_604_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFFFF83, 0405067F, FFFFFF7F, 0C0D0E8F]
test_vor_605_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFFFFF8D, 000D007F, FFFFFF7F, 000D008D]
test_vor_606_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFFFFFB3, 4455667F, FFFFFFFF, CCDDEEFF]
test_vor_607_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FFFFFF80, 0000FF7F, FFFEFFFF, FFFF00FF]
test_vor_608_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FFFFFF84, 0404047F, FFFEFF7F, 04050484]
test_vor_609_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [FFFFFF87, 0707077F, FFFFFF7F, 07070787]
test_vor_610_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FFFFFF88, 0808087F, FFFEFF7F, 08090888]
test_vor_611_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [FFFFFF92, 1212127F, FFFEFF7F, 12131292]
test_vor_612_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [FFFFFFF8, 8765437F, FFFEFF7F, 55677788]
test_vor_613_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [FFFFFF80, 3FC0007F, FFFEFFFF, 3FF333B3]
test_vor_614_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [FFFFFF80, C120007F, FFFEFF7F, C1710080]
test_vor_615_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFFFF83, 0405067F, FFFEFF7F, 0C0D0E8F]
test_vor_616_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FFFFFF90, 808F007F, FFFFFFFF, 8FFFFFFF]
test_vor_617_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [FFFFFF80, BFC0007F, FFFEFFFF, BFF333B3]
test_vor_618_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [FFFFFF80, 41A0007F, FFFEFF7F, 41F10080]
test_vor_619_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [FFFFFFCD, CDCDCDFF, FFFFFFFF, 04010283]
test_vor_620_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFFFFFFB, FCFDFEFF, FFFFFF7F, 04050687]
test_vor_621_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FFFFFFFE, FEFEFEFF, FFFEFFFF, FEFFFEFE]
test_vor_622_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFFFFFD, FFFEFFFF, FFFEFF7F, 00030083]
test_vor_623_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFFFFFE, 000200FF, FFFEFF7F, 00030082]
test_vor_624_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFFFF81, 7070FFFF, FFFFFFFF, 00010080]
test_vor_625_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_626_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_627_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_628_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_629_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_630_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_631_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_632_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_633_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_634_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_635_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_636_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_637_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_638_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_639_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_640_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_641_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_642_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_643_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_644_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_645_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_646_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_647_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_648_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_649_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vor_650_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vor v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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