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Xenia-Canary/src/xenia/cpu/ppc/testing/instr__gen_vsl.s
Dr. Chat 54582cc823 Generated tests from Rick
2019-04-04 18:13:11 -05:00

5851 lines
222 KiB
ArmAsm
Raw Blame History

test_vsl_1_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_2_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_3_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_4_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_5_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_6_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_7_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_8_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_9_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_10_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_11_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_12_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_13_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_14_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_15_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_16_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_17_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_18_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_19_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_20_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_21_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_22_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_23_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_24_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_25_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
test_vsl_26_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
test_vsl_27_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [00000080, 00000001, 00000001, 00000001]
test_vsl_28_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00000008, 00000080, 00000008, 00000080]
test_vsl_29_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [00000020, 00000020, 00000020, 00000020]
test_vsl_30_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [00000008, 00000080, 00000008, 00000080]
test_vsl_31_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [00000001, 00000001, 00000080, 00000080]
test_vsl_32_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [00000010, 00000010, 00000010, 00000010]
test_vsl_33_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [00000080, 00000080, 00000080, 00000080]
test_vsl_34_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
test_vsl_35_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [00000004, 00000004, 00000004, 00000004]
test_vsl_36_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [00000001, 00000002, 00000010, 00000001]
test_vsl_37_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [00000001, 00000001, 00000020, 00000008]
test_vsl_38_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
test_vsl_39_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00000008, 00000080, 00000008, 00000080]
test_vsl_40_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [00000001, 00000001, 00000080, 00000080]
test_vsl_41_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [00000001, 00000001, 00000020, 00000008]
test_vsl_42_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
test_vsl_43_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [00000020, 00000020, 00000020, 00000008]
test_vsl_44_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [00000008, 00000080, 00000008, 00000080]
test_vsl_45_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [00000040, 00000040, 00000040, 00000040]
test_vsl_46_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00000020, 00000080, 00000002, 00000008]
test_vsl_47_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00000040, 00000002, 00000020, 00000004]
test_vsl_48_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [00000002, 00000080, 00000080, 00000001]
test_vsl_49_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [00000001, 00000080, 00000080, 00000001]
test_vsl_50_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00000080, 00000080, 00000080, 00000080]
test_vsl_51_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
test_vsl_52_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000001, FFFF0000]
test_vsl_53_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [0001FFFF, FFE00000, 00000007, FFE00000]
test_vsl_54_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [001FFFFF, FFE00000, 0000001F, FFE00000]
test_vsl_55_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [0001FFFF, FFE00000, 00000007, FFE00000]
test_vsl_56_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [007FFFFF, FFFF0000, 0000007F, FF800000]
test_vsl_57_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [000FFFFF, FFF00000, 0000000F, FFF00000]
test_vsl_58_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [007FFFFF, FF800000, 0000007F, FF800000]
test_vsl_59_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
test_vsl_60_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [0003FFFF, FFFC0000, 00000003, FFFC0000]
test_vsl_61_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [000FFFFF, FFE00000, 0000000F, FFC00000]
test_vsl_62_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 0000001F, FFF80000]
test_vsl_63_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
test_vsl_64_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [0000FFFF, FFE00000, 00000007, FFE00000]
test_vsl_65_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [0000FFFF, FF800000, 0000007F, FF800000]
test_vsl_66_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 0000001F, FFF80000]
test_vsl_67_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
test_vsl_68_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [001FFFFF, FFE00000, 0000001F, FFFE0000]
test_vsl_69_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [0001FFFF, FFE00000, 00000007, FFE00000]
test_vsl_70_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [003FFFFF, FFC00000, 0000003F, FFC00000]
test_vsl_71_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [000FFFFF, FFC00000, 00000001, FFFC0000]
test_vsl_72_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [001FFFFF, FFFC0000, 0000001F, FFF80000]
test_vsl_73_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [007FFFFF, FFFF0000, 0000007F, FFFF0000]
test_vsl_74_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [007FFFFF, FFFF0000, 0000007F, FFFE0000]
test_vsl_75_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [007FFFFF, FF800000, 0000007F, FF800000]
test_vsl_76_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_vsl_77_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [00010206, 0405060E, 08090A16, 0C0D0E1E]
test_vsl_78_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [00010182, 02830607, 08090A0B, 06870E0F]
test_vsl_79_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [00200260, 04A006E1, 08210A61, 0CA10EE0]
test_vsl_80_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [00020818, 40A08184, 08122858, C0A18380]
test_vsl_81_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [00810103, 04050307, 04090A86, 06870E80]
test_vsl_82_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [00102030, 40506070, 8090A0B0, C0D0E0F0]
test_vsl_83_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [00810182, 02830384, 04850586, 06870780]
test_vsl_84_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_vsl_85_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [0004080C, 1014181C, 2024282C, 3034383C]
test_vsl_86_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [00108003, 02A0300E, 102450B0, 8143070F]
test_vsl_87_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [00010203, 02050607, 0490A061, 06687078]
test_vsl_88_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [00010203, 08050607, 10090A0B, 180D0E0F]
test_vsl_89_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00010818, 40A08184, 04092858, C0A18380]
test_vsl_90_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [00010203, 04830607, 04850586, 06870780]
test_vsl_91_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [00010203, 02050607, 0490A061, 06687078]
test_vsl_92_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [00010203, 08050607, 10090A0B, 180D0E0F]
test_vsl_93_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [00204060, 80A0C0E1, 01214161, C01A3878]
test_vsl_94_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [00020818, 40A08184, 08122858, C0A18380]
test_vsl_95_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [004080C1, 014181C2, 024282C3, 034383C0]
test_vsl_96_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00100160, 02410384, 08090A16, 0C340E78]
test_vsl_97_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [002001C1, 0414060E, 04900561, 0C680E3C]
test_vsl_98_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [00810406, 04050384, 04850586, 0C0D0E0F]
test_vsl_99_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [00810103, 04050684, 04420586, 0C1A0E0F]
test_vsl_100_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00810182, 02830384, 04850586, 06870780]
test_vsl_101_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
test_vsl_102_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [000D001A, 000D001A, 000D001A, 000D001A]
test_vsl_103_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [000D0680, 0680000D, 000D000D, 0680000D]
test_vsl_104_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [001A0068, 00A00380, 001A0068, 00A00380]
test_vsl_105_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [001A0068, 00A00380, 001A0068, 00A00380]
test_vsl_106_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [0080060D, 000D060D, 060D0080, 06800080]
test_vsl_107_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [00D000D0, 00D000D0, 00D000D0, 00D000D0]
test_vsl_108_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [06800680, 06800680, 06800680, 06800680]
test_vsl_109_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
test_vsl_110_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [00340034, 00340034, 00340034, 00340034]
test_vsl_111_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [00D0030D, 06A0001A, 003400D0, 0140060D]
test_vsl_112_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [060D000D, 060D000D, 06D000A0, 06680068]
test_vsl_113_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
test_vsl_114_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [060D0068, 00A00380, 060D0068, 00A00380]
test_vsl_115_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [000D000D, 0080000D, 06800680, 06800680]
test_vsl_116_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [060D000D, 060D000D, 06D000A0, 06680068]
test_vsl_117_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
test_vsl_118_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [01A001A0, 01A001A0, 01A001A0, 001A0068]
test_vsl_119_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [001A0068, 00A00380, 001A0068, 00A00380]
test_vsl_120_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [03400340, 03400340, 03400340, 03400340]
test_vsl_121_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [06D006A0, 06400680, 000D001A, 00340068]
test_vsl_122_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [06A00640, 0034001A, 06D006A0, 00680034]
test_vsl_123_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [0680001A, 000D0680, 06800680, 000D000D]
test_vsl_124_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [0680060D, 000D0080, 06400680, 001A000D]
test_vsl_125_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [06800680, 06800680, 06800680, 06800680]
test_vsl_126_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
test_vsl_127_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [00112266, 445566EF, 8899AA77, CCDDEEFE]
test_vsl_128_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [001119A2, 2AB36677, 8899AABB, 6EF7EEFF]
test_vsl_129_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [0022889A, 45AC9DC4, 8833AADE, CDBDBF80]
test_vsl_130_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [00242268, 44AC66F1, 8835AA79, CCBDEEE0]
test_vsl_131_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [00911933, 44553B77, 4C99AAE6, 6EF7EE80]
test_vsl_132_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [01122334, 45566778, 899AABBC, CDDEEFF0]
test_vsl_133_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [089119A2, 2AB33BC4, 4CD55DE6, 6EF77F80]
test_vsl_134_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
test_vsl_135_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [004488CD, 115599DE, 2266AAEF, 3377BBFC]
test_vsl_136_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [00128C33, 2AAC33EF, 116655BC, 9B7B7FFF]
test_vsl_137_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [08112233, 2A556677, 4C9AAB79, 6EEF77F8]
test_vsl_138_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [00112233, 88556677, 1199AABB, 99DDEEFF]
test_vsl_139_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [0811889A, 45AC9DC4, 4C99AADE, CDBDBF80]
test_vsl_140_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [00112233, 44B36677, 4CD55DE6, 6EF77F80]
test_vsl_141_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [08112233, 2A556677, 4C9AAB79, 6EEF77F8]
test_vsl_142_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [00112233, 88556677, 1199AABB, 99DDEEFF]
test_vsl_143_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [02244668, 8AACCEF1, 13355779, CDBBBBF8]
test_vsl_144_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [0022889A, 45AC9DC4, 8833AADE, CDBDBF80]
test_vsl_145_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [04488CD1, 15599DE2, 266AAEF3, 377BBFC0]
test_vsl_146_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [08121968, 2A593BC4, 8899AA77, CC77EEF8]
test_vsl_147_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [082419D1, 445566EF, 4C9A5D79, CCEFEEFC]
test_vsl_148_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [08914466, 44553BC4, 4CD55DE6, CCDDEEFF]
test_vsl_149_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [08911933, 445566C4, 4C6A5DE6, CCBBEEFF]
test_vsl_150_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [089119A2, 2AB33BC4, 4CD55DE6, 6EF77F80]
test_vsl_151_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
test_vsl_152_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [00FFFF00, 0000FF01, FF0000FF, FFFF00FE]
test_vsl_153_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [00FF8000, 007FFF00, FF0000FF, FF8000FF]
test_vsl_154_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00FFFC00, 001FC07F, FF0003FF, FFE03F80]
test_vsl_155_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [00FFFF00, 001FFF1F, FF0000FF, FFE000E0]
test_vsl_156_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [00FFFC00, 001FC07F, FF0003FF, FFE03F80]
test_vsl_157_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [0FFFF000, 000FF00F, F0000FFF, FFF00FF0]
test_vsl_158_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [7FFF8000, 007F807F, 80007FFF, FF807F80]
test_vsl_159_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
test_vsl_160_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [03FFFC00, 0003FC03, FC0003FF, FFFC03FC]
test_vsl_161_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [03FFC000, 001FF801, FE0007FF, FFC07FFF]
test_vsl_162_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [7FFFFF00, 0000FF00, 80000FFF, FFF807F8]
test_vsl_163_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [01FFFF00, 0000FF00, FE0000FF, FFFF00FF]
test_vsl_164_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7FFFFC00, 001FC07F, 800003FF, FFE03F80]
test_vsl_165_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [00FFFF00, 007FFF00, 80007FFF, FF807F80]
test_vsl_166_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [7FFFFF00, 0000FF00, 80000FFF, FFF807F8]
test_vsl_167_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [01FFFF00, 0000FF00, FE0000FF, FFFF00FF]
test_vsl_168_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [1FFFE000, 001FE01F, E0001FFF, FFFE03F8]
test_vsl_169_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [00FFFC00, 001FC07F, FF0003FF, FFE03F80]
test_vsl_170_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [3FFFC000, 003FC03F, C0003FFF, FFC03FC0]
test_vsl_171_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [7FFF8000, 003F807F, FF0000FF, FFFC00F8]
test_vsl_172_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [7FFF8000, 0003FF01, 80007FFF, FFF800FC]
test_vsl_173_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [7FFFFE00, 0000807F, 80007FFF, FFFF00FF]
test_vsl_174_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [7FFF8000, 0000FF7F, 80007FFF, FFFE00FF]
test_vsl_175_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [7FFF8000, 007F807F, 80007FFF, FF807F80]
test_vsl_176_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
test_vsl_177_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [04040408, 04040408, 04040408, 04040408]
test_vsl_178_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [04040202, 02020404, 04040404, 02020404]
test_vsl_179_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [04081020, 40800102, 04081020, 40800100]
test_vsl_180_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [04800480, 04800480, 04800480, 04800480]
test_vsl_181_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [04081020, 40800102, 04081020, 40800100]
test_vsl_182_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [04020204, 04040204, 02040402, 02020400]
test_vsl_183_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [02020202, 02020202, 02020202, 02020200]
test_vsl_184_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
test_vsl_185_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [10101010, 10101010, 10101010, 10101010]
test_vsl_186_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [10400104, 02802008, 08102040, 80010204]
test_vsl_187_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [02040404, 02040404, 02404080, 02202020]
test_vsl_188_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [08040404, 08040404, 08040404, 08040404]
test_vsl_189_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [02041020, 40800102, 02041020, 40800100]
test_vsl_190_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [04040404, 04020404, 02020202, 02020200]
test_vsl_191_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [02040404, 02040404, 02404080, 02202020]
test_vsl_192_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [08040404, 08040404, 08040404, 08040404]
test_vsl_193_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 40081020]
test_vsl_194_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [04081020, 40800102, 04081020, 40800100]
test_vsl_195_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010100]
test_vsl_196_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [02400280, 02010202, 04040408, 04100420]
test_vsl_197_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [02800201, 04100408, 02400280, 04200410]
test_vsl_198_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [02020808, 04040202, 02020202, 04040404]
test_vsl_199_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [02020204, 04040402, 02010202, 04080404]
test_vsl_200_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [02020202, 02020202, 02020202, 02020200]
test_vsl_201_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707]
test_vsl_202_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [0707070E, 0707070E, 0707070E, 0707070E]
test_vsl_203_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [07078383, 83830707, 07070707, 83830707]
test_vsl_204_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [070E1C38, 70E0C183, 070E1C38, 70E0C180]
test_vsl_205_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [07E007E0, 07E007E0, 07E007E0, 07E007E0]
test_vsl_206_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [070E1C38, 70E0C183, 070E1C38, 70E0C180]
test_vsl_207_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [07838307, 07078307, 83070783, 83830780]
test_vsl_208_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [70707070, 70707070, 70707070, 70707070]
test_vsl_209_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707]
test_vsl_210_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [1C1C1C1C, 1C1C1C1C, 1C1C1C1C, 1C1C1C1C]
test_vsl_211_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [1C70C107, 83E0380E, 0E1C3870, E0C18307]
test_vsl_212_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [83070707, 83070707, 837070E0, 83383838]
test_vsl_213_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [0E070707, 0E070707, 0E070707, 0E070707]
test_vsl_214_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [83071C38, 70E0C183, 83071C38, 70E0C180]
test_vsl_215_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [07070707, 07830707, 83838383, 83838380]
test_vsl_216_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [83070707, 83070707, 837070E0, 83383838]
test_vsl_217_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [0E070707, 0E070707, 0E070707, 0E070707]
test_vsl_218_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [E0E0E0E0, E0E0E0E0, E0E0E0E0, 700E1C38]
test_vsl_219_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [070E1C38, 70E0C183, 070E1C38, 70E0C180]
test_vsl_220_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [C1C1C1C1, C1C1C1C1, C1C1C1C1, C1C1C1C0]
test_vsl_221_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [837083E0, 83C18383, 0707070E, 071C0738]
test_vsl_222_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [83E083C1, 071C070E, 837083E0, 0738071C]
test_vsl_223_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [83830E0E, 07078383, 83838383, 07070707]
test_vsl_224_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [83838307, 07070783, 83C18383, 070E0707]
test_vsl_225_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [83838383, 83838383, 83838383, 83838380]
test_vsl_226_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
test_vsl_227_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [08080810, 08080810, 08080810, 08080810]
test_vsl_228_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [08080404, 04040808, 08080808, 04040808]
test_vsl_229_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [08102040, 80010204, 08102040, 80010200]
test_vsl_230_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [08010801, 08010801, 08010801, 08010800]
test_vsl_231_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [08102040, 80010204, 08102040, 80010200]
test_vsl_232_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [08040408, 08080408, 04080804, 04040800]
test_vsl_233_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 80808080]
test_vsl_234_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040400]
test_vsl_235_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [20202020, 20202020, 20202020, 20202020]
test_vsl_236_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [20800208, 04014010, 10204080, 01020408]
test_vsl_237_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [04080808, 04080808, 04808001, 04404040]
test_vsl_238_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [10080808, 10080808, 10080808, 10080808]
test_vsl_239_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [04082040, 80010204, 04082040, 80010200]
test_vsl_240_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [08080808, 08040808, 04040404, 04040400]
test_vsl_241_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [04080808, 04080808, 04808001, 04404040]
test_vsl_242_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [10080808, 10080808, 10080808, 10080808]
test_vsl_243_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 80102040]
test_vsl_244_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [08102040, 80010204, 08102040, 80010200]
test_vsl_245_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [02020202, 02020202, 02020202, 02020200]
test_vsl_246_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [04800401, 04020404, 08080810, 08200840]
test_vsl_247_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [04010402, 08200810, 04800401, 08400820]
test_vsl_248_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [04041010, 08080404, 04040404, 08080808]
test_vsl_249_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [04040408, 08080804, 04020404, 08100808]
test_vsl_250_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040400]
test_vsl_251_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212]
test_vsl_252_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [12121224, 12121224, 12121224, 12121224]
test_vsl_253_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [12120909, 09091212, 12121212, 09091212]
test_vsl_254_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [12244890, 21428409, 12244890, 21428400]
test_vsl_255_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [12421242, 12421242, 12421242, 12421240]
test_vsl_256_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [12244890, 21428409, 12244890, 21428400]
test_vsl_257_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [12090912, 12120912, 09121209, 09091200]
test_vsl_258_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [21212121, 21212121, 21212121, 21212120]
test_vsl_259_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [09090909, 09090909, 09090909, 09090900]
test_vsl_260_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212]
test_vsl_261_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [48218412, 09429024, 24489021, 42840912]
test_vsl_262_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [09121212, 09121212, 09212142, 09909090]
test_vsl_263_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [24121212, 24121212, 24121212, 24121212]
test_vsl_264_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [09124890, 21428409, 09124890, 21428400]
test_vsl_265_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [12121212, 12091212, 09090909, 09090900]
test_vsl_266_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [09121212, 09121212, 09212142, 09909090]
test_vsl_267_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [24121212, 24121212, 24121212, 24121212]
test_vsl_268_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [42424242, 42424242, 42424242, 21244890]
test_vsl_269_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [12244890, 21428409, 12244890, 21428400]
test_vsl_270_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [84848484, 84848484, 84848484, 84848480]
test_vsl_271_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [09210942, 09840909, 12121224, 12481290]
test_vsl_272_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [09420984, 12481224, 09210942, 12901248]
test_vsl_273_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [09092424, 12120909, 09090909, 12121212]
test_vsl_274_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [09090912, 12121209, 09840909, 12241212]
test_vsl_275_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [09090909, 09090909, 09090909, 09090900]
test_vsl_276_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788]
test_vsl_277_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [123456F1, 87654342, 11223388, 55667710]
test_vsl_278_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [12343C43, B2A14321, 11223344, B33B7788]
test_vsl_279_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [126859C4, 76A8C888, 1144CD22, 56CEE200]
test_vsl_280_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [128A5610, 87A84322, 1146338A, 55CE7700]
test_vsl_281_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [126859C4, 76A8C888, 1144CD22, 56CEE200]
test_vsl_282_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [122B3C78, 87659021, 9122332A, B33B7700]
test_vsl_283_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [23456788, 76543211, 12233445, 56677880]
test_vsl_284_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [1A2B3C43, B2A19088, 9119A22A, B33BC400]
test_vsl_285_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788]
test_vsl_286_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [48D159E2, 1D950C84, 4488CD11, 5599DE20]
test_vsl_287_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [1A345678, B2654321, 9123348A, B333BC40]
test_vsl_288_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [24345678, 0E654321, 22223344, AA667788]
test_vsl_289_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [1A3459C4, 76A8C888, 9122CD22, 56CEE200]
test_vsl_290_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [12345678, 87A14321, 9119A22A, B33BC400]
test_vsl_291_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [1A345678, B2654321, 9123348A, B333BC40]
test_vsl_292_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [24345678, 0E654321, 22223344, AA667788]
test_vsl_293_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [468ACF10, ECA86422, 2446688A, 56CCDE40]
test_vsl_294_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [126859C4, 76A8C888, 1144CD22, 56CEE200]
test_vsl_295_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [8D159E21, D950C844, 488CD115, 599DE200]
test_vsl_296_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [1A453C10, B2509088, 11223388, 55997740]
test_vsl_297_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [1A8A3C21, 87954342, 9123A28A, 55337720]
test_vsl_298_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [1A2BACF1, 87659088, 9119A22A, 55667788]
test_vsl_299_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [1A2B3C78, 87654388, 918CA22A, 55CC7788]
test_vsl_300_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [1A2B3C43, B2A19088, 9119A22A, B33BC400]
test_vsl_301_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
test_vsl_302_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCC9A, 3FF33366]
test_vsl_303_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [3F80001F, E0000000, 3F8CCCCD, F9993333]
test_vsl_304_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [3F000001, FC00001F, 3F193369, FF66CC80]
test_vsl_305_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [3F000007, 3F000007, 3F99CCA7, 3F663360]
test_vsl_306_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [3F000001, FC00001F, 3F193369, FF66CC80]
test_vsl_307_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [3F000000, 3FC00000, C68CCC9F, F9993380]
test_vsl_308_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [F8000003, FC000003, F8CCCCD3, FF333330]
test_vsl_309_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [C000001F, E000001F, C666669F, F9999980]
test_vsl_310_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
test_vsl_311_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [FE000000, FF000000, FE333334, FFCCCCCC]
test_vsl_312_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [FE000000, E0000000, 7F3366D3, FECC9933]
test_vsl_313_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [7F800000, 7FC00000, 7F8CCCCD, 7FF33333]
test_vsl_314_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [C0800001, FC00001F, C68C3369, FF66CC80]
test_vsl_315_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [3F800000, 3F000000, C666669F, F9999980]
test_vsl_316_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [C0800000, E0C00000, C6CCCCA7, F9999998]
test_vsl_317_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [7F800000, 7FC00000, 7F8CCCCD, 7FF33333]
test_vsl_318_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [F0000007, F8000007, F19999A7, FFE6CC98]
test_vsl_319_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [3F000001, FC00001F, 3F193369, FF66CC80]
test_vsl_320_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [E000000F, F000000F, E333334F, FCCCCCC0]
test_vsl_321_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [C0000007, E000001F, 3F8CCC9A, 3FCC3398]
test_vsl_322_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [C000000F, 3F000000, C6CC66A7, 3F9933CC]
test_vsl_323_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [C0000000, 3FC0001F, C666669F, 3FF33333]
test_vsl_324_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [C0000000, 3FC0001F, C633669F, 3FE63333]
test_vsl_325_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [C000001F, E000001F, C666669F, F9999980]
test_vsl_326_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
test_vsl_327_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [41200001, C1200000, 41700001, C1700000]
test_vsl_328_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [41200060, 90000000, 41700000, B8000000]
test_vsl_329_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [41400006, 12000020, 41E00006, 17000000]
test_vsl_330_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [41000018, C1000008, 41000018, C1000000]
test_vsl_331_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [41400006, 12000020, 41E00006, 17000000]
test_vsl_332_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [41000000, C1200000, B8700060, B8000000]
test_vsl_333_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [1200000C, 12000004, 1700000C, 17000000]
test_vsl_334_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [90000060, 90000020, B8000060, B8000000]
test_vsl_335_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
test_vsl_336_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [04800003, 04800001, 05C00003, 05C00000]
test_vsl_337_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [04000000, 90000000, 82C0000C, 2E000000]
test_vsl_338_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [90200000, 90200000, B8000018, B8800000]
test_vsl_339_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [90200006, 12000020, B8700006, 17000000]
test_vsl_340_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [41200000, C1000000, B8000060, B8000000]
test_vsl_341_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [90200000, 90200000, B8000018, B8800000]
test_vsl_342_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [82200000, 82200000, 82700000, 82700000]
test_vsl_343_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [24000018, 24000008, 2E000018, 17E00000]
test_vsl_344_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [41400006, 12000020, 41E00006, 17000000]
test_vsl_345_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [48000030, 48000010, 5C000030, 5C000000]
test_vsl_346_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [90000018, 90000020, 41700001, C1C00000]
test_vsl_347_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [90000030, C1800000, B8000018, C1800000]
test_vsl_348_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [90000001, C1200020, B8000060, C1700000]
test_vsl_349_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [90000000, C1200020, B8000060, C1E00000]
test_vsl_350_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [90000060, 90000020, B8000060, B8000000]
test_vsl_351_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
test_vsl_352_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [7F800206, 0405060E, 7F800A16, 0C0D0E1E]
test_vsl_353_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [7F800182, 02830607, 7F800A0B, 06870E0F]
test_vsl_354_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7F000818, 40A081BF, 7F002858, C0A18380]
test_vsl_355_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [7F000260, 04A006EF, 7F010A61, 0CA10EE0]
test_vsl_356_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [7F000818, 40A081BF, 7F002858, C0A18380]
test_vsl_357_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [7F010103, 04050307, C0800A86, 06870E80]
test_vsl_358_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [F8002030, 40506077, F800A0B0, C0D0E0F0]
test_vsl_359_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [C0010182, 028303BF, C0050586, 06870780]
test_vsl_360_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
test_vsl_361_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [FE00080C, 1014181D, FE00282C, 3034383C]
test_vsl_362_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [FE008003, 02A0300E, FF0050B0, 8143070F]
test_vsl_363_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [C0800203, 02050607, C000A061, 06687078]
test_vsl_364_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [FF800203, 08050607, FF800A0B, 180D0E0F]
test_vsl_365_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7F800203, 04830607, C0050586, 06870780]
test_vsl_366_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [C0800203, 02050607, C000A061, 06687078]
test_vsl_367_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [FF800203, 08050607, FF800A0B, 180D0E0F]
test_vsl_368_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [F0004060, 80A0C0EF, F0014161, C01A3878]
test_vsl_369_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [7F000818, 40A081BF, 7F002858, C0A18380]
test_vsl_370_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [E00080C1, 014181DF, E00282C3, 034383C0]
test_vsl_371_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [C0000160, 024103BF, 7F800A16, 0C340E78]
test_vsl_372_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [C00001C1, 0414060E, C0000561, 0C680E3C]
test_vsl_373_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [C0010406, 040503BF, C0050586, 0C0D0E0F]
test_vsl_374_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [C0010103, 040506BF, C0020586, 0C1A0E0F]
test_vsl_375_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [C0010182, 028303BF, C0050586, 06870780]
test_vsl_376_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
test_vsl_377_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [80081021, 808F0000, 7FFFFFFF, 8FFFFFFE]
test_vsl_378_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [80080840, 47800000, 7FFFFFFF, FFFFFFFF]
test_vsl_379_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [80104084, 08E0003F, 7FFFFFFC, FFFFFF80]
test_vsl_380_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [80021010, 80E0000F, 7FFFFFF1, 8FFFFFE0]
test_vsl_381_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [80104084, 08E0003F, 7FFFFFFC, FFFFFF80]
test_vsl_382_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [80080810, 808F0000, FFFFFFC7, FFFFFF80]
test_vsl_383_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [00810108, 08F00007, FFFFFFF8, FFFFFFF0]
test_vsl_384_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [04080840, 4780003F, FFFFFFC7, FFFFFF80]
test_vsl_385_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
test_vsl_386_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [00204042, 023C0001, FFFFFFFE, 3FFFFFFC]
test_vsl_387_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [00810410, 47E00000, FFFFFFF8, FFFFFFFF]
test_vsl_388_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [04081010, 478F0000, FFFFFFF1, FFFFFFF8]
test_vsl_389_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [00081010, 018F0000, FFFFFFFF, 1FFFFFFF]
test_vsl_390_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [04084084, 08E0003F, FFFFFFFC, FFFFFF80]
test_vsl_391_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [04081010, 478F0000, FFFFFFF1, FFFFFFF8]
test_vsl_392_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [00081010, 018F0000, FFFFFFFF, 1FFFFFFF]
test_vsl_393_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [01020210, 11E0000F, FFFFFFF1, FFFFFFF8]
test_vsl_394_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [80104084, 08E0003F, 7FFFFFFC, FFFFFF80]
test_vsl_395_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [02040420, 23C0001F, FFFFFFE3, FFFFFFC0]
test_vsl_396_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [04810810, 47C0003F, 7FFFFFFF, 8FFFFFF8]
test_vsl_397_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [04020820, 803C0000, FFFFFFF1, 8FFFFFFC]
test_vsl_398_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [04082021, 808F003F, FFFFFFC7, 8FFFFFFF]
test_vsl_399_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [04080810, 808F003F, FFFFFFC7, 8FFFFFFF]
test_vsl_400_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [04080840, 4780003F, FFFFFFC7, FFFFFF80]
test_vsl_401_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333]
test_vsl_402_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [BF800001, BFC00001, BF8CCC9B, BFF33366]
test_vsl_403_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [BF80005F, E0000000, BF8CCCCD, F9993333]
test_vsl_404_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [BF000005, FC00005F, BF19336D, FF66CC80]
test_vsl_405_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [BF000017, BF000017, BF99CCB7, BF663360]
test_vsl_406_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [BF000005, FC00005F, BF19336D, FF66CC80]
test_vsl_407_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [BF000000, BFC00000, C68CCCDF, F9993380]
test_vsl_408_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [F800000B, FC00000B, F8CCCCDB, FF333330]
test_vsl_409_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [C000005F, E000005F, C66666DF, F9999980]
test_vsl_410_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333]
test_vsl_411_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [FE000002, FF000002, FE333336, FFCCCCCC]
test_vsl_412_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [FE000000, E0000001, 7F3366DB, FECC9933]
test_vsl_413_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [C0800000, E0C00000, C6CCCCB7, F9999998]
test_vsl_414_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [7F800000, 7FC00000, 7F8CCCCD, 7FF33333]
test_vsl_415_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [C0800005, FC00005F, C68C336D, FF66CC80]
test_vsl_416_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [BF800000, BF000000, C66666DF, F9999980]
test_vsl_417_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [7F800000, 7FC00000, 7F8CCCCD, 7FF33333]
test_vsl_418_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [F0000017, F8000017, F19999B7, FFE6CC98]
test_vsl_419_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [BF000005, FC00005F, BF19336D, FF66CC80]
test_vsl_420_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [E000002F, F000002F, E333336F, FCCCCCC0]
test_vsl_421_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [C0000017, E000005F, BF8CCC9B, BFCC3398]
test_vsl_422_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [C000002F, BF000001, C6CC66B7, BF9933CC]
test_vsl_423_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [C0000001, BFC0005F, C66666DF, BFF33333]
test_vsl_424_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [C0000000, BFC0005F, C63366DF, BFE63333]
test_vsl_425_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [C000005F, E000005F, C66666DF, F9999980]
test_vsl_426_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000]
test_vsl_427_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [C1200000, 41A00001, C1A00000, 41F00000]
test_vsl_428_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [C1200020, D0000000, C1A00000, F8000000]
test_vsl_429_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [C1400002, 1A000060, C1400002, 1F000000]
test_vsl_430_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [C1000008, 41000018, C1000008, 41000000]
test_vsl_431_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [C1400002, 1A000060, C1400002, 1F000000]
test_vsl_432_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [C1000000, 41A00000, D0A00020, F8000000]
test_vsl_433_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [12000004, 1A00000C, 1A000004, 1F000000]
test_vsl_434_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [90000020, D0000060, D0000020, F8000000]
test_vsl_435_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000]
test_vsl_436_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [04800001, 06800003, 06800001, 07C00000]
test_vsl_437_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [04000000, D0000001, 83800004, 3E000000]
test_vsl_438_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [90200000, D0A00000, D0000008, F8800000]
test_vsl_439_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [82200000, 83A00000, 83A00000, 83F00000]
test_vsl_440_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [90200002, 1A000060, D0A00002, 1F000000]
test_vsl_441_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [C1200000, 41000000, D0000020, F8000000]
test_vsl_442_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [90200000, D0A00000, D0000008, F8800000]
test_vsl_443_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [24000008, 34000018, 34000008, 1FE00000]
test_vsl_444_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [C1400002, 1A000060, C1400002, 1F000000]
test_vsl_445_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [48000010, 68000030, 68000010, 7C000000]
test_vsl_446_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [90000008, D0000060, C1A00000, 41C00000]
test_vsl_447_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [90000010, 41800001, D0000008, 41800000]
test_vsl_448_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [90000000, 41A00060, D0000020, 41F00000]
test_vsl_449_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [90000000, 41A00060, D0000020, 41E00000]
test_vsl_450_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [90000020, D0000060, D0000020, F8000000]
test_vsl_451_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
test_vsl_452_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [CDCDCD9B, CDCDCD9B, CDCDCD9A, 04010206]
test_vsl_453_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [CDCDE6E6, E6E6CDCD, CDCDCDCD, 00810203]
test_vsl_454_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [CD9B376E, DCB973E6, CD9B3768, 40208080]
test_vsl_455_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [CDB9CDB9, CDB9CDB9, CDB9CDA0, 04200260]
test_vsl_456_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [CD9B376E, DCB973E6, CD9B3768, 40208080]
test_vsl_457_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [CDE6E6CD, CDCDE6CD, E6CDCD82, 00810280]
test_vsl_458_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [DCDCDCDC, DCDCDCDC, DCDCDCD0, 40102030]
test_vsl_459_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [E6E6E6E6, E6E6E6E6, E6E6E682, 00810180]
test_vsl_460_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
test_vsl_461_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [37373737, 37373737, 37373734, 1004080C]
test_vsl_462_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [37DC73CD, E6B96E9B, 9B376ED0, 80400103]
test_vsl_463_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [E6CDCDCD, E6CDCDCD, E6DCDCA0, 00081018]
test_vsl_464_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [9BCDCDCD, 9BCDCDCD, 9BCDCDCD, 08010203]
test_vsl_465_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [E6CD376E, DCB973E6, E6CD3768, 40208080]
test_vsl_466_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [CDCDCDCD, CDE6CDCD, E6E6E682, 00810180]
test_vsl_467_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [E6CDCDCD, E6CDCDCD, E6DCDCA0, 00081018]
test_vsl_468_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [9BCDCDCD, 9BCDCDCD, 9BCDCDCD, 08010203]
test_vsl_469_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [CD9B376E, DCB973E6, CD9B3768, 40208080]
test_vsl_470_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [73737373, 73737373, 73737341, 004080C0]
test_vsl_471_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [E6DCE6B9, E673E6E6, CDCDCD9A, 04040218]
test_vsl_472_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [E6B9E673, CD37CD9B, E6DCE6A0, 0408020C]
test_vsl_473_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [E6E69B9B, CDCDE6E6, E6E6E682, 04010203]
test_vsl_474_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [E6E6E6CD, CDCDCDE6, E673E682, 04020203]
test_vsl_475_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [E6E6E6E6, E6E6E6E6, E6E6E682, 00810180]
test_vsl_476_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
test_vsl_477_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [F8F9FAF7, FCFDFEFE, 00010206, 0405060E]
test_vsl_478_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [F8F97DFE, 7EFFFEFF, 00010203, 02830607]
test_vsl_479_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [F8F3EBDF, CFBFBF80, 00020818, 40A08180]
test_vsl_480_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [F83FFA7F, FCBFFEE0, 00200260, 04A006E0]
test_vsl_481_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [F8F3EBDF, CFBFBF80, 00020818, 40A08180]
test_vsl_482_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [F8FD7DFB, FCFD7FFF, 00010282, 02830680]
test_vsl_483_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [8F9FAFBF, CFDFEFF0, 00102030, 40506070]
test_vsl_484_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [7CFD7DFE, 7EFF7F80, 00810182, 02830380]
test_vsl_485_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
test_vsl_486_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [E3E7EBEF, F3F7FBFC, 0004080C, 1014181C]
test_vsl_487_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [E39FBEFB, 7EBFF7FE, 00041030, 80410307]
test_vsl_488_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [7CF9FAFB, 7EFDFEFF, 00102060, 02283038]
test_vsl_489_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [F1F9FAFB, F9FDFEFF, 00010203, 08050607]
test_vsl_490_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7CF9EBDF, CFBFBF80, 00010818, 40A08180]
test_vsl_491_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [F8F9FAFB, FCFFFEFF, 00810182, 02830380]
test_vsl_492_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [7CF9FAFB, 7EFDFEFF, 00102060, 02283038]
test_vsl_493_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [F1F9FAFB, F9FDFEFF, 00010203, 08050607]
test_vsl_494_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [1F3F5F7F, 9FBFDFE0, 00204060, 400A1838]
test_vsl_495_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [3E7EBEFF, 3F7FBFC0, 004080C1, 014181C0]
test_vsl_496_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [7C9F7D7F, 7E7F7F80, 00010206, 04140638]
test_vsl_497_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [7C3F7DFF, FCF7FEFE, 00100160, 0428061C]
test_vsl_498_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [7CFDF5F7, FCFD7F80, 00810182, 04050607]
test_vsl_499_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [7CFD7DFB, FCFDFE80, 00400182, 040A0607]
test_vsl_500_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [7CFD7DFE, 7EFF7F80, 00810182, 02830380]
test_vsl_501_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
test_vsl_502_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FEFEFEFD, FEFEFEFD, FEFEFEFD, FEFEFEFC]
test_vsl_503_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FEFE7F7F, 7F7FFEFE, FEFEFEFE, 7F7FFEFE]
test_vsl_504_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FEFDFBF7, EFDFBF7F, FEFDFBF7, EFDFBF00]
test_vsl_505_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FEDFFEDF, FEDFFEDF, FEDFFEDF, FEDFFEC0]
test_vsl_506_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FEFDFBF7, EFDFBF7F, FEFDFBF7, EFDFBF00]
test_vsl_507_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FE7F7FFE, FEFE7FFE, 7FFEFE7F, 7F7FFE00]
test_vsl_508_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [EFEFEFEF, EFEFEFEF, EFEFEFEF, EFEFEFE0]
test_vsl_509_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F00]
test_vsl_510_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
test_vsl_511_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [FBFBFBFB, FBFBFBFB, FBFBFBFB, FBFBFBF8]
test_vsl_512_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [FBEFBFFE, 7FDFF7FD, FDFBF7EF, DFBF7FFE]
test_vsl_513_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [7FFEFEFE, 7FFEFEFE, 7FEFEFDF, 7FF7F7F0]
test_vsl_514_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [FDFEFEFE, FDFEFEFE, FDFEFEFE, FDFEFEFE]
test_vsl_515_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7FFEFBF7, EFDFBF7F, 7FFEFBF7, EFDFBF00]
test_vsl_516_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FEFEFEFE, FE7FFEFE, 7F7F7F7F, 7F7F7F00]
test_vsl_517_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [7FFEFEFE, 7FFEFEFE, 7FEFEFDF, 7FF7F7F0]
test_vsl_518_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [FDFEFEFE, FDFEFEFE, FDFEFEFE, FDFEFEFE]
test_vsl_519_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [DFDFDFDF, DFDFDFDF, DFDFDFDF, EFFDFBF0]
test_vsl_520_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FEFDFBF7, EFDFBF7F, FEFDFBF7, EFDFBF00]
test_vsl_521_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [7FEF7FDF, 7FBF7F7F, FEFEFEFD, FEFBFEF0]
test_vsl_522_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [7FDF7FBF, FEFBFEFD, 7FEF7FDF, FEF7FEF8]
test_vsl_523_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [7F7FFDFD, FEFE7F7F, 7F7F7F7F, FEFEFEFE]
test_vsl_524_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [7F7F7FFE, FEFEFE7F, 7FBF7F7F, FEFDFEFE]
test_vsl_525_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F00]
test_vsl_526_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
test_vsl_527_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFCFFFB, FFFEFFFE, 00000002, 00020006]
test_vsl_528_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFCFEFF, FF7FFFFF, 00000001, 01000003]
test_vsl_529_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFF9FFEF, FFDFFF80, 00000008, 00400080]
test_vsl_530_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FF9FFFBF, FFDFFFE0, 00000020, 00400060]
test_vsl_531_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFF9FFEF, FFDFFF80, 00000008, 00400080]
test_vsl_532_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FF7FFEFD, FFFEFFFF, 00000080, 01000080]
test_vsl_533_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FFCFFFDF, FFEFFFF0, 00000010, 00200030]
test_vsl_534_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [FE7FFEFF, FF7FFF80, 00000080, 01000180]
test_vsl_535_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
test_vsl_536_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [FFF3FFF7, FFFBFFFC, 00000004, 0008000C]
test_vsl_537_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [FFCFFFFD, FFDFFFFE, 00000010, 00800103]
test_vsl_538_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [FEFCFFFD, FFFEFFFF, 00000020, 01100018]
test_vsl_539_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
test_vsl_540_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FEFCFFEF, FFDFFF80, 00000008, 00400080]
test_vsl_541_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FFFCFFFD, FF7FFFFF, 00000080, 01000180]
test_vsl_542_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [FEFCFFFD, FFFEFFFF, 00000020, 01100018]
test_vsl_543_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
test_vsl_544_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [FF9FFFBF, FFDFFFE0, 00000020, 00040018]
test_vsl_545_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFF9FFEF, FFDFFF80, 00000008, 00400080]
test_vsl_546_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FF3FFF7F, FFBFFFC0, 00000040, 008000C0]
test_vsl_547_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FE9FFE7F, FFFBFFFE, 00000020, 0010000C]
test_vsl_548_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FE7FFFFB, FFFEFF80, 00000080, 00020003]
test_vsl_549_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FE7FFEFD, FFFEFF80, 00000080, 00040003]
test_vsl_550_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FE7FFEFF, FF7FFF80, 00000080, 01000180]
test_vsl_551_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
test_vsl_552_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFDFFFC, 00020003, FFFCFFFA, 00030004]
test_vsl_553_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFDBF00, 01000081, FFFCFF7D, 01800082]
test_vsl_554_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFBFDF0, 004020FF, FFF9FDE8, 00602000]
test_vsl_555_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFBFFFC0, 0040003F, FF9FFFA0, 00600040]
test_vsl_556_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFFBFDF0, 004020FF, FFF9FDE8, 00602000]
test_vsl_557_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FFFFBF7E, 00024081, FEFCFF80, 01800000]
test_vsl_558_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FFDFF7E0, 0020081F, FFCFF7D0, 00300820]
test_vsl_559_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [FEFFBF00, 010040FF, FE7FBE80, 01804100]
test_vsl_560_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
test_vsl_561_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [FFF7FDF8, 00080207, FFF3FDF4, 000C0208]
test_vsl_562_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [FFDFDF7E, 01400403, FFF3FBD0, 00C04182]
test_vsl_563_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [FEFDFF7E, 01020081, FECFF7A0, 01180410]
test_vsl_564_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
test_vsl_565_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FEFDFDF0, 004020FF, FEFCFDE8, 00602000]
test_vsl_566_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FFFDFF7E, 00000081, FE7FBE80, 01804100]
test_vsl_567_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [FEFDFF7E, 01020081, FECFF7A0, 01180410]
test_vsl_568_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
test_vsl_569_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [FFBFEFC0, 0040103F, FF9FEFA0, 00060210]
test_vsl_570_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFFBFDF0, 004020FF, FFF9FDE8, 00602000]
test_vsl_571_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FF7FDF80, 0080207F, FF3FDF40, 00C02080]
test_vsl_572_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FEDFBFC0, 018040FF, FFFCFFFA, 000C0010]
test_vsl_573_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FEFFFEFC, 000240FF, FE7FBE80, 00030082]
test_vsl_574_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FEFFBF7E, 000200FF, FE3FBE80, 00060082]
test_vsl_575_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FEFFBF00, 010040FF, FE7FBE80, 01804100]
test_vsl_576_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
test_vsl_577_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFF0102, 7070FFFF, FFFFFFFE, 00000000]
test_vsl_578_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFF80B8, 387FFFFF, FFFFFFFF, 00000000]
test_vsl_579_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFE040B, 071FFFFF, FFFFFFF8, 00000000]
test_vsl_580_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFE0012E, 701FFFFF, FFFFFFE0, 00000000]
test_vsl_581_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFFE040B, 071FFFFF, FFFFFFF8, 00000000]
test_vsl_582_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FF808001, 7070FFFF, FFFFFF80, 00000000]
test_vsl_583_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FFF01017, 070FFFFF, FFFFFFF0, 00000000]
test_vsl_584_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [FF8080B8, 387FFFFF, FFFFFF80, 00000000]
test_vsl_585_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
test_vsl_586_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [FFFC0405, C1C3FFFF, FFFFFFFC, 00000000]
test_vsl_587_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [FFF04001, 381FFFFF, FFFFFFF0, 00000000]
test_vsl_588_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [FFFF0101, 3870FFFF, FFFFFFE0, 00000000]
test_vsl_589_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [FFFF0101, E070FFFF, FFFFFFFF, 00000000]
test_vsl_590_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFF040B, 071FFFFF, FFFFFFF8, 00000000]
test_vsl_591_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FFFF0101, 707FFFFF, FFFFFF80, 00000000]
test_vsl_592_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [FFFF0101, 3870FFFF, FFFFFFE0, 00000000]
test_vsl_593_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [FFFF0101, E070FFFF, FFFFFFFF, 00000000]
test_vsl_594_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [FFE0202E, 0E1FFFFF, FFFFFFE0, 00000000]
test_vsl_595_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFFE040B, 071FFFFF, FFFFFFF8, 00000000]
test_vsl_596_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FFC0405C, 1C3FFFFF, FFFFFFC0, 00000000]
test_vsl_597_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFF0802E, 383FFFFF, FFFFFFFE, 00000000]
test_vsl_598_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFE0805C, 70C3FFFF, FFFFFFE0, 00000000]
test_vsl_599_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FF808001, 7070FFFF, FFFFFF80, 00000000]
test_vsl_600_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FF8080B8, 387FFFFF, FFFFFF80, 00000000]
test_vsl_601_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
test_vsl_602_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFFFF00, 000000FF, FFFEFFFE, 00010000]
test_vsl_603_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFFC000, 0000007F, FFFEFF7F, 00800080]
test_vsl_604_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFFFE00, 00001FFF, FFFDFDF8, 00202000]
test_vsl_605_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFFFFF00, 000000FF, FFDFFFE0, 00200000]
test_vsl_606_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFFFFE00, 00001FFF, FFFDFDF8, 00202000]
test_vsl_607_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FFFFC080, 00003F7F, FFFEFF80, 00800000]
test_vsl_608_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FFFFF800, 000007FF, FFEFF7F0, 00100800]
test_vsl_609_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [FFFFC000, 00003FFF, FF7FBF80, 00804000]
test_vsl_610_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
test_vsl_611_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [FFFFFE00, 000001FF, FFFBFDFC, 00040200]
test_vsl_612_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [FFFFE080, 000003FF, FFFBFBF0, 00404080]
test_vsl_613_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFEFF7E0, 00080400]
test_vsl_614_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
test_vsl_615_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFFFE00, 00001FFF, FFFEFDF8, 00202000]
test_vsl_616_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FF7FBF80, 00804000]
test_vsl_617_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFEFF7E0, 00080400]
test_vsl_618_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
test_vsl_619_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [FFFFF000, 00000FFF, FFDFEFE0, 00020200]
test_vsl_620_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFFFFE00, 00001FFF, FFFDFDF8, 00202000]
test_vsl_621_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FFFFE000, 00001FFF, FFBFDFC0, 00402000]
test_vsl_622_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFFC000, 00003FFF, FFFEFFFE, 00040000]
test_vsl_623_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFFC000, 000000FF, FFEFBFE0, 00080000]
test_vsl_624_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFFFF00, 00003FFF, FF7FBF80, 00010080]
test_vsl_625_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFC000, 00003FFF, FF7FBF80, 00804000]
test_vsl_626_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsl_627_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFE]
test_vsl_628_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsl_629_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF80]
test_vsl_630_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFE0]
test_vsl_631_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF80]
test_vsl_632_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF80]
test_vsl_633_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFF0]
test_vsl_634_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF80]
test_vsl_635_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsl_636_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFC]
test_vsl_637_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsl_638_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFF8]
test_vsl_639_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsl_640_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF80]
test_vsl_641_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF80]
test_vsl_642_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFF8]
test_vsl_643_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsl_644_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFF8]
test_vsl_645_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFF80]
test_vsl_646_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFC0]
test_vsl_647_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFF8]
test_vsl_648_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFC]
test_vsl_649_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsl_650_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsl v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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