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Xenia-Canary/src/xenia/cpu/ppc/testing/instr__gen_vsubsws.s
Dr. Chat 54582cc823 Generated tests from Rick
2019-04-04 18:13:11 -05:00

5851 lines
227 KiB
ArmAsm
Raw Blame History

test_vsubsws_1_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsubsws_2_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFF0001, 00010000, 00000000, 00010000]
test_vsubsws_3_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFEFDFD, FBFAF9F9, F7F6F5F5, F3F2F1F1]
test_vsubsws_4_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFF2FFF3, FFF2FFF3, FFF2FFF3, FFF2FFF3]
test_vsubsws_5_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFEEDDCD, BBAA9989, 77665545, 33221101]
test_vsubsws_6_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FF000100, FFFF0100, 00FFFF01, 0000FF01]
test_vsubsws_7_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FBFBFBFC, FBFBFBFC, FBFBFBFC, FBFBFBFC]
test_vsubsws_8_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [F8F8F8F9, F8F8F8F9, F8F8F8F9, F8F8F8F9]
test_vsubsws_9_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [F7F7F7F8, F7F7F7F8, F7F7F7F8, F7F7F7F8]
test_vsubsws_10_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [EDEDEDEE, EDEDEDEE, EDEDEDEE, EDEDEDEE]
test_vsubsws_11_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [EDCBA988, 789ABCDF, EEDDCCBC, AA998878]
test_vsubsws_12_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [C0800000, C0400000, C0733333, C00CCCCD]
test_vsubsws_13_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [BEE00000, 3EE00000, BE900000, 3E900000]
test_vsubsws_14_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [807FFDFD, FBFAF9F9, 807FF5F5, F3F2F1F1]
test_vsubsws_15_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FF7EFF0, 7F710000, 80000001, 70000001]
test_vsubsws_16_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [40800000, 40400000, 40733333, 400CCCCD]
test_vsubsws_17_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [3EE00000, BE600000, 3E600000, BE100000]
test_vsubsws_18_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [32323233, 32323233, 32323233, FBFEFDFD]
test_vsubsws_19_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [07060505, 03020101, FFFEFDFD, FBFAF9F9]
test_vsubsws_20_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [01010102, 01010102, 01010102, 01010102]
test_vsubsws_21_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00030003, 00010001, FFFFFFFF, FFFDFFFD]
test_vsubsws_22_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00020082, FFFDFF7F, 00030083, FFFCFF7E]
test_vsubsws_23_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [0000FEFF, 8F8F0001, 00000001, 00000000]
test_vsubsws_24_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [00000080, FFFFFF81, 00010081, FFFEFF80]
test_vsubsws_25_GEN:
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
test_vsubsws_26_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
test_vsubsws_27_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFF0002, 00010001, 00000001, 00010001]
test_vsubsws_28_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFEFDFE, FBFAF9FA, F7F6F5F6, F3F2F1F2]
test_vsubsws_29_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFF2FFF4, FFF2FFF4, FFF2FFF4, FFF2FFF4]
test_vsubsws_30_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFEEDDCE, BBAA998A, 77665546, 33221102]
test_vsubsws_31_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FF000101, FFFF0101, 00FFFF02, 0000FF02]
test_vsubsws_32_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FBFBFBFD, FBFBFBFD, FBFBFBFD, FBFBFBFD]
test_vsubsws_33_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [F8F8F8FA, F8F8F8FA, F8F8F8FA, F8F8F8FA]
test_vsubsws_34_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [F7F7F7F9, F7F7F7F9, F7F7F7F9, F7F7F7F9]
test_vsubsws_35_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [EDEDEDEF, EDEDEDEF, EDEDEDEF, EDEDEDEF]
test_vsubsws_36_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [EDCBA989, 789ABCE0, EEDDCCBD, AA998879]
test_vsubsws_37_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [C0800001, C0400001, C0733334, C00CCCCE]
test_vsubsws_38_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [BEE00001, 3EE00001, BE900001, 3E900001]
test_vsubsws_39_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [807FFDFE, FBFAF9FA, 807FF5F6, F3F2F1F2]
test_vsubsws_40_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FF7EFF1, 7F710001, 80000002, 70000002]
test_vsubsws_41_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [40800001, 40400001, 40733334, 400CCCCE]
test_vsubsws_42_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [3EE00001, BE600001, 3E600001, BE100001]
test_vsubsws_43_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [32323234, 32323234, 32323234, FBFEFDFE]
test_vsubsws_44_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [07060506, 03020102, FFFEFDFE, FBFAF9FA]
test_vsubsws_45_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [01010103, 01010103, 01010103, 01010103]
test_vsubsws_46_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00030004, 00010002, 00000000, FFFDFFFE]
test_vsubsws_47_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00020083, FFFDFF80, 00030084, FFFCFF7F]
test_vsubsws_48_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [0000FF00, 8F8F0002, 00000002, 00000001]
test_vsubsws_49_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [00000081, FFFFFF82, 00010082, FFFEFF81]
test_vsubsws_50_GEN:
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00000002, 00000002, 00000002, 00000002]
test_vsubsws_51_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
test_vsubsws_52_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [0000FFFE, FFFEFFFF, FFFFFFFF, FFFEFFFF]
test_vsubsws_53_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFFFDFC, FBF9F9F9, F7F6F5F5, F3F1F1F1]
test_vsubsws_54_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFF3FFF2, FFF1FFF3, FFF2FFF3, FFF1FFF3]
test_vsubsws_55_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFEFDDCC, BBA99989, 77665545, 33211101]
test_vsubsws_56_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FF0100FF, FFFE0100, 00FFFF01, FFFFFF01]
test_vsubsws_57_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FBFCFBFB, FBFAFBFC, FBFBFBFC, FBFAFBFC]
test_vsubsws_58_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [F8F9F8F8, F8F7F8F9, F8F8F8F9, F8F7F8F9]
test_vsubsws_59_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [F7F8F7F7, F7F6F7F8, F7F7F7F8, F7F6F7F8]
test_vsubsws_60_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [EDEEEDED, EDECEDEE, EDEDEDEE, EDECEDEE]
test_vsubsws_61_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [EDCCA987, 7899BCDF, EEDDCCBC, AA988878]
test_vsubsws_62_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [C080FFFF, C03F0000, C0733333, C00BCCCD]
test_vsubsws_63_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [BEE0FFFF, 3EDF0000, BE900000, 3E8F0000]
test_vsubsws_64_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [8080FDFC, FBF9F9F9, 807FF5F5, F3F1F1F1]
test_vsubsws_65_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FF8EFEF, 7F700000, 80000001, 6FFF0001]
test_vsubsws_66_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [4080FFFF, 403F0000, 40733333, 400BCCCD]
test_vsubsws_67_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [3EE0FFFF, BE5F0000, 3E600000, BE0F0000]
test_vsubsws_68_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [32333232, 32313233, 32323233, FBFDFDFD]
test_vsubsws_69_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [07070504, 03010101, FFFEFDFD, FBF9F9F9]
test_vsubsws_70_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [01020101, 01000102, 01010102, 01000102]
test_vsubsws_71_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00040002, 00000001, FFFFFFFF, FFFCFFFD]
test_vsubsws_72_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00030081, FFFCFF7F, 00030083, FFFBFF7E]
test_vsubsws_73_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [0001FEFE, 8F8E0001, 00000001, FFFF0000]
test_vsubsws_74_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [0001007F, FFFEFF81, 00010081, FFFDFF80]
test_vsubsws_75_GEN:
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00010000, FFFF0001, 00000001, FFFF0001]
test_vsubsws_76_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_vsubsws_77_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [00010202, 04050606, 08090A0A, 0C0D0E0E]
test_vsubsws_78_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [00000204, 04060607, 08090A0B, 0C0E0E0F]
test_vsubsws_79_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFF401F6, 03F805FA, 07FC09FE, 0C000E02]
test_vsubsws_80_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFEFDFD0, BFAF9F90, 7F6F5F50, 3F2F1F10]
test_vsubsws_81_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FF010303, 04040707, 0909090C, 0C0E0D10]
test_vsubsws_82_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FBFCFDFF, 00010203, 04050607, 08090A0B]
test_vsubsws_83_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [F8F9FAFC, FCFDFF00, 01020304, 05060708]
test_vsubsws_84_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [F7F8F9FB, FBFCFDFF, 00010203, 04050607]
test_vsubsws_85_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [EDEEEFF1, F1F2F3F5, F5F6F7F9, F9FAFBFD]
test_vsubsws_86_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [EDCCAB8B, 7C9FC2E6, F6E6D6C7, B6A69687]
test_vsubsws_87_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [C0810203, C4450607, C87C3D3E, CC19DADC]
test_vsubsws_88_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [BEE10203, 42E50607, C6990A0B, 4A9D0E0F]
test_vsubsws_89_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [80810000, 00000000, 88890000, 00000000]
test_vsubsws_90_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FF8F1F3, 7FFFFFFF, 88090A0C, 7C0D0E10]
test_vsubsws_91_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [40810203, 44450607, 487C3D3E, 4C19DADC]
test_vsubsws_92_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [3EE10203, C2650607, 46690A0B, CA1D0E0F]
test_vsubsws_93_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [32333436, 3637383A, 3A3B3C3E, 080C0C0C]
test_vsubsws_94_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [07070708, 07070708, 08080808, 08080808]
test_vsubsws_95_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [01020305, 05060709, 090A0B0D, 0D0E0F11]
test_vsubsws_96_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00040206, 04060608, 08090A0A, 0C0B0E0C]
test_vsubsws_97_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00030285, 04030586, 080C0A8E, 0C0A0D8D]
test_vsubsws_98_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [00020102, 93940608, 08090A0C, 0C0D0E0F]
test_vsubsws_99_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [00010283, 04050588, 080A0A8C, 0C0C0D8F]
test_vsubsws_100_GEN:
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00010204, 04050608, 08090A0C, 0C0D0E10]
test_vsubsws_101_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
test_vsubsws_102_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [000D000C, 000D000C, 000D000C, 000D000C]
test_vsubsws_103_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [000C000E, 000E000D, 000D000D, 000E000D]
test_vsubsws_104_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [000BFE0A, FC07FA06, F803F602, F3FFF1FE]
test_vsubsws_105_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFFBDDDA, BBB79996, 77735552, 332F110E]
test_vsubsws_106_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FF0D010D, 000C010D, 010CFF0E, 000DFF0E]
test_vsubsws_107_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FC08FC09, FC08FC09, FC08FC09, FC08FC09]
test_vsubsws_108_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [F905F906, F905F906, F905F906, F905F906]
test_vsubsws_109_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [F804F805, F804F805, F804F805, F804F805]
test_vsubsws_110_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [EDFAEDFB, EDFAEDFB, EDFAEDFB, EDFAEDFB]
test_vsubsws_111_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [EDD8A995, 78A7BCEC, EEEACCC9, AAA68885]
test_vsubsws_112_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [C08D000D, C04D000D, C0803340, C019CCDA]
test_vsubsws_113_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [BEED000D, 3EED000D, BE9D000D, 3E9D000D]
test_vsubsws_114_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [808CFE0A, FC07FA06, 808CF602, F3FFF1FE]
test_vsubsws_115_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FFFFFFF, 7F7E000D, 800D000E, 700D000E]
test_vsubsws_116_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [408D000D, 404D000D, 40803340, 4019CCDA]
test_vsubsws_117_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [3EED000D, BE6D000D, 3E6D000D, BE1D000D]
test_vsubsws_118_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [323F3240, 323F3240, 323F3240, FC0BFE0A]
test_vsubsws_119_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [07130512, 030F010E, 000BFE0A, FC07FA06]
test_vsubsws_120_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [010E010F, 010E010F, 010E010F, 010E010F]
test_vsubsws_121_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00100010, 000E000E, 000D000C, 000B000A]
test_vsubsws_122_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [000F008F, 000AFF8C, 00100090, 0009FF8B]
test_vsubsws_123_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [000DFF0C, 8F9C000E, 000D000E, 000D000D]
test_vsubsws_124_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [000D008D, 000CFF8E, 000E008E, 000BFF8D]
test_vsubsws_125_GEN:
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [000D000E, 000D000E, 000D000E, 000D000E]
test_vsubsws_126_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
test_vsubsws_127_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [00112232, 44556676, 8899AABA, CCDDEEFE]
test_vsubsws_128_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [00102234, 44566677, 8899AABB, CCDEEEFF]
test_vsubsws_129_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00102030, 40506070, 8090A0B0, C0D0E0F0]
test_vsubsws_130_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [00042226, 4448666A, 888CAAAE, CCD0EEF2]
test_vsubsws_131_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FF112333, 44546777, 8999A9BC, CCDEEE00]
test_vsubsws_132_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FC0D1E2F, 40516273, 8495A6B7, C8D9EAFB]
test_vsubsws_133_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [F90A1B2C, 3D4E5F70, 8192A3B4, C5D6E7F8]
test_vsubsws_134_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [F8091A2B, 3C4D5E6F, 8091A2B3, C4D5E6F7]
test_vsubsws_135_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [EDFF1021, 32435465, 80000000, BACBDCED]
test_vsubsws_136_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [EDDCCBBB, 7FFFFFFF, 80000000, 80000000]
test_vsubsws_137_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [C0912233, 04956677, 80000000, 8CEABBCC]
test_vsubsws_138_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [BEF12233, 7FFFFFFF, 80000000, 0B6DEEFF]
test_vsubsws_139_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [80912030, 40506070, 80000000, C0D0E0F0]
test_vsubsws_140_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 80000000, 3CDDEF00]
test_vsubsws_141_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [40912233, 7FFFFFFF, C90CDDEE, 0CEABBCC]
test_vsubsws_142_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [3EF12233, 02B56677, C6F9AABB, 8AEDEEFF]
test_vsubsws_143_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [32435466, 768798AA, BACBDCEE, C8DCECFC]
test_vsubsws_144_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [07172738, 47576778, 8898A8B8, C8D8E8F8]
test_vsubsws_145_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [01122335, 45566779, 899AABBD, CDDEF001]
test_vsubsws_146_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00142236, 44566678, 8899AABA, CCDBEEFC]
test_vsubsws_147_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [001322B5, 445365F6, 889CAB3E, CCDAEE7D]
test_vsubsws_148_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [00122132, D3E46678, 8899AABC, CCDDEEFF]
test_vsubsws_149_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [001122B3, 445565F8, 889AAB3C, CCDCEE7F]
test_vsubsws_150_GEN:
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00112234, 44556678, 8899AABC, CCDDEF00]
test_vsubsws_151_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
test_vsubsws_152_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [00FFFEFF, 0000FEFF, FF0000FE, FFFF00FE]
test_vsubsws_153_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [00FEFF01, 0001FF00, FF0000FF, 000000FF]
test_vsubsws_154_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [00FEFCFD, FBFBF8F9, F6F6F6F4, F3F1F2F0]
test_vsubsws_155_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [00F2FEF3, FFF3FEF3, FEF300F2, FFF200F2]
test_vsubsws_156_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [00EEDCCD, BBAB9889, 76665644, 33211200]
test_vsubsws_157_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FCFBFAFC, FBFCFAFC, FAFBFCFB, FBFAFCFB]
test_vsubsws_158_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [F9F8F7F9, F8F9F7F9, F7F8F9F8, F8F7F9F8]
test_vsubsws_159_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [F8F7F6F8, F7F8F6F8, F6F7F8F7, F7F6F8F7]
test_vsubsws_160_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [EEEDECEE, EDEEECEE, ECEDEEED, EDECEEED]
test_vsubsws_161_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [EECBA888, 789BBBDF, EDDDCDBB, AA988977]
test_vsubsws_162_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [C17FFF00, C040FF00, BF733432, C00BCDCC]
test_vsubsws_163_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [BFDFFF00, 3EE0FF00, BD9000FF, 3E8F00FF]
test_vsubsws_164_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [817FFCFD, FBFBF8F9, 80000000, F3F1F2F0]
test_vsubsws_165_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FFFFFFF, 7F71FF00, 80000000, 6FFF0100]
test_vsubsws_166_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [417FFF00, 4040FF00, 3F733432, 400BCDCC]
test_vsubsws_167_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [3FDFFF00, BE60FF00, 3D6000FF, BE0F00FF]
test_vsubsws_168_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [33323133, 32333133, 31323332, FBFDFEFC]
test_vsubsws_169_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [08060405, 03030001, FEFEFEFC, FBF9FAF8]
test_vsubsws_170_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [02010002, 01020002, 00010201, 01000201]
test_vsubsws_171_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [0102FF03, 0001FF01, FF0000FE, FFFD00FC]
test_vsubsws_172_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [0101FF82, FFFEFE7F, FF030182, FFFC007D]
test_vsubsws_173_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [0100FDFF, 8F8FFF01, FF000100, FFFF00FF]
test_vsubsws_174_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [00FFFF80, 0000FE81, FF010180, FFFE007F]
test_vsubsws_175_GEN:
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [00FFFF01, 0000FF01, FF000100, FFFF0100]
test_vsubsws_176_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
test_vsubsws_177_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [04040403, 04040403, 04040403, 04040403]
test_vsubsws_178_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [04030405, 04050404, 04040404, 04050404]
test_vsubsws_179_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [04030201, FFFEFDFD, FBFAF9F9, F7F6F5F5]
test_vsubsws_180_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [03F703F7, 03F703F7, 03F703F7, 03F703F7]
test_vsubsws_181_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [03F2E1D1, BFAE9D8D, 7B6A5949, 37261505]
test_vsubsws_182_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [03040504, 04030504, 05040305, 04050305]
test_vsubsws_183_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [FCFCFCFD, FCFCFCFD, FCFCFCFD, FCFCFCFD]
test_vsubsws_184_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FBFBFBFC, FBFBFBFC, FBFBFBFC, FBFBFBFC]
test_vsubsws_185_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [F1F1F1F2, F1F1F1F2, F1F1F1F2, F1F1F1F2]
test_vsubsws_186_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [F1CFAD8C, 7C9EC0E3, F2E1D0C0, AE9D8C7C]
test_vsubsws_187_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [C4840404, C4440404, C4773737, C410D0D1]
test_vsubsws_188_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [C2E40404, 42E40404, C2940404, 42940404]
test_vsubsws_189_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [84840201, FFFEFDFD, 8483F9F9, F7F6F5F5]
test_vsubsws_190_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 84040405, 74040405]
test_vsubsws_191_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [44840404, 44440404, 44773737, 4410D0D1]
test_vsubsws_192_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [42E40404, C2640404, 42640404, C2140404]
test_vsubsws_193_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [36363637, 36363637, 36363637, 00030201]
test_vsubsws_194_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [0B0A0909, 07060505, 04030201, FFFEFDFD]
test_vsubsws_195_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [05050506, 05050506, 05050506, 05050506]
test_vsubsws_196_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [04070407, 04050405, 04040403, 04020401]
test_vsubsws_197_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [04060486, 04020383, 04070487, 04010382]
test_vsubsws_198_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [04050303, 93930405, 04040405, 04040404]
test_vsubsws_199_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [04040484, 04040385, 04050485, 04030384]
test_vsubsws_200_GEN:
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [04040405, 04040405, 04040405, 04040405]
test_vsubsws_201_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707]
test_vsubsws_202_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [07070706, 07070706, 07070706, 07070706]
test_vsubsws_203_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [07060708, 07080707, 07070707, 07080707]
test_vsubsws_204_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [07060504, 03020100, FEFDFCFC, FAF9F8F8]
test_vsubsws_205_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [06FA06FA, 06FA06FA, 06FA06FA, 06FA06FA]
test_vsubsws_206_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [06F5E4D4, C2B1A090, 7E6D5C4C, 3A291808]
test_vsubsws_207_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [06070807, 07060807, 08070608, 07080608]
test_vsubsws_208_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [03030303, 03030303, 03030303, 03030303]
test_vsubsws_209_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [FEFEFEFF, FEFEFEFF, FEFEFEFF, FEFEFEFF]
test_vsubsws_210_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [F4F4F4F5, F4F4F4F5, F4F4F4F5, F4F4F4F5]
test_vsubsws_211_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [F4D2B08F, 7FA1C3E6, F5E4D3C3, B1A08F7F]
test_vsubsws_212_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [C7870707, C7470707, C77A3A3A, C713D3D4]
test_vsubsws_213_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [C5E70707, 45E70707, C5970707, 45970707]
test_vsubsws_214_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [87870504, 03020100, 8786FCFC, FAF9F8F8]
test_vsubsws_215_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 87070708, 77070708]
test_vsubsws_216_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [47870707, 47470707, 477A3A3A, 4713D3D4]
test_vsubsws_217_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [45E70707, C5670707, 45670707, C5170707]
test_vsubsws_218_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [3939393A, 3939393A, 3939393A, 03060504]
test_vsubsws_219_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [0E0D0C0C, 0A090808, 07060504, 03020100]
test_vsubsws_220_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [08080809, 08080809, 08080809, 08080809]
test_vsubsws_221_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [070A070A, 07080708, 07070706, 07050704]
test_vsubsws_222_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [07090789, 07050686, 070A078A, 07040685]
test_vsubsws_223_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [07080606, 96960708, 07070708, 07070707]
test_vsubsws_224_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [07070787, 07070688, 07080788, 07060687]
test_vsubsws_225_GEN:
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [07070708, 07070708, 07070708, 07070708]
test_vsubsws_226_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
test_vsubsws_227_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [08080807, 08080807, 08080807, 08080807]
test_vsubsws_228_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [08070809, 08090808, 08080808, 08090808]
test_vsubsws_229_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [08070605, 04030201, FFFEFDFD, FBFAF9F9]
test_vsubsws_230_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [07FB07FB, 07FB07FB, 07FB07FB, 07FB07FB]
test_vsubsws_231_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [07F6E5D5, C3B2A191, 7F6E5D4D, 3B2A1909]
test_vsubsws_232_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [07080908, 08070908, 09080709, 08090709]
test_vsubsws_233_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
test_vsubsws_234_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
test_vsubsws_235_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [F5F5F5F6, F5F5F5F6, F5F5F5F6, F5F5F5F6]
test_vsubsws_236_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [F5D3B190, 7FFFFFFF, F6E5D4C4, B2A19080]
test_vsubsws_237_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [C8880808, C8480808, C87B3B3B, C814D4D5]
test_vsubsws_238_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [C6E80808, 46E80808, C6980808, 46980808]
test_vsubsws_239_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [88880605, 04030201, 8887FDFD, FBFAF9F9]
test_vsubsws_240_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 88080809, 78080809]
test_vsubsws_241_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [48880808, 48480808, 487B3B3B, 4814D4D5]
test_vsubsws_242_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [46E80808, C6680808, 46680808, C6180808]
test_vsubsws_243_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [3A3A3A3B, 3A3A3A3B, 3A3A3A3B, 04070605]
test_vsubsws_244_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [0F0E0D0D, 0B0A0909, 08070605, 04030201]
test_vsubsws_245_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [0909090A, 0909090A, 0909090A, 0909090A]
test_vsubsws_246_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [080B080B, 08090809, 08080807, 08060805]
test_vsubsws_247_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [080A088A, 08060787, 080B088B, 08050786]
test_vsubsws_248_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [08090707, 97970809, 08080809, 08080808]
test_vsubsws_249_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [08080888, 08080789, 08090889, 08070788]
test_vsubsws_250_GEN:
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [08080809, 08080809, 08080809, 08080809]
test_vsubsws_251_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212]
test_vsubsws_252_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [12121211, 12121211, 12121211, 12121211]
test_vsubsws_253_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [12111213, 12131212, 12121212, 12131212]
test_vsubsws_254_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [1211100F, 0E0D0C0B, 0A090807, 06050403]
test_vsubsws_255_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [12051205, 12051205, 12051205, 12051205]
test_vsubsws_256_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [1200EFDF, CDBCAB9B, 7FFFFFFF, 45342313]
test_vsubsws_257_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [11121312, 12111312, 13121113, 12131113]
test_vsubsws_258_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [0E0E0E0E, 0E0E0E0E, 0E0E0E0E, 0E0E0E0E]
test_vsubsws_259_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [0B0B0B0B, 0B0B0B0B, 0B0B0B0B, 0B0B0B0B]
test_vsubsws_260_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [0A0A0A0A, 0A0A0A0A, 0A0A0A0A, 0A0A0A0A]
test_vsubsws_261_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [FFDDBB9A, 7FFFFFFF, 00EFDECE, BCAB9A8A]
test_vsubsws_262_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [D2921212, D2521212, D2854545, D21EDEDF]
test_vsubsws_263_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [D0F21212, 50F21212, D0A21212, 50A21212]
test_vsubsws_264_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [9292100F, 0E0D0C0B, 92920807, 06050403]
test_vsubsws_265_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 92121213, 7FFFFFFF]
test_vsubsws_266_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [52921212, 52521212, 52854545, 521EDEDF]
test_vsubsws_267_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [50F21212, D0721212, 50721212, D0221212]
test_vsubsws_268_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [44444445, 44444445, 44444445, 0E11100F]
test_vsubsws_269_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [19181717, 15141313, 1211100F, 0E0D0C0B]
test_vsubsws_270_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [13131314, 13131314, 13131314, 13131314]
test_vsubsws_271_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [12151215, 12131213, 12121211, 1210120F]
test_vsubsws_272_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [12141294, 12101191, 12151295, 120F1190]
test_vsubsws_273_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [12131111, A1A11213, 12121213, 12121212]
test_vsubsws_274_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [12121292, 12121193, 12131293, 12111192]
test_vsubsws_275_GEN:
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [12121213, 12121213, 12121213, 12121213]
test_vsubsws_276_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788]
test_vsubsws_277_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [12345677, 87654320, 11223343, 55667787]
test_vsubsws_278_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [12335679, 87664321, 11223344, 55677788]
test_vsubsws_279_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [12335475, 83603D1A, 09192939, 49596979]
test_vsubsws_280_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [1227566B, 87584314, 11153337, 5559777B]
test_vsubsws_281_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [12233445, 80000000, 7FFFFFFF, 7FFFFFFF]
test_vsubsws_282_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [11345778, 87644421, 12223245, 55677689]
test_vsubsws_283_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [0E305274, 83613F1D, 0D1E2F40, 51627384]
test_vsubsws_284_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [0B2D4F71, 805E3C1A, 0A1B2C3D, 4E5F7081]
test_vsubsws_285_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [0A2C4E70, 80000000, 091A2B3C, 4D5E6F80]
test_vsubsws_286_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [00224466, 80000000, FF102132, 43546576]
test_vsubsws_287_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [D2B45678, 80000000, D1956677, 15734455]
test_vsubsws_288_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [D1145678, C6454321, CFB23344, 7FFFFFFF]
test_vsubsws_289_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [92B45475, 83603D1A, 91A22939, 49596979]
test_vsubsws_290_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FFFFFFF, 06D64321, 91223345, 7FFFFFFF]
test_vsubsws_291_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [52B45678, C7A54321, 51956677, 7FFFFFFF]
test_vsubsws_292_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [51145678, 80000000, 4F823344, 13767788]
test_vsubsws_293_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [446688AB, B9977554, 43546577, 51657585]
test_vsubsws_294_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [193A5B7D, 8A674422, 11213141, 51617181]
test_vsubsws_295_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [1335577A, 88664423, 12233446, 5667788A]
test_vsubsws_296_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [1237567B, 87664322, 11223343, 55647785]
test_vsubsws_297_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [123656FA, 876342A0, 112533C7, 55637706]
test_vsubsws_298_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [12355577, 80000000, 11223345, 55667788]
test_vsubsws_299_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [123456F8, 876542A2, 112333C5, 55657708]
test_vsubsws_300_GEN:
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [12345679, 87654322, 11223345, 55667789]
test_vsubsws_301_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
test_vsubsws_302_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [3F7FFFFF, 3FBFFFFF, 3F8CCCCC, 3FF33332]
test_vsubsws_303_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [3F7F0001, 3FC10000, 3F8CCCCD, 3FF43333]
test_vsubsws_304_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [3F7EFDFD, 3BBAF9F9, 3783C2C2, 33E62524]
test_vsubsws_305_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [3F72FFF3, 3FB2FFF3, 3F7FCCC0, 3FE63326]
test_vsubsws_306_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [3F6EDDCD, FB6A9989, 7FFFFFFF, 73154434]
test_vsubsws_307_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [3E800100, 3FBF0100, 408CCBCE, 3FF43234]
test_vsubsws_308_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [3B7BFBFC, 3BBBFBFC, 3B88C8C9, 3BEF2F2F]
test_vsubsws_309_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [3878F8F9, 38B8F8F9, 3885C5C6, 38EC2C2C]
test_vsubsws_310_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [3777F7F8, 37B7F7F8, 3784C4C5, 37EB2B2B]
test_vsubsws_311_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [2D6DEDEE, 2DADEDEE, 2D7ABABB, 2DE12121]
test_vsubsws_312_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [2D4BA988, 7FFFFFFF, 2E6A9989, EA8CBBAB]
test_vsubsws_313_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [FE600000, 7EA00000, FE1CCCCD, 7E833333]
test_vsubsws_314_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [BFFFFDFD, 3BBAF9F9, C00CC2C2, 33E62524]
test_vsubsws_315_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, BF8CCCCE, 7FFFFFFF]
test_vsubsws_316_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
test_vsubsws_317_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [7E600000, FE200000, 7DECCCCD, FE033333]
test_vsubsws_318_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [71B23233, 71F23233, 71BEFF00, 3BF23130]
test_vsubsws_319_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [46860505, 42C20101, 3F8BCACA, 3BEE2D2C]
test_vsubsws_320_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [40810102, 40C10102, 408DCDCF, 40F43435]
test_vsubsws_321_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [3F830003, 3FC10001, 3F8CCCCC, 3FF13330]
test_vsubsws_322_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [3F820082, 3FBDFF7F, 3F8FCD50, 3FF032B1]
test_vsubsws_323_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [3F80FEFF, CF4F0001, 3F8CCCCE, 3FF33333]
test_vsubsws_324_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [3F800080, 3FBFFF81, 3F8DCD4E, 3FF232B3]
test_vsubsws_325_GEN:
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [3F800001, 3FC00001, 3F8CCCCE, 3FF33334]
test_vsubsws_326_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
test_vsubsws_327_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [411FFFFF, C11FFFFF, 416FFFFF, C16FFFFF]
test_vsubsws_328_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [411F0001, C1210000, 41700000, C1710000]
test_vsubsws_329_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [411EFDFD, BD1AF9F9, 3966F5F5, B562F1F1]
test_vsubsws_330_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [4112FFF3, C112FFF3, 4162FFF3, C162FFF3]
test_vsubsws_331_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [410EDDCD, 80000000, 7FFFFFFF, F4921101]
test_vsubsws_332_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [40200100, C11F0100, 426FFF01, C170FF01]
test_vsubsws_333_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [3D1BFBFC, BD1BFBFC, 3D6BFBFC, BD6BFBFC]
test_vsubsws_334_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [3A18F8F9, BA18F8F9, 3A68F8F9, BA68F8F9]
test_vsubsws_335_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [3917F7F8, B917F7F8, 3967F7F8, B967F7F8]
test_vsubsws_336_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [2F0DEDEE, AF0DEDEE, 2F5DEDEE, AF5DEDEE]
test_vsubsws_337_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [2EEBA988, 39BABCDF, 304DCCBC, 80000000]
test_vsubsws_338_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [01A00000, 81600000, 01E33333, 817CCCCD]
test_vsubsws_339_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [C19FFDFD, BD1AF9F9, C1EFF5F5, B562F1F1]
test_vsubsws_340_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FFFFFFF, 40910000, C1700001, 31700001]
test_vsubsws_341_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [7FFFFFFF, 01600000, 7FFFFFFF, 017CCCCD]
test_vsubsws_342_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [7FFFFFFF, 80000000, 7FD00000, 80000000]
test_vsubsws_343_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [73523233, F3523233, 73A23233, BD6EFDFD]
test_vsubsws_344_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [48260505, C4220101, 416EFDFD, BD6AF9F9]
test_vsubsws_345_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [42210102, C2210102, 42710102, C2710102]
test_vsubsws_346_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [41230003, C1210001, 416FFFFF, C16DFFFD]
test_vsubsws_347_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [41220082, C11DFF7F, 41730083, C16CFF7E]
test_vsubsws_348_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [4120FEFF, 80000000, 41700001, C1700000]
test_vsubsws_349_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [41200080, C11FFF81, 41710081, C16EFF80]
test_vsubsws_350_GEN:
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [41200001, C1200001, 41700001, C1700001]
test_vsubsws_351_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
test_vsubsws_352_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [7F800202, 04050606, 7F800A0A, 0C0D0E0E]
test_vsubsws_353_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [7F7F0204, 04060607, 7F800A0B, 0C0E0E0F]
test_vsubsws_354_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [7F7F0000, 00000000, 77770000, 00000000]
test_vsubsws_355_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [7F7301F6, 03F805FA, 7F7309FE, 0C000E02]
test_vsubsws_356_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [7F6EDFD0, BFAF9F90, 7FFFFFFF, 3F2F1F10]
test_vsubsws_357_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [7E800303, 04040707, 7FFFFFFF, 0C0E0D10]
test_vsubsws_358_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [7B7BFDFF, 00010203, 7B7C0607, 08090A0B]
test_vsubsws_359_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [7878FAFC, FCFDFF00, 78790304, 05060708]
test_vsubsws_360_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [7777F9FB, FBFCFDFF, 77780203, 04050607]
test_vsubsws_361_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [6D6DEFF1, F1F2F3F5, 6D6DF7F9, F9FAFBFD]
test_vsubsws_362_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [6D4BAB8B, 7C9FC2E6, 6E5DD6C7, B6A69687]
test_vsubsws_363_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [40000203, C4450607, 3FF33D3E, CC19DADC]
test_vsubsws_364_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [3E600203, 42E50607, 3E100A0B, 4A9D0E0F]
test_vsubsws_365_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, FF800A0C, 7C0D0E10]
test_vsubsws_366_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [7FFFFFFF, 44450607, 7FFFFFFF, 4C19DADC]
test_vsubsws_367_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [7FFFFFFF, C2650607, 7FFFFFFF, CA1D0E0F]
test_vsubsws_368_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [7FFFFFFF, 3637383A, 7FFFFFFF, 080C0C0C]
test_vsubsws_369_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [7FFFFFFF, 07070708, 7F7F0808, 08080808]
test_vsubsws_370_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [7FFFFFFF, 05060709, 7FFFFFFF, 0D0E0F11]
test_vsubsws_371_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [7F830206, 04060608, 7F800A0A, 0C0B0E0C]
test_vsubsws_372_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [7F820285, 04030586, 7F830A8E, 0C0A0D8D]
test_vsubsws_373_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [7F810102, 93940608, 7F800A0C, 0C0D0E0F]
test_vsubsws_374_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [7F800283, 04050588, 7F810A8C, 0C0C0D8F]
test_vsubsws_375_GEN:
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [7F800204, 04050608, 7F800A0C, 0C0D0E10]
test_vsubsws_376_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
test_vsubsws_377_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [8008100F, 808EFFFF, 7FFFFFFE, 8FFFFFFE]
test_vsubsws_378_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [80071011, 80900000, 7FFFFFFF, 9000FFFF]
test_vsubsws_379_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [80070E0D, 80000000, 77F6F5F4, 83F2F1F0]
test_vsubsws_380_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [80000000, 8081FFF3, 7FF2FFF2, 8FF2FFF2]
test_vsubsws_381_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [80000000, 80000000, 7FFFFFFF, C3221100]
test_vsubsws_382_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [80000000, 808E0100, 7FFFFFFF, 9000FF00]
test_vsubsws_383_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [80000000, 80000000, 7BFBFBFB, 8BFBFBFB]
test_vsubsws_384_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [80000000, 80000000, 78F8F8F8, 88F8F8F8]
test_vsubsws_385_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [80000000, 80000000, 77F7F7F7, 87F7F7F7]
test_vsubsws_386_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [80000000, 80000000, 6DEDEDED, 80000000]
test_vsubsws_387_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [80000000, F929BCDF, 6EDDCCBB, 80000000]
test_vsubsws_388_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [80000000, 80000000, 40733332, 80000000]
test_vsubsws_389_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [80000000, BF6F0000, 3E8FFFFF, CE8FFFFF]
test_vsubsws_390_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [80000000, 80000000, 007FF5F4, 83F2F1F0]
test_vsubsws_391_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [C0881010, C0CF0000, 7FFFFFFF, D00CCCCC]
test_vsubsws_392_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [BEE81010, 80000000, 7FFFFFFF, 80000000]
test_vsubsws_393_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [B23A4243, B2C13233, 7FFFFFFF, 8BFEFDFC]
test_vsubsws_394_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [870E1515, 83910101, 7FFEFDFC, 8BFAF9F8]
test_vsubsws_395_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [81091112, 81900102, 7FFFFFFF, 91010101]
test_vsubsws_396_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [800B1013, 80900001, 7FFFFFFE, 8FFDFFFC]
test_vsubsws_397_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [800A1092, 808CFF7F, 7FFFFFFF, 8FFCFF7D]
test_vsubsws_398_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [80090F0F, 80000000, 7FFFFFFF, 8FFFFFFF]
test_vsubsws_399_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [80081090, 808EFF81, 7FFFFFFF, 8FFEFF7F]
test_vsubsws_400_GEN:
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [80081011, 808F0001, 7FFFFFFF, 90000000]
test_vsubsws_401_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333]
test_vsubsws_402_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [BF7FFFFF, BFBFFFFF, BF8CCCCC, BFF33332]
test_vsubsws_403_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [BF7F0001, BFC10000, BF8CCCCD, BFF43333]
test_vsubsws_404_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [BF7EFDFD, BBBAF9F9, B783C2C2, B3E62524]
test_vsubsws_405_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [BF72FFF3, BFB2FFF3, BF7FCCC0, BFE63326]
test_vsubsws_406_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [BF6EDDCD, 80000000, 36F32212, F3154434]
test_vsubsws_407_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [BE800100, BFBF0100, C08CCBCE, BFF43234]
test_vsubsws_408_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [BB7BFBFC, BBBBFBFC, BB88C8C9, BBEF2F2F]
test_vsubsws_409_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [B878F8F9, B8B8F8F9, B885C5C6, B8EC2C2C]
test_vsubsws_410_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [B777F7F8, B7B7F7F8, B784C4C5, B7EB2B2B]
test_vsubsws_411_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [AD6DEDEE, ADADEDEE, AD7ABABB, ADE12121]
test_vsubsws_412_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [AD4BA988, 385ABCDF, AE6A9989, 80000000]
test_vsubsws_413_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
test_vsubsws_414_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [80000000, FEA00000, 80000000, FE833333]
test_vsubsws_415_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [80000000, BBBAF9F9, 80000000, B3E62524]
test_vsubsws_416_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [3F77EFF0, 3F310000, 80000000, 2FF33334]
test_vsubsws_417_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [FE600000, 80000000, FDECCCCD, 80000000]
test_vsubsws_418_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [F1B23233, F1F23233, F1BEFF00, BBF23130]
test_vsubsws_419_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [C6860505, C2C20101, BF8BCACA, BBEE2D2C]
test_vsubsws_420_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [C0810102, C0C10102, C08DCDCF, C0F43435]
test_vsubsws_421_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [BF830003, BFC10001, BF8CCCCC, BFF13330]
test_vsubsws_422_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [BF820082, BFBDFF7F, BF8FCD50, BFF032B1]
test_vsubsws_423_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [BF80FEFF, 80000000, BF8CCCCE, BFF33333]
test_vsubsws_424_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [BF800080, BFBFFF81, BF8DCD4E, BFF232B3]
test_vsubsws_425_GEN:
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [BF800001, BFC00001, BF8CCCCE, BFF33334]
test_vsubsws_426_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000]
test_vsubsws_427_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [C11FFFFF, 419FFFFF, C19FFFFF, 41EFFFFF]
test_vsubsws_428_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [C11F0001, 41A10000, C1A00000, 41F10000]
test_vsubsws_429_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [C11EFDFD, 3D9AF9F9, B996F5F5, 35E2F1F1]
test_vsubsws_430_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [C112FFF3, 4192FFF3, C192FFF3, 41E2FFF3]
test_vsubsws_431_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [C10EDDCD, FD4A9989, 39065545, 75121101]
test_vsubsws_432_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [C0200100, 419F0100, C29FFF01, 41F0FF01]
test_vsubsws_433_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [BD1BFBFC, 3D9BFBFC, BD9BFBFC, 3DEBFBFC]
test_vsubsws_434_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [BA18F8F9, 3A98F8F9, BA98F8F9, 3AE8F8F9]
test_vsubsws_435_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [B917F7F8, 3997F7F8, B997F7F8, 39E7F7F8]
test_vsubsws_436_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [AF0DEDEE, 2F8DEDEE, AF8DEDEE, 2FDDEDEE]
test_vsubsws_437_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [AEEBA988, 7FFFFFFF, B07DCCBC, EC898878]
test_vsubsws_438_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [81A00000, 01E00000, 82133333, 01FCCCCD]
test_vsubsws_439_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [80000000, 7FFFFFFF, 80300000, 7FFFFFFF]
test_vsubsws_440_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [80000000, 3D9AF9F9, 80000000, 35E2F1F1]
test_vsubsws_441_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [4117EFF0, 7FFFFFFF, 80000000, 7FFFFFFF]
test_vsubsws_442_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [01A00000, 7FFFFFFF, 02133333, 7FFFFFFF]
test_vsubsws_443_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [F3523233, 73D23233, F3D23233, 3DEEFDFD]
test_vsubsws_444_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [C8260505, 44A20101, C19EFDFD, 3DEAF9F9]
test_vsubsws_445_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [C2210102, 42A10102, C2A10102, 42F10102]
test_vsubsws_446_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [C1230003, 41A10001, C19FFFFF, 41EDFFFD]
test_vsubsws_447_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [C1220082, 419DFF7F, C1A30083, 41ECFF7E]
test_vsubsws_448_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [C120FEFF, D12F0001, C1A00001, 41F00000]
test_vsubsws_449_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [C1200080, 419FFF81, C1A10081, 41EEFF80]
test_vsubsws_450_GEN:
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [C1200001, 41A00001, C1A00001, 41F00001]
test_vsubsws_451_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
test_vsubsws_452_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [CDCDCDCC, CDCDCDCC, CDCDCDCC, 04010202]
test_vsubsws_453_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [CDCCCDCE, CDCECDCD, CDCDCDCD, 04020203]
test_vsubsws_454_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [CDCCCBCA, C9C8C7C6, C5C4C3C2, F7F3F3F4]
test_vsubsws_455_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [CDC0CDC0, CDC0CDC0, CDC0CDC0, 03F401F6]
test_vsubsws_456_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [CDBCAB9A, 89786756, 45342312, 37231304]
test_vsubsws_457_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [CCCDCECD, CDCCCECD, CECDCCCE, 04020104]
test_vsubsws_458_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [C9C9C9C9, C9C9C9C9, C9C9C9C9, FFFCFDFF]
test_vsubsws_459_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [C6C6C6C6, C6C6C6C6, C6C6C6C6, FCF9FAFC]
test_vsubsws_460_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [C5C5C5C5, C5C5C5C5, C5C5C5C5, FBF8F9FB]
test_vsubsws_461_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [BBBBBBBB, BBBBBBBB, BBBBBBBB, F1EEEFF1]
test_vsubsws_462_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [BB997755, 46688AAC, BCAB9A89, AE9A8A7B]
test_vsubsws_463_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [8E4DCDCD, 8E0DCDCD, 8E410100, C40DCED0]
test_vsubsws_464_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [8CADCDCD, 0CADCDCD, 8C5DCDCD, 42910203]
test_vsubsws_465_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [80000000, C9C8C7C6, 80000000, F7F3F3F4]
test_vsubsws_466_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [4DC5BDBD, 4D3ECDCD, 80000000, 74010204]
test_vsubsws_467_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [0E4DCDCD, 0E0DCDCD, 0E410100, 440DCED0]
test_vsubsws_468_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [0CADCDCD, 8C2DCDCD, 0C2DCDCD, C2110203]
test_vsubsws_469_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [D4D3D2D2, D0CFCECE, CDCCCBCA, FFFBFBFC]
test_vsubsws_470_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [CECECECF, CECECECF, CECECECF, 05020305]
test_vsubsws_471_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [CDD0CDD0, CDCECDCE, CDCDCDCC, 03FF0200]
test_vsubsws_472_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [CDCFCE4F, CDCBCD4C, CDD0CE50, 03FE0181]
test_vsubsws_473_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [CDCECCCC, 80000000, CDCDCDCE, 04010203]
test_vsubsws_474_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [CDCDCE4D, CDCDCD4E, CDCECE4E, 04000183]
test_vsubsws_475_GEN:
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [CDCDCDCE, CDCDCDCE, CDCDCDCE, 04010204]
test_vsubsws_476_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
test_vsubsws_477_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [F8F9FAFA, FCFDFEFE, 00010202, 04050606]
test_vsubsws_478_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [F8F8FAFC, FCFEFEFF, 00010203, 04060607]
test_vsubsws_479_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [F8F8F8F8, F8F8F8F8, F7F7F7F8, F7F7F7F8]
test_vsubsws_480_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [F8ECFAEE, FCF0FEF2, FFF401F6, 03F805FA]
test_vsubsws_481_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [F8E8D8C8, B8A89888, 77675748, 37271708]
test_vsubsws_482_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [F7F9FBFB, FCFCFFFF, 01010104, 04060508]
test_vsubsws_483_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [F4F5F6F7, F8F9FAFB, FBFCFDFF, 00010203]
test_vsubsws_484_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [F1F2F3F4, F5F6F7F8, F8F9FAFC, FCFDFF00]
test_vsubsws_485_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F7F8F9FB, FBFCFDFF]
test_vsubsws_486_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [E6E7E8E9, EAEBECED, EDEEEFF1, F1F2F3F5]
test_vsubsws_487_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [E6C5A483, 7598BBDE, EEDECEBF, AE9E8E7F]
test_vsubsws_488_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [B979FAFB, BD3DFEFF, C0743536, C411D2D4]
test_vsubsws_489_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [B7D9FAFB, 3BDDFEFF, BE910203, 42950607]
test_vsubsws_490_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [80000000, F8F8F8F8, 8080F7F8, F7F7F7F8]
test_vsubsws_491_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [78F1EAEB, 7C6EFEFF, 80010204, 74050608]
test_vsubsws_492_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [3979FAFB, 3D3DFEFF, 40743536, 4411D2D4]
test_vsubsws_493_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [37D9FAFB, BB5DFEFF, 3E610203, C2150607]
test_vsubsws_494_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [2B2C2D2E, 2F303132, 32333436, 00040404]
test_vsubsws_495_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [F9FAFBFD, FDFF0001, 01020305, 05060709]
test_vsubsws_496_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [F8FCFAFE, FCFEFF00, 00010202, 04030604]
test_vsubsws_497_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [F8FBFB7D, FCFBFE7E, 00040286, 04020585]
test_vsubsws_498_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [F8FAF9FA, 8C8CFF00, 00010204, 04050607]
test_vsubsws_499_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [F8F9FB7B, FCFDFE80, 00020284, 04040587]
test_vsubsws_500_GEN:
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [F8F9FAFC, FCFDFF00, 00010204, 04050608]
test_vsubsws_501_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
test_vsubsws_502_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FEFEFEFD, FEFEFEFD, FEFEFEFD, FEFEFEFD]
test_vsubsws_503_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FEFDFEFF, FEFFFEFE, FEFEFEFE, FEFFFEFE]
test_vsubsws_504_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FEFDFCFB, FAF9F8F7, F6F5F4F3, F2F1F0EF]
test_vsubsws_505_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FEF1FEF1, FEF1FEF1, FEF1FEF1, FEF1FEF1]
test_vsubsws_506_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FEEDDCCB, BAA99887, 76655443, 32210FFF]
test_vsubsws_507_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FDFEFFFE, FEFDFFFE, FFFEFDFF, FEFFFDFF]
test_vsubsws_508_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FAFAFAFA, FAFAFAFA, FAFAFAFA, FAFAFAFA]
test_vsubsws_509_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [F7F7F7F7, F7F7F7F7, F7F7F7F7, F7F7F7F7]
test_vsubsws_510_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [F6F6F6F6, F6F6F6F6, F6F6F6F6, F6F6F6F6]
test_vsubsws_511_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [ECECECEC, ECECECEC, ECECECEC, ECECECEC]
test_vsubsws_512_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [ECCAA886, 7799BBDD, EDDCCBBA, A9988776]
test_vsubsws_513_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [BF7EFEFE, BF3EFEFE, BF723231, BF0BCBCB]
test_vsubsws_514_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [BDDEFEFE, 3DDEFEFE, BD8EFEFE, 3D8EFEFE]
test_vsubsws_515_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [80000000, FAF9F8F7, 80000000, F2F1F0EF]
test_vsubsws_516_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7EF6EEEE, 7E6FFEFE, 80000000, 6EFEFEFF]
test_vsubsws_517_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [3F7EFEFE, 3F3EFEFE, 3F723231, 3F0BCBCB]
test_vsubsws_518_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [3DDEFEFE, BD5EFEFE, 3D5EFEFE, BD0EFEFE]
test_vsubsws_519_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [31313131, 31313131, 31313131, FAFDFCFB]
test_vsubsws_520_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [06050403, 0200FFFF, FEFDFCFB, FAF9F8F7]
test_vsubsws_521_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [FF01FF01, FEFFFEFF, FEFEFEFD, FEFCFEFB]
test_vsubsws_522_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FF00FF80, FEFCFE7D, FF01FF81, FEFBFE7C]
test_vsubsws_523_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FEFFFDFD, 8E8DFEFF, FEFEFEFF, FEFEFEFE]
test_vsubsws_524_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FEFEFF7E, FEFEFE7F, FEFFFF7F, FEFDFE7E]
test_vsubsws_525_GEN:
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FEFEFEFF, FEFEFEFF, FEFEFEFF, FEFEFEFF]
test_vsubsws_526_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
test_vsubsws_527_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFCFFFC, FFFEFFFE, 00000000, 00020002]
test_vsubsws_528_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFBFFFE, FFFFFFFF, 00000001, 00030003]
test_vsubsws_529_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFBFDFA, FBF9F9F8, F7F6F5F6, F3F4F1F4]
test_vsubsws_530_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFEFFFF0, FFF1FFF2, FFF2FFF4, FFF4FFF6]
test_vsubsws_531_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFEBDDCA, BBA99988, 77665546, 33241104]
test_vsubsws_532_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FEFD00FD, FFFE00FF, 00FFFF02, 0002FF04]
test_vsubsws_533_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FBF8FBF9, FBFAFBFB, FBFBFBFD, FBFDFBFF]
test_vsubsws_534_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [F8F5F8F6, F8F7F8F8, F8F8F8FA, F8FAF8FC]
test_vsubsws_535_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [F7F4F7F5, F7F6F7F7, F7F7F7F9, F7F9F7FB]
test_vsubsws_536_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [EDEAEDEB, EDECEDED, EDEDEDEF, EDEFEDF1]
test_vsubsws_537_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [EDC8A985, 7899BCDE, EEDDCCBD, AA9B887B]
test_vsubsws_538_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [C07CFFFD, C03EFFFF, C0733334, C00ECCD0]
test_vsubsws_539_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [BEDCFFFD, 3EDEFFFF, BE900001, 3E920003]
test_vsubsws_540_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [807CFDFA, FBF9F9F8, 807FF5F6, F3F4F1F4]
test_vsubsws_541_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FF4EFED, 7F6FFFFF, 80000002, 70020004]
test_vsubsws_542_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [407CFFFD, 403EFFFF, 40733334, 400ECCD0]
test_vsubsws_543_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [3EDCFFFD, BE5EFFFF, 3E600001, BE120003]
test_vsubsws_544_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [322F3230, 32313232, 32323234, FC00FE00]
test_vsubsws_545_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [07030502, 03010100, FFFEFDFE, FBFCF9FC]
test_vsubsws_546_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [00FE00FF, 01000101, 01010103, 01030105]
test_vsubsws_547_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [FFFF007F, FFFCFF7E, 00030084, FFFEFF81]
test_vsubsws_548_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFDFEFC, 8F8E0000, 00000002, 00020003]
test_vsubsws_549_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFD007D, FFFEFF80, 00010082, 0000FF83]
test_vsubsws_550_GEN:
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFCFFFE, FFFF0000, 00000002, 00020004]
test_vsubsws_551_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
test_vsubsws_552_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFDFF7D, 00020080, FFFCFF7C, 00030081]
test_vsubsws_553_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFCFF7F, 00030081, FFFCFF7D, 00040082]
test_vsubsws_554_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFCFD7B, FBFCFA7A, F7F3F572, F3F5F273]
test_vsubsws_555_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFF0FF71, FFF50074, FFEFFF70, FFF60075]
test_vsubsws_556_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFECDD4B, BBAC9A0A, 776354C2, 33251183]
test_vsubsws_557_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FEFE007E, 00010181, 00FCFE7E, 0003FF83]
test_vsubsws_558_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FBF9FB7A, FBFDFC7D, FBF8FB79, FBFEFC7E]
test_vsubsws_559_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [F8F6F877, F8FAF97A, F8F5F876, F8FBF97B]
test_vsubsws_560_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [F7F5F776, F7F9F879, F7F4F775, F7FAF87A]
test_vsubsws_561_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [EDEBED6C, EDEFEE6F, EDEAED6B, EDF0EE70]
test_vsubsws_562_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [EDC9A906, 789CBD60, EEDACC39, AA9C88FA]
test_vsubsws_563_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [C07DFF7E, C0420081, C07032B0, C00FCD4F]
test_vsubsws_564_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [BEDDFF7E, 3EE20081, BE8CFF7D, 3E930082]
test_vsubsws_565_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [807DFD7B, FBFCFA7A, 807CF572, F3F5F273]
test_vsubsws_566_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FF5EF6E, 7F730081, 80000000, 70030083]
test_vsubsws_567_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [407DFF7E, 40420081, 407032B0, 400FCD4F]
test_vsubsws_568_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [3EDDFF7E, BE620081, 3E5CFF7D, BE130082]
test_vsubsws_569_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [323031B1, 323432B4, 322F31B0, FC01FE7F]
test_vsubsws_570_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [07040483, 03040182, FFFBFD7A, FBFDFA7B]
test_vsubsws_571_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [00FF0080, 01030183, 00FE007F, 01040184]
test_vsubsws_572_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [0000FF81, 00030082, FFFCFF7C, 0001007F]
test_vsubsws_573_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [FFFEFE7D, 8F910082, FFFCFF7E, 00030082]
test_vsubsws_574_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFDFFFE, 00020002, FFFDFFFE, 00020002]
test_vsubsws_575_GEN:
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFDFF7F, 00020082, FFFCFF7E, 00030083]
test_vsubsws_576_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
test_vsubsws_577_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFF0100, 7070FFFE, FFFFFFFE, FFFFFFFF]
test_vsubsws_578_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFE0102, 7071FFFF, FFFFFFFF, 00010000]
test_vsubsws_579_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFDFEFE, 6C6BF9F8, F7F6F5F4, F3F2F1F1]
test_vsubsws_580_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFF200F4, 7063FFF2, FFF2FFF2, FFF2FFF3]
test_vsubsws_581_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFEDDECE, 2C1B9988, 77665544, 33221101]
test_vsubsws_582_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FEFF0201, 707000FF, 00FFFF00, 0000FF01]
test_vsubsws_583_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FBFAFCFD, 6C6CFBFB, FBFBFBFB, FBFBFBFC]
test_vsubsws_584_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [F8F7F9FA, 6969F8F8, F8F8F8F8, F8F8F8F9]
test_vsubsws_585_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [F7F6F8F9, 6868F7F7, F7F7F7F7, F7F7F7F8]
test_vsubsws_586_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [EDECEEEF, 5E5EEDED, EDEDEDED, EDEDEDEE]
test_vsubsws_587_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [EDCAAA89, 7FFFFFFF, EEDDCCBB, AA998878]
test_vsubsws_588_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [C07F0101, 30B0FFFF, C0733332, C00CCCCD]
test_vsubsws_589_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [BEDF0101, 7FFFFFFF, BE8FFFFF, 3E900000]
test_vsubsws_590_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [807EFEFE, 6C6BF9F8, 807FF5F4, F3F2F1F1]
test_vsubsws_591_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FF6F0F1, 7FFFFFFF, 80000000, 70000001]
test_vsubsws_592_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [407F0101, 7FFFFFFF, 40733332, 400CCCCD]
test_vsubsws_593_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [3EDF0101, 2ED0FFFF, 3E5FFFFF, BE100000]
test_vsubsws_594_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [32313334, 7FFFFFFF, 32323232, FBFEFDFD]
test_vsubsws_595_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [07050606, 73730100, FFFEFDFC, FBFAF9F9]
test_vsubsws_596_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [01000203, 71720101, 01010101, 01010102]
test_vsubsws_597_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00020104, 70720000, FFFFFFFE, FFFDFFFD]
test_vsubsws_598_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00010183, 706EFF7E, 00030082, FFFCFF7E]
test_vsubsws_599_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [FFFF0181, 7070FF80, 00010080, FFFEFF80]
test_vsubsws_600_GEN:
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFF0102, 70710000, 00000000, 00000001]
test_vsubsws_601_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
test_vsubsws_602_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFFFF7F, 0000007E, FFFEFF7E, 0001007F]
test_vsubsws_603_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFEFF81, 0001007F, FFFEFF7F, 00020080]
test_vsubsws_604_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFEFD7D, FBFAFA78, F7F5F574, F3F3F271]
test_vsubsws_605_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFF2FF73, FFF30072, FFF1FF72, FFF40073]
test_vsubsws_606_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFEEDD4D, BBAA9A08, 776554C4, 33231181]
test_vsubsws_607_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FF000080, FFFF017F, 00FEFE80, 0001FF81]
test_vsubsws_608_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FBFBFB7C, FBFBFC7B, FBFAFB7B, FBFCFC7C]
test_vsubsws_609_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [F8F8F879, F8F8F978, F8F7F878, F8F9F979]
test_vsubsws_610_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [F7F7F778, F7F7F877, F7F6F777, F7F8F878]
test_vsubsws_611_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [EDEDED6E, EDEDEE6D, EDECED6D, EDEEEE6E]
test_vsubsws_612_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [EDCBA908, 789ABD5E, EEDCCC3B, AA9A88F8]
test_vsubsws_613_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [C07FFF80, C040007F, C07232B2, C00DCD4D]
test_vsubsws_614_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [BEDFFF80, 3EE0007F, BE8EFF7F, 3E910080]
test_vsubsws_615_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [807FFD7D, FBFAFA78, 807EF574, F3F3F271]
test_vsubsws_616_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FF7EF70, 7F71007F, 80000000, 70010081]
test_vsubsws_617_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [407FFF80, 4040007F, 407232B2, 400DCD4D]
test_vsubsws_618_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [3EDFFF80, BE60007F, 3E5EFF7F, BE110080]
test_vsubsws_619_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [323231B3, 323232B2, 323131B2, FBFFFE7D]
test_vsubsws_620_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [07060485, 03020180, FFFDFD7C, FBFBFA79]
test_vsubsws_621_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [01010082, 01010181, 01000081, 01020182]
test_vsubsws_622_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [0002FF83, 00010080, FFFEFF7E, FFFF007D]
test_vsubsws_623_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00020002, FFFDFFFE, 00020002, FFFDFFFE]
test_vsubsws_624_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [0000FE7F, 8F8F0080, FFFEFF80, 00010080]
test_vsubsws_625_GEN:
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v3 [FFFFFF81, 00000080, FFFEFF80, 00010081]
test_vsubsws_626_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
test_vsubsws_627_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
#_ REGISTER_OUT v3 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
test_vsubsws_628_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
#_ REGISTER_OUT v3 [FFFF0000, 0000FFFF, FFFFFFFF, 0000FFFF]
test_vsubsws_629_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [FFFEFDFC, FBFAF9F8, F7F6F5F4, F3F2F1F0]
test_vsubsws_630_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
#_ REGISTER_OUT v3 [FFF2FFF2, FFF2FFF2, FFF2FFF2, FFF2FFF2]
test_vsubsws_631_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_OUT v3 [FFEEDDCC, BBAA9988, 77665544, 33221100]
test_vsubsws_632_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
#_ REGISTER_OUT v3 [FF0000FF, FFFF00FF, 00FFFF00, 0000FF00]
test_vsubsws_633_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
#_ REGISTER_OUT v3 [FBFBFBFB, FBFBFBFB, FBFBFBFB, FBFBFBFB]
test_vsubsws_634_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
#_ REGISTER_OUT v3 [F8F8F8F8, F8F8F8F8, F8F8F8F8, F8F8F8F8]
test_vsubsws_635_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
#_ REGISTER_OUT v3 [F7F7F7F7, F7F7F7F7, F7F7F7F7, F7F7F7F7]
test_vsubsws_636_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
#_ REGISTER_OUT v3 [EDEDEDED, EDEDEDED, EDEDEDED, EDEDEDED]
test_vsubsws_637_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
#_ REGISTER_OUT v3 [EDCBA987, 789ABCDE, EEDDCCBB, AA998877]
test_vsubsws_638_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
#_ REGISTER_OUT v3 [C07FFFFF, C03FFFFF, C0733332, C00CCCCC]
test_vsubsws_639_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
#_ REGISTER_OUT v3 [BEDFFFFF, 3EDFFFFF, BE8FFFFF, 3E8FFFFF]
test_vsubsws_640_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
#_ REGISTER_OUT v3 [807FFDFC, FBFAF9F8, 807FF5F4, F3F2F1F0]
test_vsubsws_641_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
#_ REGISTER_OUT v3 [7FF7EFEF, 7F70FFFF, 80000000, 70000000]
test_vsubsws_642_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
#_ REGISTER_OUT v3 [407FFFFF, 403FFFFF, 40733332, 400CCCCC]
test_vsubsws_643_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
#_ REGISTER_OUT v3 [3EDFFFFF, BE5FFFFF, 3E5FFFFF, BE0FFFFF]
test_vsubsws_644_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
#_ REGISTER_OUT v3 [32323232, 32323232, 32323232, FBFEFDFC]
test_vsubsws_645_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
#_ REGISTER_OUT v3 [07060504, 03020100, FFFEFDFC, FBFAF9F8]
test_vsubsws_646_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
test_vsubsws_647_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
#_ REGISTER_OUT v3 [00030002, 00010000, FFFFFFFE, FFFDFFFC]
test_vsubsws_648_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
#_ REGISTER_OUT v3 [00020081, FFFDFF7E, 00030082, FFFCFF7D]
test_vsubsws_649_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
#_ REGISTER_OUT v3 [0000FEFE, 8F8F0000, 00000000, FFFFFFFF]
test_vsubsws_650_GEN:
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
vsubsws v3, v1, v2
blr
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
#_ REGISTER_OUT v3 [0000007F, FFFFFF80, 00010080, FFFEFF7F]
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