5851 lines
227 KiB
ArmAsm
5851 lines
227 KiB
ArmAsm
test_vsubuhs_1_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_2_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_3_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_4_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_5_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_6_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_7_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_8_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_9_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_10_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_11_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_12_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_13_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_14_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_15_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_16_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_17_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_18_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
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|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_19_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
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#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_20_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_21_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_22_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_23_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
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|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_24_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_25_GEN:
|
|
#_ REGISTER_IN v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_26_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
|
|
|
test_vsubuhs_27_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000001, 00000001, 00000001]
|
|
|
|
test_vsubuhs_28_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_29_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_30_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_31_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_32_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_33_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_34_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_35_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_36_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_37_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000000, 00000000]
|
|
|
|
test_vsubuhs_38_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
|
|
|
test_vsubuhs_39_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_40_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000001, 00000000, 00000000]
|
|
|
|
test_vsubuhs_41_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000000, 00000000]
|
|
|
|
test_vsubuhs_42_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
|
|
|
test_vsubuhs_43_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_44_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_45_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_46_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_47_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_48_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000001]
|
|
|
|
test_vsubuhs_49_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_50_GEN:
|
|
#_ REGISTER_IN v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_51_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
|
|
test_vsubuhs_52_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [0000FFFE, FFFF0000, 00000000, FFFF0000]
|
|
|
|
test_vsubuhs_53_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [0000FDFC, FBFA0000, 00000000, F3F20000]
|
|
|
|
test_vsubuhs_54_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [0000FFF2, FFF20000, 00000000, FFF20000]
|
|
|
|
test_vsubuhs_55_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [0000DDCC, BBAA0000, 00000000, 33220000]
|
|
|
|
test_vsubuhs_56_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [000000FF, FFFF0000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_57_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [0000FBFB, FBFB0000, 00000000, FBFB0000]
|
|
|
|
test_vsubuhs_58_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [0000F8F8, F8F80000, 00000000, F8F80000]
|
|
|
|
test_vsubuhs_59_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [0000F7F7, F7F70000, 00000000, F7F70000]
|
|
|
|
test_vsubuhs_60_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [0000EDED, EDED0000, 00000000, EDED0000]
|
|
|
|
test_vsubuhs_61_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [0000A987, 789A0000, 00000000, AA990000]
|
|
|
|
test_vsubuhs_62_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [0000FFFF, C03F0000, 00000000, C00C0000]
|
|
|
|
test_vsubuhs_63_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [0000FFFF, 3EDF0000, 00000000, 3E8F0000]
|
|
|
|
test_vsubuhs_64_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [0000FDFC, FBFA0000, 00000000, F3F20000]
|
|
|
|
test_vsubuhs_65_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [0000EFEF, 7F700000, 00000000, 70000000]
|
|
|
|
test_vsubuhs_66_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [0000FFFF, 403F0000, 00000000, 400C0000]
|
|
|
|
test_vsubuhs_67_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [0000FFFF, BE5F0000, 00000000, BE0F0000]
|
|
|
|
test_vsubuhs_68_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00003232, 32320000, 00000000, FBFE0000]
|
|
|
|
test_vsubuhs_69_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000504, 03020000, 00000000, FBFA0000]
|
|
|
|
test_vsubuhs_70_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000101, 01010000, 00000000, 01010000]
|
|
|
|
test_vsubuhs_71_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000002, 00010000, 00000000, FFFD0000]
|
|
|
|
test_vsubuhs_72_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000081, FFFD0000, 00000000, FFFC0000]
|
|
|
|
test_vsubuhs_73_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000FEFE, 8F8F0000, 00000000, FFFF0000]
|
|
|
|
test_vsubuhs_74_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [0000007F, FFFF0000, 00000000, FFFE0000]
|
|
|
|
test_vsubuhs_75_GEN:
|
|
#_ REGISTER_IN v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_76_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
|
|
test_vsubuhs_77_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00010202, 04050606, 08090A0A, 0C0D0E0E]
|
|
|
|
test_vsubuhs_78_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00010000, 00000607, 08090A0B, 00000E0F]
|
|
|
|
test_vsubuhs_79_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [000001F6, 03F805FA, 07FC09FE, 0C000E02]
|
|
|
|
test_vsubuhs_80_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_81_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00000000, 04050000, 0000090C, 00000D10]
|
|
|
|
test_vsubuhs_82_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [00000000, 00010203, 04050607, 08090A0B]
|
|
|
|
test_vsubuhs_83_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 01020304, 05060708]
|
|
|
|
test_vsubuhs_84_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00010203, 04050607]
|
|
|
|
test_vsubuhs_85_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_86_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_87_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00000203, 00000607, 00000000, 00000000]
|
|
|
|
test_vsubuhs_88_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00000203, 00000607, 00000A0B, 00000E0F]
|
|
|
|
test_vsubuhs_89_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_90_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000607, 00000000, 00000000]
|
|
|
|
test_vsubuhs_91_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00000203, 00000607, 00000000, 00000000]
|
|
|
|
test_vsubuhs_92_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00000203, 00000607, 00000A0B, 00000E0F]
|
|
|
|
test_vsubuhs_93_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 080C0C0C]
|
|
|
|
test_vsubuhs_94_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 08080808, 08080808]
|
|
|
|
test_vsubuhs_95_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_96_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 08090A0A, 0C0B0E0C]
|
|
|
|
test_vsubuhs_97_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 04030586, 00000000, 0C0A0D8D]
|
|
|
|
test_vsubuhs_98_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000102, 00000000, 00000000, 0C0D0E0F]
|
|
|
|
test_vsubuhs_99_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 04050588, 00000000, 0C0C0D8F]
|
|
|
|
test_vsubuhs_100_GEN:
|
|
#_ REGISTER_IN v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_101_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
|
|
test_vsubuhs_102_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [000D000C, 000D000C, 000D000C, 000D000C]
|
|
|
|
test_vsubuhs_103_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [000D0000, 0000000D, 000D000D, 0000000D]
|
|
|
|
test_vsubuhs_104_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [000C0000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_105_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_106_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00000000, 000D0000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_107_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_108_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_109_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_110_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_111_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_112_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [0000000D, 0000000D, 00000000, 00000000]
|
|
|
|
test_vsubuhs_113_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [0000000D, 0000000D, 0000000D, 0000000D]
|
|
|
|
test_vsubuhs_114_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_115_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 0000000D, 00000000, 00000000]
|
|
|
|
test_vsubuhs_116_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [0000000D, 0000000D, 00000000, 00000000]
|
|
|
|
test_vsubuhs_117_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [0000000D, 0000000D, 0000000D, 0000000D]
|
|
|
|
test_vsubuhs_118_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_119_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 000C0000, 00000000]
|
|
|
|
test_vsubuhs_120_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_121_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 000D000C, 000B000A]
|
|
|
|
test_vsubuhs_122_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 000B0000, 00000000, 000A0000]
|
|
|
|
test_vsubuhs_123_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 000D000D]
|
|
|
|
test_vsubuhs_124_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 000D0000, 00000000, 000C0000]
|
|
|
|
test_vsubuhs_125_GEN:
|
|
#_ REGISTER_IN v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_126_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
|
|
test_vsubuhs_127_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00112232, 44556676, 8899AABA, CCDDEEFE]
|
|
|
|
test_vsubuhs_128_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00110000, 00006677, 8899AABB, 0000EEFF]
|
|
|
|
test_vsubuhs_129_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00102030, 40506070, 8090A0B0, C0D0E0F0]
|
|
|
|
test_vsubuhs_130_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00042226, 4448666A, 888CAAAE, CCD0EEF2]
|
|
|
|
test_vsubuhs_131_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [00000000, 44550000, 0000A9BC, 0000EE00]
|
|
|
|
test_vsubuhs_132_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [00001E2F, 40516273, 8495A6B7, C8D9EAFB]
|
|
|
|
test_vsubuhs_133_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [00001B2C, 3D4E5F70, 8192A3B4, C5D6E7F8]
|
|
|
|
test_vsubuhs_134_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [00001A2B, 3C4D5E6F, 8091A2B3, C4D5E6F7]
|
|
|
|
test_vsubuhs_135_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00001021, 32435465, 768798A9, BACBDCED]
|
|
|
|
test_vsubuhs_136_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00000000, 00002356, 77777777, 77777777]
|
|
|
|
test_vsubuhs_137_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00002233, 04956677, 490D0000, 8CEABBCC]
|
|
|
|
test_vsubuhs_138_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00002233, 00006677, 4729AABB, 0B6DEEFF]
|
|
|
|
test_vsubuhs_139_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00002030, 40506070, 0919A0B0, C0D0E0F0]
|
|
|
|
test_vsubuhs_140_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00001223, 00006677, 089A0000, 3CDE0000]
|
|
|
|
test_vsubuhs_141_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00002233, 00006677, 00000000, 0CEABBCC]
|
|
|
|
test_vsubuhs_142_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00002233, 02B56677, 0000AABB, 8AEDEEFF]
|
|
|
|
test_vsubuhs_143_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, C8DCECFC]
|
|
|
|
test_vsubuhs_144_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 8898A8B8, C8D8E8F8]
|
|
|
|
test_vsubuhs_145_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_146_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 8899AABA, CCDBEEFC]
|
|
|
|
test_vsubuhs_147_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 445365F6, 00000000, CCDAEE7D]
|
|
|
|
test_vsubuhs_148_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00002132, 00000000, 00000000, CCDDEEFF]
|
|
|
|
test_vsubuhs_149_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 445565F8, 00000000, CCDCEE7F]
|
|
|
|
test_vsubuhs_150_GEN:
|
|
#_ REGISTER_IN v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_151_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
|
|
test_vsubuhs_152_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [00FFFEFF, 0000FEFF, FF0000FE, FFFF00FE]
|
|
|
|
test_vsubuhs_153_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [00FF0000, 0000FF00, FF0000FF, 000000FF]
|
|
|
|
test_vsubuhs_154_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00FEFCFD, 0000F8F9, F6F70000, F3F20000]
|
|
|
|
test_vsubuhs_155_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [00F2FEF3, 0000FEF3, FEF300F2, FFF200F2]
|
|
|
|
test_vsubuhs_156_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [00EEDCCD, 00009889, 76670000, 33220000]
|
|
|
|
test_vsubuhs_157_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [0000FAFC, 0000FAFC, FAFC0000, FBFB0000]
|
|
|
|
test_vsubuhs_158_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [0000F7F9, 0000F7F9, F7F90000, F8F80000]
|
|
|
|
test_vsubuhs_159_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [0000F6F8, 0000F6F8, F6F80000, F7F70000]
|
|
|
|
test_vsubuhs_160_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [0000ECEE, 0000ECEE, ECEE0000, EDED0000]
|
|
|
|
test_vsubuhs_161_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [0000A888, 0000BBDF, EDDE0000, AA990000]
|
|
|
|
test_vsubuhs_162_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [0000FF00, 0000FF00, BF740000, C00C0000]
|
|
|
|
test_vsubuhs_163_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [0000FF00, 0000FF00, BD9000FF, 3E8F00FF]
|
|
|
|
test_vsubuhs_164_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [0000FCFD, 0000F8F9, 7F800000, F3F20000]
|
|
|
|
test_vsubuhs_165_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [0000EEF0, 0000FF00, 7F010000, 70000000]
|
|
|
|
test_vsubuhs_166_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [0000FF00, 0000FF00, 3F740000, 400C0000]
|
|
|
|
test_vsubuhs_167_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [0000FF00, 0000FF00, 3D6000FF, BE0F00FF]
|
|
|
|
test_vsubuhs_168_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00003133, 00003133, 31330000, FBFE0000]
|
|
|
|
test_vsubuhs_169_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000405, 00000001, FEFF0000, FBFA0000]
|
|
|
|
test_vsubuhs_170_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000002, 00000002, 00020000, 01010000]
|
|
|
|
test_vsubuhs_171_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, FF0000FE, FFFD00FC]
|
|
|
|
test_vsubuhs_172_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 0000FE7F, 00000000, FFFC007D]
|
|
|
|
test_vsubuhs_173_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000FDFF, 00000000, 00000000, FFFF00FF]
|
|
|
|
test_vsubuhs_174_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 0000FE81, 00000000, FFFE007F]
|
|
|
|
test_vsubuhs_175_GEN:
|
|
#_ REGISTER_IN v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_176_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vsubuhs_177_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [04040403, 04040403, 04040403, 04040403]
|
|
|
|
test_vsubuhs_178_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [04040000, 00000404, 04040404, 00000404]
|
|
|
|
test_vsubuhs_179_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [04030201, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_180_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [03F703F7, 03F703F7, 03F703F7, 03F703F7]
|
|
|
|
test_vsubuhs_181_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [03F30000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_182_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [03050000, 04040000, 00000305, 00000305]
|
|
|
|
test_vsubuhs_183_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_184_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_185_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_186_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_187_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00000404, 00000404, 00000000, 00000000]
|
|
|
|
test_vsubuhs_188_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00000404, 00000404, 00000404, 00000404]
|
|
|
|
test_vsubuhs_189_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000201, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_190_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000404, 00000000, 00000000]
|
|
|
|
test_vsubuhs_191_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00000404, 00000404, 00000000, 00000000]
|
|
|
|
test_vsubuhs_192_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00000404, 00000404, 00000404, 00000404]
|
|
|
|
test_vsubuhs_193_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00030201]
|
|
|
|
test_vsubuhs_194_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 04030201, 00000000]
|
|
|
|
test_vsubuhs_195_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_196_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 04040403, 04020401]
|
|
|
|
test_vsubuhs_197_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 04020383, 00000000, 04010382]
|
|
|
|
test_vsubuhs_198_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000303, 00000000, 00000000, 04040404]
|
|
|
|
test_vsubuhs_199_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 04040385, 00000000, 04030384]
|
|
|
|
test_vsubuhs_200_GEN:
|
|
#_ REGISTER_IN v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_201_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [07070707, 07070707, 07070707, 07070707]
|
|
|
|
test_vsubuhs_202_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [07070706, 07070706, 07070706, 07070706]
|
|
|
|
test_vsubuhs_203_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [07070000, 00000707, 07070707, 00000707]
|
|
|
|
test_vsubuhs_204_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [07060504, 03020100, 00000000, 00000000]
|
|
|
|
test_vsubuhs_205_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [06FA06FA, 06FA06FA, 06FA06FA, 06FA06FA]
|
|
|
|
test_vsubuhs_206_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [06F60000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_207_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [06080000, 07070000, 00000608, 00000608]
|
|
|
|
test_vsubuhs_208_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [03030303, 03030303, 03030303, 03030303]
|
|
|
|
test_vsubuhs_209_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_210_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_211_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_212_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00000707, 00000707, 00000000, 00000000]
|
|
|
|
test_vsubuhs_213_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00000707, 00000707, 00000707, 00000707]
|
|
|
|
test_vsubuhs_214_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000504, 03020100, 00000000, 00000000]
|
|
|
|
test_vsubuhs_215_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000707, 00000000, 00000000]
|
|
|
|
test_vsubuhs_216_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00000707, 00000707, 00000000, 00000000]
|
|
|
|
test_vsubuhs_217_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00000707, 00000707, 00000707, 00000707]
|
|
|
|
test_vsubuhs_218_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 03060504]
|
|
|
|
test_vsubuhs_219_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 07060504, 03020100]
|
|
|
|
test_vsubuhs_220_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_221_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 07070706, 07050704]
|
|
|
|
test_vsubuhs_222_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 07050686, 00000000, 07040685]
|
|
|
|
test_vsubuhs_223_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000606, 00000000, 00000000, 07070707]
|
|
|
|
test_vsubuhs_224_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 07070688, 00000000, 07060687]
|
|
|
|
test_vsubuhs_225_GEN:
|
|
#_ REGISTER_IN v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_226_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [08080808, 08080808, 08080808, 08080808]
|
|
|
|
test_vsubuhs_227_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [08080807, 08080807, 08080807, 08080807]
|
|
|
|
test_vsubuhs_228_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [08080000, 00000808, 08080808, 00000808]
|
|
|
|
test_vsubuhs_229_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [08070605, 04030201, 00000000, 00000000]
|
|
|
|
test_vsubuhs_230_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [07FB07FB, 07FB07FB, 07FB07FB, 07FB07FB]
|
|
|
|
test_vsubuhs_231_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [07F70000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_232_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [07090000, 08080000, 00000709, 00000709]
|
|
|
|
test_vsubuhs_233_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [04040404, 04040404, 04040404, 04040404]
|
|
|
|
test_vsubuhs_234_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
|
|
|
|
test_vsubuhs_235_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_236_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_237_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00000808, 00000808, 00000000, 00000000]
|
|
|
|
test_vsubuhs_238_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00000808, 00000808, 00000808, 00000808]
|
|
|
|
test_vsubuhs_239_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000605, 04030201, 00000000, 00000000]
|
|
|
|
test_vsubuhs_240_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000808, 00000000, 00000000]
|
|
|
|
test_vsubuhs_241_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00000808, 00000808, 00000000, 00000000]
|
|
|
|
test_vsubuhs_242_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00000808, 00000808, 00000808, 00000808]
|
|
|
|
test_vsubuhs_243_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 04070605]
|
|
|
|
test_vsubuhs_244_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 08070605, 04030201]
|
|
|
|
test_vsubuhs_245_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_246_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 08080807, 08060805]
|
|
|
|
test_vsubuhs_247_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 08060787, 00000000, 08050786]
|
|
|
|
test_vsubuhs_248_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000707, 00000000, 00000000, 08080808]
|
|
|
|
test_vsubuhs_249_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 08080789, 00000000, 08070788]
|
|
|
|
test_vsubuhs_250_GEN:
|
|
#_ REGISTER_IN v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_251_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [12121212, 12121212, 12121212, 12121212]
|
|
|
|
test_vsubuhs_252_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [12121211, 12121211, 12121211, 12121211]
|
|
|
|
test_vsubuhs_253_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [12120000, 00001212, 12121212, 00001212]
|
|
|
|
test_vsubuhs_254_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [1211100F, 0E0D0C0B, 0A090807, 06050403]
|
|
|
|
test_vsubuhs_255_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [12051205, 12051205, 12051205, 12051205]
|
|
|
|
test_vsubuhs_256_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [12010000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_257_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [11130000, 12120000, 00001113, 00001113]
|
|
|
|
test_vsubuhs_258_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [0E0E0E0E, 0E0E0E0E, 0E0E0E0E, 0E0E0E0E]
|
|
|
|
test_vsubuhs_259_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [0B0B0B0B, 0B0B0B0B, 0B0B0B0B, 0B0B0B0B]
|
|
|
|
test_vsubuhs_260_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [0A0A0A0A, 0A0A0A0A, 0A0A0A0A, 0A0A0A0A]
|
|
|
|
test_vsubuhs_261_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00F00000, 00000000]
|
|
|
|
test_vsubuhs_262_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00001212, 00001212, 00000000, 00000000]
|
|
|
|
test_vsubuhs_263_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00001212, 00001212, 00001212, 00001212]
|
|
|
|
test_vsubuhs_264_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [0000100F, 0E0D0C0B, 00000807, 06050403]
|
|
|
|
test_vsubuhs_265_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000202, 00001212, 00000000, 00000000]
|
|
|
|
test_vsubuhs_266_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00001212, 00001212, 00000000, 00000000]
|
|
|
|
test_vsubuhs_267_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00001212, 00001212, 00001212, 00001212]
|
|
|
|
test_vsubuhs_268_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 0E11100F]
|
|
|
|
test_vsubuhs_269_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 1211100F, 0E0D0C0B]
|
|
|
|
test_vsubuhs_270_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_271_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 12121211, 1210120F]
|
|
|
|
test_vsubuhs_272_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 12101191, 00000000, 120F1190]
|
|
|
|
test_vsubuhs_273_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00001111, 00000000, 00000000, 12121212]
|
|
|
|
test_vsubuhs_274_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 12121193, 00000000, 12111192]
|
|
|
|
test_vsubuhs_275_GEN:
|
|
#_ REGISTER_IN v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_276_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [12345678, 87654321, 11223344, 55667788]
|
|
|
|
test_vsubuhs_277_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [12345677, 87654320, 11223343, 55667787]
|
|
|
|
test_vsubuhs_278_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [12340000, 00004321, 11223344, 00007788]
|
|
|
|
test_vsubuhs_279_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [12335475, 83603D1A, 09192939, 49596979]
|
|
|
|
test_vsubuhs_280_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [1227566B, 87584314, 11153337, 5559777B]
|
|
|
|
test_vsubuhs_281_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [12233445, 43100000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_282_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [11350000, 87650000, 00003245, 00007689]
|
|
|
|
test_vsubuhs_283_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [0E305274, 83613F1D, 0D1E2F40, 51627384]
|
|
|
|
test_vsubuhs_284_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [0B2D4F71, 805E3C1A, 0A1B2C3D, 4E5F7081]
|
|
|
|
test_vsubuhs_285_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [0A2C4E70, 7F5D3B19, 091A2B3C, 4D5E6F80]
|
|
|
|
test_vsubuhs_286_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [00224466, 7553310F, 00002132, 43546576]
|
|
|
|
test_vsubuhs_287_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [00005678, 47A54321, 00000000, 15734455]
|
|
|
|
test_vsubuhs_288_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00005678, 00004321, 00003344, 00007788]
|
|
|
|
test_vsubuhs_289_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00005475, 83603D1A, 00002939, 49596979]
|
|
|
|
test_vsubuhs_290_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00004668, 06D64321, 00000000, 00000000]
|
|
|
|
test_vsubuhs_291_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00005678, 00004321, 00000000, 00004455]
|
|
|
|
test_vsubuhs_292_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00005678, 45C54321, 00003344, 13767788]
|
|
|
|
test_vsubuhs_293_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 51657585]
|
|
|
|
test_vsubuhs_294_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 11213141, 51617181]
|
|
|
|
test_vsubuhs_295_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_296_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 11223343, 55647785]
|
|
|
|
test_vsubuhs_297_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 876342A0, 00000000, 55637706]
|
|
|
|
test_vsubuhs_298_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00005577, 16F50000, 00000000, 55667788]
|
|
|
|
test_vsubuhs_299_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 876542A2, 00000000, 55657708]
|
|
|
|
test_vsubuhs_300_GEN:
|
|
#_ REGISTER_IN v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_301_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
|
|
test_vsubuhs_302_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [3F800000, 3FC00000, 3F8CCCCC, 3FF33332]
|
|
|
|
test_vsubuhs_303_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [3F800000, 00000000, 3F8CCCCD, 00003333]
|
|
|
|
test_vsubuhs_304_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [3F7F0000, 3BBB0000, 3783C2C2, 33E62524]
|
|
|
|
test_vsubuhs_305_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [3F730000, 3FB30000, 3F7FCCC0, 3FE63326]
|
|
|
|
test_vsubuhs_306_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [3F6F0000, 00000000, 00002212, 00000000]
|
|
|
|
test_vsubuhs_307_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [3E810000, 3FC00000, 0000CBCE, 00003234]
|
|
|
|
test_vsubuhs_308_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [3B7C0000, 3BBC0000, 3B88C8C9, 3BEF2F2F]
|
|
|
|
test_vsubuhs_309_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [38790000, 38B90000, 3885C5C6, 38EC2C2C]
|
|
|
|
test_vsubuhs_310_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [37780000, 37B80000, 3784C4C5, 37EB2B2B]
|
|
|
|
test_vsubuhs_311_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [2D6E0000, 2DAE0000, 2D7ABABB, 2DE12121]
|
|
|
|
test_vsubuhs_312_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [2D4C0000, 00000000, 2E6A9989, 00000000]
|
|
|
|
test_vsubuhs_313_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 0000CCCD, 00003333]
|
|
|
|
test_vsubuhs_314_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000000, 3BBB0000, 0000C2C2, 33E62524]
|
|
|
|
test_vsubuhs_315_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_316_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_317_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 0000CCCD, 00003333]
|
|
|
|
test_vsubuhs_318_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 3BF23130]
|
|
|
|
test_vsubuhs_319_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 3F8BCACA, 3BEE2D2C]
|
|
|
|
test_vsubuhs_320_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_321_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 3F8CCCCC, 3FF13330]
|
|
|
|
test_vsubuhs_322_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 3FBE0000, 00000000, 3FF032B1]
|
|
|
|
test_vsubuhs_323_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 3FF33333]
|
|
|
|
test_vsubuhs_324_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 3FC00000, 00000000, 3FF232B3]
|
|
|
|
test_vsubuhs_325_GEN:
|
|
#_ REGISTER_IN v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_326_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
|
|
|
|
test_vsubuhs_327_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [41200000, C1200000, 41700000, C1700000]
|
|
|
|
test_vsubuhs_328_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [41200000, 00000000, 41700000, 00000000]
|
|
|
|
test_vsubuhs_329_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [411F0000, BD1B0000, 39670000, B5630000]
|
|
|
|
test_vsubuhs_330_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [41130000, C1130000, 41630000, C1630000]
|
|
|
|
test_vsubuhs_331_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [410F0000, 7CCB0000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_332_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [40210000, C1200000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_333_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [3D1C0000, BD1C0000, 3D6C0000, BD6C0000]
|
|
|
|
test_vsubuhs_334_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [3A190000, BA190000, 3A690000, BA690000]
|
|
|
|
test_vsubuhs_335_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [39180000, B9180000, 39680000, B9680000]
|
|
|
|
test_vsubuhs_336_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [2F0E0000, AF0E0000, 2F5E0000, AF5E0000]
|
|
|
|
test_vsubuhs_337_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [2EEC0000, 39BB0000, 304E0000, 6C0A0000]
|
|
|
|
test_vsubuhs_338_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [01A00000, 81600000, 01E40000, 817D0000]
|
|
|
|
test_vsubuhs_339_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00000000, BD1B0000, 00000000, B5630000]
|
|
|
|
test_vsubuhs_340_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 40910000, 00000000, 31710000]
|
|
|
|
test_vsubuhs_341_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00000000, 01600000, 00000000, 017D0000]
|
|
|
|
test_vsubuhs_342_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00000000, 7F800000, 00000000, 7F800000]
|
|
|
|
test_vsubuhs_343_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, BD6F0000]
|
|
|
|
test_vsubuhs_344_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 416F0000, BD6B0000]
|
|
|
|
test_vsubuhs_345_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_346_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 41700000, C16E0000]
|
|
|
|
test_vsubuhs_347_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, C11E0000, 00000000, C16D0000]
|
|
|
|
test_vsubuhs_348_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000000, 50B00000, 00000000, C1700000]
|
|
|
|
test_vsubuhs_349_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, C1200000, 00000000, C16F0000]
|
|
|
|
test_vsubuhs_350_GEN:
|
|
#_ REGISTER_IN v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_351_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
|
|
test_vsubuhs_352_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [7F800202, 04050606, 7F800A0A, 0C0D0E0E]
|
|
|
|
test_vsubuhs_353_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [7F800000, 00000607, 7F800A0B, 00000E0F]
|
|
|
|
test_vsubuhs_354_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [7F7F0000, 00000000, 77770000, 00000000]
|
|
|
|
test_vsubuhs_355_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [7F7301F6, 03F805FA, 7F7309FE, 0C000E02]
|
|
|
|
test_vsubuhs_356_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [7F6F0000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_357_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [7E810000, 04050000, 0000090C, 00000D10]
|
|
|
|
test_vsubuhs_358_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [7B7C0000, 00010203, 7B7C0607, 08090A0B]
|
|
|
|
test_vsubuhs_359_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [78790000, 00000000, 78790304, 05060708]
|
|
|
|
test_vsubuhs_360_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [77780000, 00000000, 77780203, 04050607]
|
|
|
|
test_vsubuhs_361_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [6D6E0000, 00000000, 6D6E0000, 00000000]
|
|
|
|
test_vsubuhs_362_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [6D4C0000, 00000000, 6E5E0000, 00000000]
|
|
|
|
test_vsubuhs_363_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [40000203, 00000607, 3FF40000, 00000000]
|
|
|
|
test_vsubuhs_364_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [3E600203, 00000607, 3E100A0B, 00000E0F]
|
|
|
|
test_vsubuhs_365_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000607, 00000000, 00000000]
|
|
|
|
test_vsubuhs_366_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00000203, 00000607, 00000000, 00000000]
|
|
|
|
test_vsubuhs_367_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00000203, 00000607, 00000A0B, 00000E0F]
|
|
|
|
test_vsubuhs_368_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 080C0C0C]
|
|
|
|
test_vsubuhs_369_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 7F7F0808, 08080808]
|
|
|
|
test_vsubuhs_370_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_371_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 7F800A0A, 0C0B0E0C]
|
|
|
|
test_vsubuhs_372_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 04030586, 00000000, 0C0A0D8D]
|
|
|
|
test_vsubuhs_373_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000102, 00000000, 00000000, 0C0D0E0F]
|
|
|
|
test_vsubuhs_374_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 04050588, 00000000, 0C0C0D8F]
|
|
|
|
test_vsubuhs_375_GEN:
|
|
#_ REGISTER_IN v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_376_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
|
|
test_vsubuhs_377_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [8008100F, 808F0000, 7FFFFFFE, 8FFFFFFE]
|
|
|
|
test_vsubuhs_378_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [80080000, 00000000, 7FFFFFFF, 0000FFFF]
|
|
|
|
test_vsubuhs_379_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [80070E0D, 7C8A0000, 77F6F5F4, 83F2F1F0]
|
|
|
|
test_vsubuhs_380_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [7FFB1003, 80820000, 7FF2FFF2, 8FF2FFF2]
|
|
|
|
test_vsubuhs_381_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [7FF70000, 3C3A0000, 00005544, 00001100]
|
|
|
|
test_vsubuhs_382_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [7F090000, 808F0000, 0000FF00, 0000FF00]
|
|
|
|
test_vsubuhs_383_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [7C040C0C, 7C8B0000, 7BFBFBFB, 8BFBFBFB]
|
|
|
|
test_vsubuhs_384_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [79010909, 79880000, 78F8F8F8, 88F8F8F8]
|
|
|
|
test_vsubuhs_385_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [78000808, 78870000, 77F7F7F7, 87F7F7F7]
|
|
|
|
test_vsubuhs_386_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [6DF60000, 6E7D0000, 6DEDEDED, 7DEDEDED]
|
|
|
|
test_vsubuhs_387_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [6DD40000, 00000000, 6EDDCCBB, 3A998877]
|
|
|
|
test_vsubuhs_388_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [40881010, 40CF0000, 40733332, 500CCCCC]
|
|
|
|
test_vsubuhs_389_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [3EE81010, 00000000, 3E8FFFFF, 0000FFFF]
|
|
|
|
test_vsubuhs_390_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [00880E0D, 7C8A0000, 007FF5F4, 83F2F1F0]
|
|
|
|
test_vsubuhs_391_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [00001010, 00000000, 00003332, 0000CCCC]
|
|
|
|
test_vsubuhs_392_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00001010, 3EEF0000, 0000FFFF, 4E0FFFFF]
|
|
|
|
test_vsubuhs_393_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00003232, 8BFEFDFC]
|
|
|
|
test_vsubuhs_394_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 7FFEFDFC, 8BFAF9F8]
|
|
|
|
test_vsubuhs_395_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000101, 00000101]
|
|
|
|
test_vsubuhs_396_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 7FFFFFFE, 8FFDFFFC]
|
|
|
|
test_vsubuhs_397_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 808D0000, 00000082, 8FFCFF7D]
|
|
|
|
test_vsubuhs_398_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000F0F, 101F0000, 00000000, 8FFFFFFF]
|
|
|
|
test_vsubuhs_399_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 808F0000, 00000080, 8FFEFF7F]
|
|
|
|
test_vsubuhs_400_GEN:
|
|
#_ REGISTER_IN v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_401_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
|
|
test_vsubuhs_402_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [BF800000, BFC00000, BF8CCCCC, BFF33332]
|
|
|
|
test_vsubuhs_403_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [BF800000, 00000000, BF8CCCCD, 00003333]
|
|
|
|
test_vsubuhs_404_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [BF7F0000, BBBB0000, B783C2C2, B3E62524]
|
|
|
|
test_vsubuhs_405_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [BF730000, BFB30000, BF7FCCC0, BFE63326]
|
|
|
|
test_vsubuhs_406_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [BF6F0000, 7B6B0000, 36F32212, 00000000]
|
|
|
|
test_vsubuhs_407_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [BE810000, BFC00000, 0000CBCE, 00003234]
|
|
|
|
test_vsubuhs_408_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [BB7C0000, BBBC0000, BB88C8C9, BBEF2F2F]
|
|
|
|
test_vsubuhs_409_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [B8790000, B8B90000, B885C5C6, B8EC2C2C]
|
|
|
|
test_vsubuhs_410_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [B7780000, B7B80000, B784C4C5, B7EB2B2B]
|
|
|
|
test_vsubuhs_411_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [AD6E0000, ADAE0000, AD7ABABB, ADE12121]
|
|
|
|
test_vsubuhs_412_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [AD4C0000, 385B0000, AE6A9989, 6A8D0000]
|
|
|
|
test_vsubuhs_413_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
|
|
|
|
test_vsubuhs_414_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [7E600000, 00000000, 7E1CCCCD, 00003333]
|
|
|
|
test_vsubuhs_415_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [40000000, BBBB0000, 400CC2C2, B3E62524]
|
|
|
|
test_vsubuhs_416_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [3F780000, 3F310000, 3F8D0000, 2FF40000]
|
|
|
|
test_vsubuhs_417_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [00000000, 7E200000, 0000CCCD, 7E033333]
|
|
|
|
test_vsubuhs_418_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, BBF23130]
|
|
|
|
test_vsubuhs_419_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, BF8BCACA, BBEE2D2C]
|
|
|
|
test_vsubuhs_420_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_421_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, BF8CCCCC, BFF13330]
|
|
|
|
test_vsubuhs_422_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, BFBE0000, 00000000, BFF032B1]
|
|
|
|
test_vsubuhs_423_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000000, 4F500000, 00000000, BFF33333]
|
|
|
|
test_vsubuhs_424_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, BFC00000, 00000000, BFF232B3]
|
|
|
|
test_vsubuhs_425_GEN:
|
|
#_ REGISTER_IN v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_426_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
|
|
test_vsubuhs_427_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
|
|
test_vsubuhs_428_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [C1200000, 00000000, C1A00000, 00000000]
|
|
|
|
test_vsubuhs_429_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [C11F0000, 3D9B0000, B9970000, 35E30000]
|
|
|
|
test_vsubuhs_430_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [C1130000, 41930000, C1930000, 41E30000]
|
|
|
|
test_vsubuhs_431_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [C10F0000, 00000000, 39070000, 00000000]
|
|
|
|
test_vsubuhs_432_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [C0210000, 41A00000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_433_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [BD1C0000, 3D9C0000, BD9C0000, 3DEC0000]
|
|
|
|
test_vsubuhs_434_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [BA190000, 3A990000, BA990000, 3AE90000]
|
|
|
|
test_vsubuhs_435_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [B9180000, 39980000, B9980000, 39E80000]
|
|
|
|
test_vsubuhs_436_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [AF0E0000, 2F8E0000, AF8E0000, 2FDE0000]
|
|
|
|
test_vsubuhs_437_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [AEEC0000, 00000000, B07E0000, 00000000]
|
|
|
|
test_vsubuhs_438_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [81A00000, 01E00000, 82140000, 01FD0000]
|
|
|
|
test_vsubuhs_439_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [80000000, 00000000, 80300000, 00000000]
|
|
|
|
test_vsubuhs_440_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [41A00000, 3D9B0000, 42200000, 35E30000]
|
|
|
|
test_vsubuhs_441_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [41180000, 00000000, 41A10000, 00000000]
|
|
|
|
test_vsubuhs_442_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [01A00000, 00000000, 02140000, 00000000]
|
|
|
|
test_vsubuhs_443_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 3DEF0000]
|
|
|
|
test_vsubuhs_444_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, C19F0000, 3DEB0000]
|
|
|
|
test_vsubuhs_445_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_446_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, C1A00000, 41EE0000]
|
|
|
|
test_vsubuhs_447_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, 419E0000, 00000000, 41ED0000]
|
|
|
|
test_vsubuhs_448_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 41F00000]
|
|
|
|
test_vsubuhs_449_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 41A00000, 00000000, 41EF0000]
|
|
|
|
test_vsubuhs_450_GEN:
|
|
#_ REGISTER_IN v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_451_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
|
|
test_vsubuhs_452_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [CDCDCDCC, CDCDCDCC, CDCDCDCC, 04010202]
|
|
|
|
test_vsubuhs_453_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [CDCD0000, 0000CDCD, CDCDCDCD, 00000203]
|
|
|
|
test_vsubuhs_454_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [CDCCCBCA, C9C8C7C6, C5C4C3C2, 00000000]
|
|
|
|
test_vsubuhs_455_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [CDC0CDC0, CDC0CDC0, CDC0CDC0, 03F401F6]
|
|
|
|
test_vsubuhs_456_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [CDBCAB9A, 89786756, 45342312, 00000000]
|
|
|
|
test_vsubuhs_457_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [CCCE0000, CDCD0000, 0000CCCE, 00000104]
|
|
|
|
test_vsubuhs_458_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [C9C9C9C9, C9C9C9C9, C9C9C9C9, 00000000]
|
|
|
|
test_vsubuhs_459_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [C6C6C6C6, C6C6C6C6, C6C6C6C6, 00000000]
|
|
|
|
test_vsubuhs_460_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [C5C5C5C5, C5C5C5C5, C5C5C5C5, 00000000]
|
|
|
|
test_vsubuhs_461_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [BBBBBBBB, BBBBBBBB, BBBBBBBB, 00000000]
|
|
|
|
test_vsubuhs_462_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [BB997755, 46688AAC, BCAB9A89, 00000000]
|
|
|
|
test_vsubuhs_463_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [8E4DCDCD, 8E0DCDCD, 8E410100, 00000000]
|
|
|
|
test_vsubuhs_464_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [8CADCDCD, 0CADCDCD, 8C5DCDCD, 00000203]
|
|
|
|
test_vsubuhs_465_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [4E4DCBCA, C9C8C7C6, 4E4DC3C2, 00000000]
|
|
|
|
test_vsubuhs_466_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [4DC5BDBD, 4D3ECDCD, 4DCE0000, 00000000]
|
|
|
|
test_vsubuhs_467_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [0E4DCDCD, 0E0DCDCD, 0E410100, 00000000]
|
|
|
|
test_vsubuhs_468_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [0CADCDCD, 8C2DCDCD, 0C2DCDCD, 00000203]
|
|
|
|
test_vsubuhs_469_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, CDCCCBCA, 00000000]
|
|
|
|
test_vsubuhs_470_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_471_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, CDCDCDCC, 03FF0200]
|
|
|
|
test_vsubuhs_472_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, CDCBCD4C, 00000000, 03FE0181]
|
|
|
|
test_vsubuhs_473_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000CCCC, 5D5D0000, 00000000, 04010203]
|
|
|
|
test_vsubuhs_474_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, CDCDCD4E, 00000000, 04000183]
|
|
|
|
test_vsubuhs_475_GEN:
|
|
#_ REGISTER_IN v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_476_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
|
|
test_vsubuhs_477_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [F8F9FAFA, FCFDFEFE, 00010202, 04050606]
|
|
|
|
test_vsubuhs_478_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [F8F90000, 0000FEFF, 00010203, 00000607]
|
|
|
|
test_vsubuhs_479_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [F8F8F8F8, F8F8F8F8, 00000000, 00000000]
|
|
|
|
test_vsubuhs_480_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [F8ECFAEE, FCF0FEF2, 000001F6, 03F805FA]
|
|
|
|
test_vsubuhs_481_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [F8E8D8C8, B8A89888, 00000000, 00000000]
|
|
|
|
test_vsubuhs_482_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [F7FA0000, FCFD0000, 00000104, 00000508]
|
|
|
|
test_vsubuhs_483_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [F4F5F6F7, F8F9FAFB, 00000000, 00010203]
|
|
|
|
test_vsubuhs_484_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [F1F2F3F4, F5F6F7F8, 00000000, 00000000]
|
|
|
|
test_vsubuhs_485_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, 00000000, 00000000]
|
|
|
|
test_vsubuhs_486_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [E6E7E8E9, EAEBECED, 00000000, 00000000]
|
|
|
|
test_vsubuhs_487_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [E6C5A483, 7598BBDE, 00000000, 00000000]
|
|
|
|
test_vsubuhs_488_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [B979FAFB, BD3DFEFF, 00000000, 00000000]
|
|
|
|
test_vsubuhs_489_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [B7D9FAFB, 3BDDFEFF, 00000203, 00000607]
|
|
|
|
test_vsubuhs_490_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [7979F8F8, F8F8F8F8, 00000000, 00000000]
|
|
|
|
test_vsubuhs_491_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [78F1EAEB, 7C6EFEFF, 00000000, 00000000]
|
|
|
|
test_vsubuhs_492_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [3979FAFB, 3D3DFEFF, 00000000, 00000000]
|
|
|
|
test_vsubuhs_493_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [37D9FAFB, BB5DFEFF, 00000203, 00000607]
|
|
|
|
test_vsubuhs_494_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [2B2C2D2E, 2F303132, 00000000, 00040404]
|
|
|
|
test_vsubuhs_495_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00000000, 00000001, 00000000, 00000000]
|
|
|
|
test_vsubuhs_496_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00010202, 04030604]
|
|
|
|
test_vsubuhs_497_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, FCFBFE7E, 00000000, 04020585]
|
|
|
|
test_vsubuhs_498_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000F9FA, 8C8D0000, 00000000, 04050607]
|
|
|
|
test_vsubuhs_499_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, FCFDFE80, 00000000, 04040587]
|
|
|
|
test_vsubuhs_500_GEN:
|
|
#_ REGISTER_IN v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_501_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
|
|
test_vsubuhs_502_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FEFEFEFD, FEFEFEFD, FEFEFEFD, FEFEFEFD]
|
|
|
|
test_vsubuhs_503_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [FEFE0000, 0000FEFE, FEFEFEFE, 0000FEFE]
|
|
|
|
test_vsubuhs_504_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FEFDFCFB, FAF9F8F7, F6F5F4F3, F2F1F0EF]
|
|
|
|
test_vsubuhs_505_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [FEF1FEF1, FEF1FEF1, FEF1FEF1, FEF1FEF1]
|
|
|
|
test_vsubuhs_506_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FEEDDCCB, BAA99887, 76655443, 32210FFF]
|
|
|
|
test_vsubuhs_507_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FDFF0000, FEFE0000, 0000FDFF, 0000FDFF]
|
|
|
|
test_vsubuhs_508_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [FAFAFAFA, FAFAFAFA, FAFAFAFA, FAFAFAFA]
|
|
|
|
test_vsubuhs_509_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [F7F7F7F7, F7F7F7F7, F7F7F7F7, F7F7F7F7]
|
|
|
|
test_vsubuhs_510_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [F6F6F6F6, F6F6F6F6, F6F6F6F6, F6F6F6F6]
|
|
|
|
test_vsubuhs_511_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [ECECECEC, ECECECEC, ECECECEC, ECECECEC]
|
|
|
|
test_vsubuhs_512_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [ECCAA886, 7799BBDD, EDDCCBBA, A9988776]
|
|
|
|
test_vsubuhs_513_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [BF7EFEFE, BF3EFEFE, BF723231, BF0BCBCB]
|
|
|
|
test_vsubuhs_514_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [BDDEFEFE, 3DDEFEFE, BD8EFEFE, 3D8EFEFE]
|
|
|
|
test_vsubuhs_515_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [7F7EFCFB, FAF9F8F7, 7F7EF4F3, F2F1F0EF]
|
|
|
|
test_vsubuhs_516_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [7EF6EEEE, 7E6FFEFE, 7EFF0000, 6EFF0000]
|
|
|
|
test_vsubuhs_517_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [3F7EFEFE, 3F3EFEFE, 3F723231, 3F0BCBCB]
|
|
|
|
test_vsubuhs_518_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [3DDEFEFE, BD5EFEFE, 3D5EFEFE, BD0EFEFE]
|
|
|
|
test_vsubuhs_519_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [31313131, 31313131, 31313131, FAFDFCFB]
|
|
|
|
test_vsubuhs_520_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [06050403, 02010000, FEFDFCFB, FAF9F8F7]
|
|
|
|
test_vsubuhs_521_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, FEFEFEFD, FEFCFEFB]
|
|
|
|
test_vsubuhs_522_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00000000, FEFCFE7D, 00000000, FEFBFE7C]
|
|
|
|
test_vsubuhs_523_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000FDFD, 8E8E0000, 00000000, FEFEFEFE]
|
|
|
|
test_vsubuhs_524_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, FEFEFE7F, 00000000, FEFDFE7E]
|
|
|
|
test_vsubuhs_525_GEN:
|
|
#_ REGISTER_IN v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_526_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
|
|
test_vsubuhs_527_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FFFCFFFC, FFFEFFFE, 00000000, 00020002]
|
|
|
|
test_vsubuhs_528_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [FFFC0000, 0000FFFF, 00000001, 00000003]
|
|
|
|
test_vsubuhs_529_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFFBFDFA, FBF9F9F8, 00000000, 00000000]
|
|
|
|
test_vsubuhs_530_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [FFEFFFF0, FFF1FFF2, 00000000, 00000000]
|
|
|
|
test_vsubuhs_531_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FFEBDDCA, BBA99988, 00000000, 00000000]
|
|
|
|
test_vsubuhs_532_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FEFD00FD, FFFE00FF, 00000000, 00000000]
|
|
|
|
test_vsubuhs_533_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [FBF8FBF9, FBFAFBFB, 00000000, 00000000]
|
|
|
|
test_vsubuhs_534_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [F8F5F8F6, F8F7F8F8, 00000000, 00000000]
|
|
|
|
test_vsubuhs_535_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [F7F4F7F5, F7F6F7F7, 00000000, 00000000]
|
|
|
|
test_vsubuhs_536_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [EDEAEDEB, EDECEDED, 00000000, 00000000]
|
|
|
|
test_vsubuhs_537_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [EDC8A985, 7899BCDE, 00000000, 00000000]
|
|
|
|
test_vsubuhs_538_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [C07CFFFD, C03EFFFF, 00000000, 00000000]
|
|
|
|
test_vsubuhs_539_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [BEDCFFFD, 3EDEFFFF, 00000001, 00000003]
|
|
|
|
test_vsubuhs_540_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [807CFDFA, FBF9F9F8, 00000000, 00000000]
|
|
|
|
test_vsubuhs_541_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [7FF4EFED, 7F6FFFFF, 00000000, 00000000]
|
|
|
|
test_vsubuhs_542_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [407CFFFD, 403EFFFF, 00000000, 00000000]
|
|
|
|
test_vsubuhs_543_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [3EDCFFFD, BE5EFFFF, 00000001, 00000003]
|
|
|
|
test_vsubuhs_544_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [322F3230, 32313232, 00000000, 00000000]
|
|
|
|
test_vsubuhs_545_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [07030502, 03010100, 00000000, 00000000]
|
|
|
|
test_vsubuhs_546_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00FE00FF, 01000101, 00000000, 00000000]
|
|
|
|
test_vsubuhs_547_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [0000007F, FFFCFF7E, 00000000, 00000000]
|
|
|
|
test_vsubuhs_548_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000FEFC, 8F8E0000, 00000000, 00020003]
|
|
|
|
test_vsubuhs_549_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [0000007D, FFFEFF80, 00000000, 00010000]
|
|
|
|
test_vsubuhs_550_GEN:
|
|
#_ REGISTER_IN v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_551_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
|
|
test_vsubuhs_552_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FFFDFF7D, 00020080, FFFCFF7C, 00030081]
|
|
|
|
test_vsubuhs_553_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [FFFD0000, 00000081, FFFCFF7D, 00000082]
|
|
|
|
test_vsubuhs_554_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFFCFD7B, 00000000, F7F3F572, 00000000]
|
|
|
|
test_vsubuhs_555_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [FFF0FF71, 00000074, FFEFFF70, 00000075]
|
|
|
|
test_vsubuhs_556_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FFECDD4B, 00000000, 776354C2, 00000000]
|
|
|
|
test_vsubuhs_557_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FEFE007E, 00020000, 00FCFE7E, 00000000]
|
|
|
|
test_vsubuhs_558_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [FBF9FB7A, 00000000, FBF8FB79, 00000000]
|
|
|
|
test_vsubuhs_559_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [F8F6F877, 00000000, F8F5F876, 00000000]
|
|
|
|
test_vsubuhs_560_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [F7F5F776, 00000000, F7F4F775, 00000000]
|
|
|
|
test_vsubuhs_561_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [EDEBED6C, 00000000, EDEAED6B, 00000000]
|
|
|
|
test_vsubuhs_562_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [EDC9A906, 00000000, EEDACC39, 00000000]
|
|
|
|
test_vsubuhs_563_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [C07DFF7E, 00000081, C07032B0, 00000000]
|
|
|
|
test_vsubuhs_564_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [BEDDFF7E, 00000081, BE8CFF7D, 00000082]
|
|
|
|
test_vsubuhs_565_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [807DFD7B, 00000000, 807CF572, 00000000]
|
|
|
|
test_vsubuhs_566_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [7FF5EF6E, 00000081, 7FFD0000, 00000000]
|
|
|
|
test_vsubuhs_567_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [407DFF7E, 00000081, 407032B0, 00000000]
|
|
|
|
test_vsubuhs_568_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [3EDDFF7E, 00000081, 3E5CFF7D, 00000082]
|
|
|
|
test_vsubuhs_569_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [323031B1, 00000000, 322F31B0, 00000000]
|
|
|
|
test_vsubuhs_570_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [07040483, 00000000, FFFBFD7A, 00000000]
|
|
|
|
test_vsubuhs_571_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [00FF0080, 00000000, 00FE007F, 00000000]
|
|
|
|
test_vsubuhs_572_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00010000, 00000000, FFFCFF7C, 0001007F]
|
|
|
|
test_vsubuhs_573_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000FE7D, 00000000, 00000000, 00030082]
|
|
|
|
test_vsubuhs_574_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 00020002, 00000000, 00020002]
|
|
|
|
test_vsubuhs_575_GEN:
|
|
#_ REGISTER_IN v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_576_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
|
|
test_vsubuhs_577_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FFFF0100, 7070FFFE, FFFFFFFE, 00000000]
|
|
|
|
test_vsubuhs_578_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [FFFF0000, 0000FFFF, FFFFFFFF, 00000000]
|
|
|
|
test_vsubuhs_579_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFFE0000, 6C6BF9F8, F7F6F5F4, 00000000]
|
|
|
|
test_vsubuhs_580_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [FFF200F4, 7063FFF2, FFF2FFF2, 00000000]
|
|
|
|
test_vsubuhs_581_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FFEE0000, 2C1B9988, 77665544, 00000000]
|
|
|
|
test_vsubuhs_582_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FF000000, 707000FF, 00FFFF00, 00000000]
|
|
|
|
test_vsubuhs_583_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [FBFB0000, 6C6CFBFB, FBFBFBFB, 00000000]
|
|
|
|
test_vsubuhs_584_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [F8F80000, 6969F8F8, F8F8F8F8, 00000000]
|
|
|
|
test_vsubuhs_585_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [F7F70000, 6868F7F7, F7F7F7F7, 00000000]
|
|
|
|
test_vsubuhs_586_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [EDED0000, 5E5EEDED, EDEDEDED, 00000000]
|
|
|
|
test_vsubuhs_587_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [EDCB0000, 0000BCDE, EEDDCCBB, 00000000]
|
|
|
|
test_vsubuhs_588_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [C07F0101, 30B0FFFF, C0733332, 00000000]
|
|
|
|
test_vsubuhs_589_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [BEDF0101, 0000FFFF, BE8FFFFF, 00000000]
|
|
|
|
test_vsubuhs_590_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [807F0000, 6C6BF9F8, 807FF5F4, 00000000]
|
|
|
|
test_vsubuhs_591_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [7FF70000, 0000FFFF, 80000000, 00000000]
|
|
|
|
test_vsubuhs_592_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [407F0101, 0000FFFF, 40733332, 00000000]
|
|
|
|
test_vsubuhs_593_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [3EDF0101, 2ED0FFFF, 3E5FFFFF, 00000000]
|
|
|
|
test_vsubuhs_594_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [32320000, 00003232, 32323232, 00000000]
|
|
|
|
test_vsubuhs_595_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [07060000, 00000100, FFFEFDFC, 00000000]
|
|
|
|
test_vsubuhs_596_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [01010000, 00000101, 01010101, 00000000]
|
|
|
|
test_vsubuhs_597_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00030000, 00000000, FFFFFFFE, 00000000]
|
|
|
|
test_vsubuhs_598_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00020000, 706EFF7E, 00030082, 00000000]
|
|
|
|
test_vsubuhs_599_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [00000000, 7070FF80, 00010080, 00000000]
|
|
|
|
test_vsubuhs_600_GEN:
|
|
#_ REGISTER_IN v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_601_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
|
|
test_vsubuhs_602_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FFFFFF7F, 0000007E, FFFEFF7E, 0001007F]
|
|
|
|
test_vsubuhs_603_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [FFFF0000, 0000007F, FFFEFF7F, 00000080]
|
|
|
|
test_vsubuhs_604_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFFEFD7D, 00000000, F7F5F574, 00000000]
|
|
|
|
test_vsubuhs_605_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [FFF2FF73, 00000072, FFF1FF72, 00000073]
|
|
|
|
test_vsubuhs_606_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FFEEDD4D, 00000000, 776554C4, 00000000]
|
|
|
|
test_vsubuhs_607_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FF000080, 00000000, 00FEFE80, 00000000]
|
|
|
|
test_vsubuhs_608_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [FBFBFB7C, 00000000, FBFAFB7B, 00000000]
|
|
|
|
test_vsubuhs_609_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [F8F8F879, 00000000, F8F7F878, 00000000]
|
|
|
|
test_vsubuhs_610_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [F7F7F778, 00000000, F7F6F777, 00000000]
|
|
|
|
test_vsubuhs_611_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [EDEDED6E, 00000000, EDECED6D, 00000000]
|
|
|
|
test_vsubuhs_612_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [EDCBA908, 00000000, EEDCCC3B, 00000000]
|
|
|
|
test_vsubuhs_613_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [C07FFF80, 0000007F, C07232B2, 00000000]
|
|
|
|
test_vsubuhs_614_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [BEDFFF80, 0000007F, BE8EFF7F, 00000080]
|
|
|
|
test_vsubuhs_615_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [807FFD7D, 00000000, 807EF574, 00000000]
|
|
|
|
test_vsubuhs_616_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [7FF7EF70, 0000007F, 7FFF0000, 00000000]
|
|
|
|
test_vsubuhs_617_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [407FFF80, 0000007F, 407232B2, 00000000]
|
|
|
|
test_vsubuhs_618_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [3EDFFF80, 0000007F, 3E5EFF7F, 00000080]
|
|
|
|
test_vsubuhs_619_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [323231B3, 00000000, 323131B2, 00000000]
|
|
|
|
test_vsubuhs_620_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [07060485, 00000000, FFFDFD7C, 00000000]
|
|
|
|
test_vsubuhs_621_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [01010082, 00000000, 01000081, 00000000]
|
|
|
|
test_vsubuhs_622_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00030000, 00000000, FFFEFF7E, 0000007D]
|
|
|
|
test_vsubuhs_623_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00020002, 00000000, 00020002, 00000000]
|
|
|
|
test_vsubuhs_624_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000FE7F, 00000000, 00000000, 00010080]
|
|
|
|
test_vsubuhs_625_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_IN v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v2 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
|
|
|
test_vsubuhs_626_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00000000, 00000000, 00000000, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00000000, 00000000, 00000000, 00000000]
|
|
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
|
|
test_vsubuhs_627_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00000001, 00000001, 00000001, 00000001]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00000001, 00000001, 00000001, 00000001]
|
|
#_ REGISTER_OUT v3 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]
|
|
|
|
test_vsubuhs_628_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [0000FFFF, FFFF0000, 00000000, FFFF0000]
|
|
#_ REGISTER_OUT v3 [FFFF0000, 0000FFFF, FFFFFFFF, 0000FFFF]
|
|
|
|
test_vsubuhs_629_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00010203, 04050607, 08090A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [FFFEFDFC, FBFAF9F8, F7F6F5F4, F3F2F1F0]
|
|
|
|
test_vsubuhs_630_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [000D000D, 000D000D, 000D000D, 000D000D]
|
|
#_ REGISTER_OUT v3 [FFF2FFF2, FFF2FFF2, FFF2FFF2, FFF2FFF2]
|
|
|
|
test_vsubuhs_631_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00112233, 44556677, 8899AABB, CCDDEEFF]
|
|
#_ REGISTER_OUT v3 [FFEEDDCC, BBAA9988, 77665544, 33221100]
|
|
|
|
test_vsubuhs_632_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [00FFFF00, 0000FF00, FF0000FF, FFFF00FF]
|
|
#_ REGISTER_OUT v3 [FF0000FF, FFFF00FF, 00FFFF00, 0000FF00]
|
|
|
|
test_vsubuhs_633_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [04040404, 04040404, 04040404, 04040404]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [04040404, 04040404, 04040404, 04040404]
|
|
#_ REGISTER_OUT v3 [FBFBFBFB, FBFBFBFB, FBFBFBFB, FBFBFBFB]
|
|
|
|
test_vsubuhs_634_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [07070707, 07070707, 07070707, 07070707]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [07070707, 07070707, 07070707, 07070707]
|
|
#_ REGISTER_OUT v3 [F8F8F8F8, F8F8F8F8, F8F8F8F8, F8F8F8F8]
|
|
|
|
test_vsubuhs_635_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [08080808, 08080808, 08080808, 08080808]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [08080808, 08080808, 08080808, 08080808]
|
|
#_ REGISTER_OUT v3 [F7F7F7F7, F7F7F7F7, F7F7F7F7, F7F7F7F7]
|
|
|
|
test_vsubuhs_636_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [12121212, 12121212, 12121212, 12121212]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [12121212, 12121212, 12121212, 12121212]
|
|
#_ REGISTER_OUT v3 [EDEDEDED, EDEDEDED, EDEDEDED, EDEDEDED]
|
|
|
|
test_vsubuhs_637_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [12345678, 87654321, 11223344, 55667788]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [12345678, 87654321, 11223344, 55667788]
|
|
#_ REGISTER_OUT v3 [EDCBA987, 789ABCDE, EEDDCCBB, AA998877]
|
|
|
|
test_vsubuhs_638_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [3F800000, 3FC00000, 3F8CCCCD, 3FF33333]
|
|
#_ REGISTER_OUT v3 [C07FFFFF, C03FFFFF, C0733332, C00CCCCC]
|
|
|
|
test_vsubuhs_639_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [41200000, C1200000, 41700000, C1700000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [41200000, C1200000, 41700000, C1700000]
|
|
#_ REGISTER_OUT v3 [BEDFFFFF, 3EDFFFFF, BE8FFFFF, 3E8FFFFF]
|
|
|
|
test_vsubuhs_640_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [7F800203, 04050607, 7F800A0B, 0C0D0E0F]
|
|
#_ REGISTER_OUT v3 [807FFDFC, FBFAF9F8, 807FF5F4, F3F2F1F0]
|
|
|
|
test_vsubuhs_641_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [80081010, 808F0000, 7FFFFFFF, 8FFFFFFF]
|
|
#_ REGISTER_OUT v3 [7FF7EFEF, 7F70FFFF, 80000000, 70000000]
|
|
|
|
test_vsubuhs_642_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [BF800000, BFC00000, BF8CCCCD, BFF33333]
|
|
#_ REGISTER_OUT v3 [407FFFFF, 403FFFFF, 40733332, 400CCCCC]
|
|
|
|
test_vsubuhs_643_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [C1200000, 41A00000, C1A00000, 41F00000]
|
|
#_ REGISTER_OUT v3 [3EDFFFFF, BE5FFFFF, 3E5FFFFF, BE0FFFFF]
|
|
|
|
test_vsubuhs_644_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
|
|
#_ REGISTER_OUT v3 [32323232, 32323232, 32323232, FBFEFDFC]
|
|
|
|
test_vsubuhs_645_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [F8F9FAFB, FCFDFEFF, 00010203, 04050607]
|
|
#_ REGISTER_OUT v3 [07060504, 03020100, FFFEFDFC, FBFAF9F8]
|
|
|
|
test_vsubuhs_646_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]
|
|
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
|
|
|
|
test_vsubuhs_647_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFCFFFD, FFFEFFFF, 00000001, 00020003]
|
|
#_ REGISTER_OUT v3 [00030002, 00010000, FFFFFFFE, FFFDFFFC]
|
|
|
|
test_vsubuhs_648_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFDFF7E, 00020081, FFFCFF7D, 00030082]
|
|
#_ REGISTER_OUT v3 [00020081, FFFDFF7E, 00030082, FFFCFF7D]
|
|
|
|
test_vsubuhs_649_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFF0101, 7070FFFF, FFFFFFFF, 00000000]
|
|
#_ REGISTER_OUT v3 [0000FEFE, 8F8F0000, 00000000, FFFFFFFF]
|
|
|
|
test_vsubuhs_650_GEN:
|
|
#_ REGISTER_IN v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_IN v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
vsubuhs v3, v1, v2
|
|
blr
|
|
#_ REGISTER_OUT v1 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
|
#_ REGISTER_OUT v2 [FFFFFF80, 0000007F, FFFEFF7F, 00010080]
|
|
#_ REGISTER_OUT v3 [0000007F, FFFFFF80, 00010080, FFFEFF7F]
|
|
|