238 lines
7.7 KiB
C++
238 lines
7.7 KiB
C++
/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2013 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#ifndef XENIA_GPU_XENOS_XENOS_H_
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#define XENIA_GPU_XENOS_XENOS_H_
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#include <xenia/core.h>
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namespace xe {
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namespace gpu {
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namespace xenos {
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typedef enum {
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XE_GPU_SHADER_TYPE_VERTEX = 0x00,
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XE_GPU_SHADER_TYPE_PIXEL = 0x01,
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} XE_GPU_SHADER_TYPE;
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typedef enum {
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XE_GPU_INVALIDATE_MASK_VERTEX_SHADER = 1 << 8,
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XE_GPU_INVALIDATE_MASK_PIXEL_SHADER = 1 << 9,
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XE_GPU_INVALIDATE_MASK_ALL = 0x7FFF,
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} XE_GPU_INVALIDATE_MASK;
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typedef enum {
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XE_GPU_PRIMITIVE_TYPE_POINT_LIST = 0x01,
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XE_GPU_PRIMITIVE_TYPE_LINE_LIST = 0x02,
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XE_GPU_PRIMITIVE_TYPE_LINE_STRIP = 0x03,
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XE_GPU_PRIMITIVE_TYPE_TRIANGLE_LIST = 0x04,
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XE_GPU_PRIMITIVE_TYPE_TRIANGLE_FAN = 0x05,
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XE_GPU_PRIMITIVE_TYPE_TRIANGLE_STRIP = 0x06,
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XE_GPU_PRIMITIVE_TYPE_UNKNOWN_07 = 0x07,
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XE_GPU_PRIMITIVE_TYPE_RECTANGLE_LIST = 0x08,
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XE_GPU_PRIMITIVE_TYPE_LINE_LOOP = 0x0C,
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XE_GPU_PRIMITIVE_TYPE_QUAD_LIST = 0x0D,
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} XE_GPU_PRIMITIVE_TYPE;
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typedef enum {
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XE_GPU_ENDIAN_NONE = 0x0,
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XE_GPU_ENDIAN_8IN16 = 0x1,
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XE_GPU_ENDIAN_8IN32 = 0x2,
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XE_GPU_ENDIAN_16IN32 = 0x3,
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} XE_GPU_ENDIAN;
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#define XE_GPU_MAKE_SWIZZLE(x, y, z, w) \
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(((XE_GPU_SWIZZLE_##x) << 0) | ((XE_GPU_SWIZZLE_##y) << 3) | ((XE_GPU_SWIZZLE_##z) << 6) | ((XE_GPU_SWIZZLE_##w) << 9))
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typedef enum {
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XE_GPU_SWIZZLE_X = 0,
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XE_GPU_SWIZZLE_R = 0,
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XE_GPU_SWIZZLE_Y = 1,
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XE_GPU_SWIZZLE_G = 1,
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XE_GPU_SWIZZLE_Z = 2,
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XE_GPU_SWIZZLE_B = 2,
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XE_GPU_SWIZZLE_W = 3,
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XE_GPU_SWIZZLE_A = 3,
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XE_GPU_SWIZZLE_0 = 4,
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XE_GPU_SWIZZLE_1 = 5,
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XE_GPU_SWIZZLE_RGBA = XE_GPU_MAKE_SWIZZLE(R, G, B, A),
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XE_GPU_SWIZZLE_BGRA = XE_GPU_MAKE_SWIZZLE(B, G, R, A),
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XE_GPU_SWIZZLE_RGB1 = XE_GPU_MAKE_SWIZZLE(R, G, B, 1),
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XE_GPU_SWIZZLE_BGR1 = XE_GPU_MAKE_SWIZZLE(B, G, R, 1),
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XE_GPU_SWIZZLE_000R = XE_GPU_MAKE_SWIZZLE(0, 0, 0, R),
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XE_GPU_SWIZZLE_RRR1 = XE_GPU_MAKE_SWIZZLE(R, R, R, 1),
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XE_GPU_SWIZZLE_R111 = XE_GPU_MAKE_SWIZZLE(R, 1, 1, 1),
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XE_GPU_SWIZZLE_R000 = XE_GPU_MAKE_SWIZZLE(R, 0, 0, 0),
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} XE_GPU_SWIZZLE;
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XEFORCEINLINE uint32_t GpuSwap(uint32_t value, XE_GPU_ENDIAN endianness) {
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switch (endianness) {
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default:
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case XE_GPU_ENDIAN_NONE: // No swap.
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return value;
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case XE_GPU_ENDIAN_8IN16: // Swap bytes in half words.
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return ((value << 8) & 0xFF00FF00) |
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((value >> 8) & 0x00FF00FF);
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case XE_GPU_ENDIAN_8IN32: // Swap bytes.
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// NOTE: we are likely doing two swaps here. Wasteful. Oh well.
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return XESWAP32(value);
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case XE_GPU_ENDIAN_16IN32: // Swap half words.
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return ((value >> 16) & 0xFFFF) | (value << 16);
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}
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}
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XEFORCEINLINE uint32_t GpuToCpu(uint32_t p) {
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return p;
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}
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XEFORCEINLINE uint32_t GpuToCpu(uint32_t base, uint32_t p) {
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uint32_t upper = base & 0xFF000000;
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uint32_t lower = p & 0x00FFFFFF;
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return upper + lower;// -(((base >> 20) + 0x200) & 0x1000);
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}
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// XE_GPU_REG_SQ_PROGRAM_CNTL
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typedef union {
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XEPACKEDSTRUCTANONYMOUS({
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uint32_t vs_regs : 6;
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uint32_t : 2;
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uint32_t ps_regs : 6;
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uint32_t : 2;
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uint32_t vs_resource : 1;
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uint32_t ps_resource : 1;
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uint32_t param_gen : 1;
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uint32_t unknown0 : 1;
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uint32_t vs_export_count : 4;
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uint32_t vs_export_mode : 3;
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uint32_t ps_export_depth : 1;
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uint32_t ps_export_count : 3;
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uint32_t gen_index_vtx : 1;
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});
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XEPACKEDSTRUCTANONYMOUS({
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uint32_t dword_0;
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});
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} xe_gpu_program_cntl_t;
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// XE_GPU_REG_SHADER_CONSTANT_FETCH_*
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XEPACKEDUNION(xe_gpu_vertex_fetch_t, {
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XEPACKEDSTRUCTANONYMOUS({
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uint32_t type : 2;
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uint32_t address : 30;
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uint32_t endian : 2;
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uint32_t size : 24;
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uint32_t unk1 : 6;
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});
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XEPACKEDSTRUCTANONYMOUS({
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uint32_t dword_0;
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uint32_t dword_1;
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});
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});
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// XE_GPU_REG_SHADER_CONSTANT_FETCH_*
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XEPACKEDUNION(xe_gpu_texture_fetch_t, {
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XEPACKEDSTRUCTANONYMOUS({
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uint32_t type : 2; // dword_0
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uint32_t sign_x : 2;
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uint32_t sign_y : 2;
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uint32_t sign_z : 2;
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uint32_t sign_w : 2;
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uint32_t clamp_x : 3;
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uint32_t clamp_y : 3;
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uint32_t clamp_z : 3;
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uint32_t unk0 : 3;
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uint32_t pitch : 9;
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uint32_t tiled : 1;
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uint32_t format : 6; // dword_1
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uint32_t endianness : 2;
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uint32_t unk1 : 4;
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uint32_t address : 20;
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union { // dword_2
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struct {
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uint32_t width : 24;
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uint32_t unused : 8;
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} size_1d;
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struct {
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uint32_t width : 13;
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uint32_t height : 13;
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uint32_t unused : 6;
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} size_2d;
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struct {
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uint32_t width : 13;
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uint32_t height : 13;
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uint32_t depth : 6;
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} size_stack;
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struct {
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uint32_t width : 11;
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uint32_t height : 11;
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uint32_t depth : 10;
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} size_3d;
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};
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uint32_t unk3_0 : 1; // dword_3
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uint32_t swizzle : 12; // xyzw, 3b each (XE_GPU_SWIZZLE)
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uint32_t unk3_1 : 6;
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uint32_t mag_filter : 2;
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uint32_t min_filter : 2;
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uint32_t mip_filter : 2;
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uint32_t unk3_2 : 6;
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uint32_t border : 1;
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uint32_t unk4; // dword_4
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uint32_t unk5 : 9; // dword_5
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uint32_t dimension : 2;
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uint32_t unk5b : 21;
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});
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XEPACKEDSTRUCTANONYMOUS({
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uint32_t dword_0;
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uint32_t dword_1;
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uint32_t dword_2;
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uint32_t dword_3;
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uint32_t dword_4;
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uint32_t dword_5;
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});
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});
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// XE_GPU_REG_SHADER_CONSTANT_FETCH_*
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XEPACKEDUNION(xe_gpu_fetch_group_t, {
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xe_gpu_texture_fetch_t texture_fetch;
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XEPACKEDSTRUCTANONYMOUS({
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xe_gpu_vertex_fetch_t vertex_fetch_0;
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xe_gpu_vertex_fetch_t vertex_fetch_1;
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xe_gpu_vertex_fetch_t vertex_fetch_2;
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});
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XEPACKEDSTRUCTANONYMOUS({
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uint32_t dword_0;
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uint32_t dword_1;
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uint32_t dword_2;
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uint32_t dword_3;
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uint32_t dword_4;
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uint32_t dword_5;
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});
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XEPACKEDSTRUCTANONYMOUS({
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uint32_t type_0 : 2;
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uint32_t : 30;
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uint32_t : 32;
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uint32_t type_1 : 2;
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uint32_t : 30;
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uint32_t : 32;
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uint32_t type_2 : 2;
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uint32_t : 30;
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uint32_t : 32;
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});
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});
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} // namespace xenos
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} // namespace gpu
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} // namespace xe
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#endif // XENIA_GPU_XENOS_XENOS_H_
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