167 lines
3.1 KiB
ArmAsm
167 lines
3.1 KiB
ArmAsm
test_divd_1:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 2
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divd r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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test_divd_1_constant:
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li r4, 1
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li r5, 2
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divd r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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# TODO(benvanik): x64 ignore divide by zero (=0)
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#test_divd_2:
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# #_ REGISTER_IN r4 1
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# #_ REGISTER_IN r5 0
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# divd r3, r4, r5
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# blr
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# #_ REGISTER_OUT r3 0
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# #_ REGISTER_OUT r4 1
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# #_ REGISTER_OUT r5 0
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# TODO(benvanik): x64 ignore divide by zero (=0)
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#test_divd_2_constant:
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# li r4, 1
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# li r5, 0
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# divd r3, r4, r5
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# blr
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# #_ REGISTER_OUT r3 0
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# #_ REGISTER_OUT r4 1
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# #_ REGISTER_OUT r5 0
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test_divd_3:
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#_ REGISTER_IN r4 2
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#_ REGISTER_IN r5 1
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divd r3, r4, r5
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blr
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#_ REGISTER_OUT r3 2
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#_ REGISTER_OUT r4 2
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#_ REGISTER_OUT r5 1
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test_divd_3_constant:
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li r4, 2
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li r5, 1
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divd r3, r4, r5
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blr
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#_ REGISTER_OUT r3 2
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#_ REGISTER_OUT r4 2
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#_ REGISTER_OUT r5 1
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test_divd_4:
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#_ REGISTER_IN r4 35
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#_ REGISTER_IN r5 7
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divd r3, r4, r5
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blr
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#_ REGISTER_OUT r3 5
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#_ REGISTER_OUT r4 35
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#_ REGISTER_OUT r5 7
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test_divd_4_constant:
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li r4, 35
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li r5, 7
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divd r3, r4, r5
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blr
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#_ REGISTER_OUT r3 5
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#_ REGISTER_OUT r4 35
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#_ REGISTER_OUT r5 7
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test_divd_5:
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#_ REGISTER_IN r4 0
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#_ REGISTER_IN r5 1
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divd r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0
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#_ REGISTER_OUT r5 1
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test_divd_5_constant:
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li r4, 0
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li r5, 1
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divd r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0
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#_ REGISTER_OUT r5 1
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test_divd_6:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 1
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divd r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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test_divd_6_constant:
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li r4, -1
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li r5, 1
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divd r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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test_divd_7:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
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divd r3, r4, r5
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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test_divd_7_constant:
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li r4, -1
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li r5, -1
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divd r3, r4, r5
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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test_divd_8:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
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divd r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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test_divd_8_constant:
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li r4, 1
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li r5, -1
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divd r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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# TODO(benvanik): integer overflow (=0)
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#test_divd_9:
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# #_ REGISTER_IN r4 0x8000000000000000
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# #_ REGISTER_IN r5 -1
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# divd r3, r4, r5
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# blr
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# #_ REGISTER_OUT r3 0
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# #_ REGISTER_OUT r4 0x8000000000000000
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# #_ REGISTER_OUT r5 -1
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# TODO(benvanik): integer overflow (=0)
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#test_divd_9_constant:
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# li r4, 1
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# sldi r4, r4, 63
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# li r5, -1
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# divd r3, r4, r5
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# blr
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# #_ REGISTER_OUT r3 0
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# #_ REGISTER_OUT r4 0x8000000000000000
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# #_ REGISTER_OUT r5 -1
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