512 lines
7.6 KiB
ArmAsm
512 lines
7.6 KiB
ArmAsm
test_twlt_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 16
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twlt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_twlt_1_constant:
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li r3, 24
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li r4, 16
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twlt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_twlt_2:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 0
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twlt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_twlt_2_constant:
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li r3, 24
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li r4, 0
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twlt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_twle_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 16
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twle r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_twle_1_constant:
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li r3, 24
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li r4, 16
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twle r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_twle_2:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 0
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twle r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_twle_2_constant:
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li r3, 24
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li r4, 0
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twle r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_tweq_1:
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#_ REGISTER_IN r3 0
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#_ REGISTER_IN r4 24
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tweq r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 24
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test_tweq_1_constant:
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li r3, 0
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li r4, 24
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tweq r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 24
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test_tweq_2:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 0
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tweq r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_tweq_2_constant:
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li r3, 24
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li r4, 0
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tweq r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_twge_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 48
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twge r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_twge_1_constant:
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li r3, 24
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li r4, 48
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twge r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_twge_2:
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#_ REGISTER_IN r3 0
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#_ REGISTER_IN r4 48
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twge r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_twge_2_constant:
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li r3, 0
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li r4, 48
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twge r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_twge_3:
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#_ REGISTER_IN r3 -1
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#_ REGISTER_IN r4 0
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twge r3, r4
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blr
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#_ REGISTER_OUT r3 -1
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#_ REGISTER_OUT r4 0
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test_twge_3_constant:
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li r3, -1
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li r4, 0
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twge r3, r4
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blr
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#_ REGISTER_OUT r3 -1
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#_ REGISTER_OUT r4 0
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test_twgt_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 48
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twgt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_twgt_1_constant:
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li r3, 24
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li r4, 48
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twgt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_twgt_2:
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#_ REGISTER_IN r3 0
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#_ REGISTER_IN r4 48
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twgt r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_twgt_2_constant:
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li r3, 0
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li r4, 48
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twgt r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_twgt_3:
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#_ REGISTER_IN r3 -1
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#_ REGISTER_IN r4 0
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twgt r3, r4
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blr
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#_ REGISTER_OUT r3 -1
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#_ REGISTER_OUT r4 0
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test_twgt_3_constant:
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li r3, -1
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li r4, 0
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twgt r3, r4
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blr
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#_ REGISTER_OUT r3 -1
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#_ REGISTER_OUT r4 0
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test_twnl_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 48
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twnl r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_twnl_1_constant:
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li r3, 24
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li r4, 48
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twnl r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_twnl_2:
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#_ REGISTER_IN r3 0
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#_ REGISTER_IN r4 48
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twnl r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_twnl_2_constant:
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li r3, 0
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li r4, 48
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twnl r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_twnl_3:
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#_ REGISTER_IN r3 -1
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#_ REGISTER_IN r4 0
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twnl r3, r4
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blr
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#_ REGISTER_OUT r3 -1
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#_ REGISTER_OUT r4 0
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test_twnl_3_constant:
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li r3, -1
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li r4, 0
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twnl r3, r4
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blr
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#_ REGISTER_OUT r3 -1
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#_ REGISTER_OUT r4 0
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test_twne_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 24
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twne r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 24
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test_twne_1_constant:
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li r3, 24
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li r4, 24
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twne r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 24
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test_twne_2:
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#_ REGISTER_IN r3 0
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#_ REGISTER_IN r4 0
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twne r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0
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test_twne_2_constant:
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li r3, 0
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li r4, 0
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twne r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0
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test_twng_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 16
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twng r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_twng_1_constant:
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li r3, 24
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li r4, 16
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twng r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_twng_2:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 0
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twng r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_twng_2_constant:
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li r3, 24
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li r4, 0
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twng r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_twng_3:
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#_ REGISTER_IN r3 0
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#_ REGISTER_IN r4 -1
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twng r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 -1
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test_twng_3_constant:
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li r3, 0
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li r4, -1
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twng r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 -1
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test_twllt_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 16
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twllt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_twllt_1_constant:
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li r3, 24
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li r4, 16
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twllt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_twllt_2:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 0
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twllt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_twllt_2_constant:
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li r3, 24
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li r4, 0
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twllt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_twlle_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 16
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twlle r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_twlle_1_constant:
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li r3, 24
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li r4, 16
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twlle r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_twlle_2:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 0
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twlle r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_twlle_2_constant:
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li r3, 24
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li r4, 0
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twlle r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_twlge_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 48
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twlge r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_twlge_1_constant:
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li r3, 24
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li r4, 48
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twlge r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_twlge_2:
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#_ REGISTER_IN r3 0
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#_ REGISTER_IN r4 48
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twlge r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_twlge_2_constant:
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li r3, 0
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li r4, 48
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twlge r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_twlgt_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 48
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twlgt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_twlgt_1_constant:
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li r3, 24
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li r4, 48
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twlgt r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_twlgt_2:
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#_ REGISTER_IN r3 0
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#_ REGISTER_IN r4 48
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twlgt r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_twlgt_2_constant:
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li r3, 0
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li r4, 48
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twlgt r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_twlnl_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 48
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twlnl r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_twlnl_1_constant:
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li r3, 24
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li r4, 48
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twlnl r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 48
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test_twlnl_2:
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#_ REGISTER_IN r3 0
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#_ REGISTER_IN r4 48
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twlnl r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_twlnl_2_constant:
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li r3, 0
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li r4, 48
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twlnl r3, r4
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 48
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test_twlng_1:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 16
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twlng r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_twlng_1_constant:
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li r3, 24
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li r4, 16
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twlng r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 16
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test_twlng_2:
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#_ REGISTER_IN r3 24
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#_ REGISTER_IN r4 0
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twlng r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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test_twlng_2_constant:
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li r3, 24
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li r4, 0
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twlng r3, r4
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blr
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#_ REGISTER_OUT r3 24
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#_ REGISTER_OUT r4 0
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