267 lines
5.4 KiB
ArmAsm
267 lines
5.4 KiB
ArmAsm
test_addc_1:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 2
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addc r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 3
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 0
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test_addc_1_constant:
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li r4, 1
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li r5, 2
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addc r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 3
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 0
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test_addc_2:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0
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addc r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 0
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test_addc_2_constant:
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li r4, -1
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li r5, 0
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addc r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 0
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test_addc_3:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 1
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addc r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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#_ REGISTER_OUT r6 1
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test_addc_3_constant:
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li r4, -1
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li r5, 1
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addc r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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#_ REGISTER_OUT r6 1
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test_addc_4:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 123
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addc r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0x000000000000007A
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 123
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#_ REGISTER_OUT r6 1
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test_addc_4_constant:
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li r4, -1
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li r5, 123
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addc r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0x000000000000007A
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 123
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#_ REGISTER_OUT r6 1
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test_addc_5:
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#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
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addc r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
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#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r6 1
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test_addc_5_constant:
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li r5, -1
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srdi r4, r5, 1
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addc r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
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#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r6 1
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test_addc_cr_1:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 2
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addc. r3, r4, r5
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adde r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 3
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 0
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#_ REGISTER_OUT r12 0x40000000
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test_addc_cr_1_constant:
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li r4, 1
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li r5, 2
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addc. r3, r4, r5
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adde r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 3
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 0
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#_ REGISTER_OUT r12 0x40000000
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test_addc_cr_2:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0
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addc. r3, r4, r5
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adde r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 0
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#_ REGISTER_OUT r12 0x80000000
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test_addc_cr_2_constant:
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li r4, -1
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li r5, 0
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addc. r3, r4, r5
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adde r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 0
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#_ REGISTER_OUT r12 0x80000000
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test_addc_cr_3:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 1
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addc. r3, r4, r5
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adde r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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#_ REGISTER_OUT r6 1
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#_ REGISTER_OUT r12 0x20000000
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test_addc_cr_3_constant:
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li r4, -1
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li r5, 1
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addc. r3, r4, r5
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adde r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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#_ REGISTER_OUT r6 1
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#_ REGISTER_OUT r12 0x20000000
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test_addc_cr_4:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 123
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addc. r3, r4, r5
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adde r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0x000000000000007A
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 123
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#_ REGISTER_OUT r6 1
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#_ REGISTER_OUT r12 0x40000000
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test_addc_cr_4_constant:
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li r4, -1
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li r5, 123
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addc. r3, r4, r5
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adde r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0x000000000000007A
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 123
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#_ REGISTER_OUT r6 1
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#_ REGISTER_OUT r12 0x40000000
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test_addc_cr_5:
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#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
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addc. r3, r4, r5
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adde r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
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#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r6 1
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#_ REGISTER_OUT r12 0x80000000
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test_addc_cr_5_constant:
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li r5, -1
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srdi r4, r5, 1
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addc. r3, r4, r5
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adde r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
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#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r6 1
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#_ REGISTER_OUT r12 0x80000000
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test_addc_cr_6:
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#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 2
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addc. r3, r4, r5
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adde r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0x8000000000000001
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#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 1
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#_ REGISTER_OUT r12 0x40000000
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test_addc_cr_6_constant:
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li r4, -1
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srdi r4, r4, 1
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li r5, 2
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addc. r3, r4, r5
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adde r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0x8000000000000001
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#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 1
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#_ REGISTER_OUT r12 0x40000000
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