259 lines
9.7 KiB
ArmAsm
259 lines
9.7 KiB
ArmAsm
# vpkd3d128 dest, src, type, mask, shift
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# type:
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# 0 = PACK_TYPE_D3DCOLOR
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# 1 = PACK_TYPE_SHORT_2
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# 2 = PACK_TYPE_2_10_10_10
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# 3 = PACK_TYPE_FLOAT16_2
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# 4 = PACK_TYPE_SHORT_4
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# 5 = PACK_TYPE_FLOAT16_4
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# mask:
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# must not be zero
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# 1 = 00000000 00000000 00000000 FFFFFFFF
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# 2 = 00000000 00000000 FFFFFFFF FFFFFFFF
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# 3 = same as 2? except mask3/shift3
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# shift:
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# 0 = no shift
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# 1 = shift left by one word
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# 2 ...
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# 3 ...
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# special case: mask3/shift3 = 00000000 00000000 00000000 FFFFFFFF
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# vpkd3d128 is broken in binutils, so these are hand coded
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test_vpkd3d128_d3dcolor_invalid_0:
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#_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 0, 1, 0
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.long 0x18811E10
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blr
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#_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000]
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test_vpkd3d128_d3dcolor_invalid_1:
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#_ REGISTER_IN v3 [40800000, 40000000, C2F60000, 4B3BDF83]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 0, 1, 0
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.long 0x18811E10
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blr
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#_ REGISTER_OUT v3 [40800000, 40000000, C2F60000, 4B3BDF83]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, FFFF0000]
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test_vpkd3d128_d3dcolor_invalid_2:
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#_ REGISTER_IN v3 [40800000, 40000000, C2F60000, FFFFFFFF]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 0, 1, 0
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.long 0x18811E10
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blr
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#_ REGISTER_OUT v3 [40800000, 40000000, C2F60000, FFFFFFFF]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00FF0000]
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test_vpkd3d128_d3dcolor_1_0:
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#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 0, 1, 0
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.long 0x18811E10
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blr
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#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
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test_vpkd3d128_d3dcolor_1_1:
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#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 0, 1, 1
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.long 0x18811E50
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blr
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#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 04010203, CDCDCDCD]
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test_vpkd3d128_d3dcolor_1_2:
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#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 0, 1, 2
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.long 0x18811E90
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blr
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#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_OUT v4 [CDCDCDCD, 04010203, CDCDCDCD, CDCDCDCD]
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test_vpkd3d128_d3dcolor_1_3:
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#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 0, 1, 3
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.long 0x18811ED0
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blr
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#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_OUT v4 [04010203, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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test_vpkd3d128_d3dcolor_2_0:
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#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 0, 2, 0
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.long 0x18821E10
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blr
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#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 00000000, 04010203]
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test_vpkd3d128_d3dcolor_2_1:
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#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 0, 2, 1
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.long 0x18821E50
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blr
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#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_OUT v4 [CDCDCDCD, 00000000, 04010203, CDCDCDCD]
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test_vpkd3d128_d3dcolor_2_2:
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#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 0, 2, 2
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.long 0x18821E90
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blr
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#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_OUT v4 [00000000, 04010203, CDCDCDCD, CDCDCDCD]
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test_vpkd3d128_d3dcolor_2_3:
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#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 0, 2, 3
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.long 0x18821ED0
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blr
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#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_OUT v4 [04010203, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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test_vpkd3d128_d3dcolor_3_0:
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#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 0, 3, 0
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.long 0x18831E10
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blr
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#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 00000000, 04010203]
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test_vpkd3d128_d3dcolor_3_1:
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#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 0, 3, 1
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.long 0x18831E50
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blr
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#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_OUT v4 [CDCDCDCD, 00000000, 04010203, CDCDCDCD]
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test_vpkd3d128_d3dcolor_3_2:
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#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 0, 3, 2
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.long 0x18831E90
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blr
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#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_OUT v4 [00000000, 04010203, CDCDCDCD, CDCDCDCD]
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test_vpkd3d128_d3dcolor_3_3:
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#_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 0, 3, 3
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.long 0x18831ED0
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blr
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#_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000]
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test_vpkd3d128_short2_invalid_0:
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#_ REGISTER_IN v3 [43817E00, C37CFC00, 42A23EC8, 403DB757]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 1, 1, 0
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.long 0x18851E10
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blr
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#_ REGISTER_OUT v3 [43817E00, C37CFC00, 42A23EC8, 403DB757]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001]
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test_vpkd3d128_short2_invalid_1:
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#_ REGISTER_IN v3 [412FDF00, C09FBE00, 42A23EC8, 403DB757]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 1, 1, 0
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.long 0x18851E10
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blr
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#_ REGISTER_OUT v3 [412FDF00, C09FBE00, 42A23EC8, 403DB757]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001]
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test_vpkd3d128_short2_0:
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#_ REGISTER_IN v3 [40407FFF, 403F8001, 00000000, 00000000]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 1, 1, 0
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.long 0x18851E10
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blr
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#_ REGISTER_OUT v3 [40407FFF, 403F8001, 00000000, 00000000]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001]
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test_vpkd3d128_short2_1:
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#_ REGISTER_IN v3 [40404000, 403FC000, 40400003, 403F8001]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 1, 1, 0
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.long 0x18851E10
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blr
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#_ REGISTER_OUT v3 [40404000, 403FC000, 40400003, 403F8001]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 4000C000]
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test_vpkd3d128_short2_2:
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#_ REGISTER_IN v3 [4040FFFE, 403FF333, 42A23EC8, 403DB757]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 1, 1, 0
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.long 0x18851E10
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blr
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#_ REGISTER_OUT v3 [4040FFFE, 403FF333, 42A23EC8, 403DB757]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFFF333]
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test_vpkd3d128_short4_0:
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# v3 = [1.5, -1.5, 1.5, -1.5]
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#_ REGISTER_IN v3 [403F8001, 403FFFF8, 4040007F, 40400000]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 4, 2, 0
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.long 0x18921E10
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blr
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#_ REGISTER_OUT v3 [403F8001, 403FFFF8, 4040007F, 40400000]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 8001FFF8, 007F0000]
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test_vpkd3d128_uint_2101010_0:
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#_ REGISTER_IN v3 [B8FF8000, B8FF8000, C04001FF, 4E9A5A5A]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 2, 1, 0
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.long 0x18891E10
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blr
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#_ REGISTER_OUT v3 [B8FF8000, B8FF8000, C04001FF, 4E9A5A5A]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, E0180601]
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test_vpkd3d128_uint_2101010_1:
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#_ REGISTER_IN v3 [42C80000, C2C80000, 40400000, 3F800000]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 2, 1, 0
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.long 0x18891E10
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blr
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#_ REGISTER_OUT v3 [42C80000, C2C80000, 40400000, 3F800000]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 000805FF]
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test_vpkd3d128_uint_2101010_2:
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#_ REGISTER_IN v3 [3F000000, BF000000, 3F800000, 00000000]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 2, 1, 0
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.long 0x18891E10
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blr
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#_ REGISTER_OUT v3 [3F000000, BF000000, 3F800000, 00000000]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 20180601]
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test_vpkd3d128_float16_2_invalid_0:
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#_ REGISTER_IN v3 [3FC00000, BFC00000, 42A23EC8, 403DB757]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 3, 1, 0
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.long 0x188D1E10
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blr
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#_ REGISTER_OUT v3 [3FC00000, BFC00000, 42A23EC8, 403DB757]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 3E00BE00]
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test_vpkd3d128_float16_2_0:
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#_ REGISTER_IN v3 [3F000000, BF000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 3, 1, 0
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.long 0x188D1E10
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blr
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#_ REGISTER_OUT v3 [3F000000, BF000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 3800B800]
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test_vpkd3d128_float16_4_invalid_0:
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#_ REGISTER_IN v3 [3FC00000, BFC00000, 3FC00000, BFC00000]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 5, 2, 0
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.long 0x18961E10
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blr
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#_ REGISTER_OUT v3 [3FC00000, BFC00000, 3FC00000, BFC00000]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 3E00BE00, 3E00BE00]
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test_vpkd3d128_float16_4_0:
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#_ REGISTER_IN v3 [3F000000, BF000000, 3F800000, BF800000]
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#_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
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# vpkd3d128 v4, v3, 5, 2, 0
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.long 0x18961E10
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blr
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#_ REGISTER_OUT v3 [3F000000, BF000000, 3F800000, BF800000]
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#_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 3800B800, 3C00BC00]
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