086a070fa9
According to the integral promotion rules https://eel.is/c++draft/conv.prom#5.sentence-1 bit fields can be promoted to `int` if it's wide enough to store their value, and then otherwise, to `unsigned int`. Hopefully fixes Clang building (the `width_div_8` case).
380 lines
12 KiB
C++
380 lines
12 KiB
C++
/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2014 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#include "xenia/gpu/texture_info.h"
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#include <algorithm>
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#include <cmath>
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#include <cstring>
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#include "xenia/base/logging.h"
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#include "xenia/base/math.h"
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#include "xenia/base/memory.h"
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#include "xenia/base/xxhash.h"
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namespace xe {
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namespace gpu {
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using namespace xe::gpu::xenos;
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bool TextureInfo::Prepare(const xe_gpu_texture_fetch_t& fetch,
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TextureInfo* out_info) {
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// https://msdn.microsoft.com/en-us/library/windows/desktop/cc308051(v=vs.85).aspx
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// a2xx_sq_surfaceformat
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std::memset(out_info, 0, sizeof(TextureInfo));
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auto& info = *out_info;
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info.format = fetch.format;
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info.endianness = fetch.endianness;
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info.dimension = fetch.dimension;
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info.width = info.height = info.depth = 0;
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info.is_stacked = false;
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switch (info.dimension) {
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case xenos::DataDimension::k1D:
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// we treat 1D textures as 2D
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info.dimension = DataDimension::k2DOrStacked;
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info.width = fetch.size_1d.width;
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assert_true(!fetch.stacked);
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break;
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case xenos::DataDimension::k2DOrStacked:
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info.width = fetch.size_2d.width;
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info.height = fetch.size_2d.height;
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if (fetch.stacked) {
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info.depth = fetch.size_2d.stack_depth;
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info.is_stacked = true;
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}
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break;
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case xenos::DataDimension::k3D:
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info.width = fetch.size_3d.width;
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info.height = fetch.size_3d.height;
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info.depth = fetch.size_3d.depth;
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assert_true(!fetch.stacked);
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break;
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case xenos::DataDimension::kCube:
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info.width = fetch.size_2d.width;
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info.height = fetch.size_2d.height;
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assert_true(fetch.size_2d.stack_depth == 5);
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info.depth = fetch.size_2d.stack_depth;
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assert_true(!fetch.stacked);
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break;
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default:
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assert_unhandled_case(info.dimension);
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break;
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}
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info.pitch = fetch.pitch << 5;
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info.mip_min_level = fetch.mip_min_level;
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info.mip_max_level =
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std::max(uint32_t(fetch.mip_min_level), uint32_t(fetch.mip_max_level));
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info.is_tiled = fetch.tiled;
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info.has_packed_mips = fetch.packed_mips;
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info.extent = TextureExtent::Calculate(out_info, true);
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info.SetupMemoryInfo(fetch.base_address << 12, fetch.mip_address << 12);
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// We've gotten this far and mip_address is zero, assume no extra mips.
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if (info.mip_max_level > 0 && !info.memory.mip_address) {
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info.mip_max_level = 0;
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}
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assert_true(info.mip_min_level <= info.mip_max_level);
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return true;
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}
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bool TextureInfo::PrepareResolve(uint32_t physical_address,
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xenos::TextureFormat format,
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xenos::Endian endian, uint32_t pitch,
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uint32_t width, uint32_t height,
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uint32_t depth, TextureInfo* out_info) {
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assert_true(width > 0);
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assert_true(height > 0);
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std::memset(out_info, 0, sizeof(TextureInfo));
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auto& info = *out_info;
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info.format = format;
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info.endianness = endian;
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info.dimension = xenos::DataDimension::k2DOrStacked;
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info.width = width - 1;
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info.height = height - 1;
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info.depth = depth - 1;
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info.pitch = pitch;
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info.mip_min_level = 0;
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info.mip_max_level = 0;
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info.is_tiled = true;
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info.has_packed_mips = false;
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info.extent = TextureExtent::Calculate(out_info, true);
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info.SetupMemoryInfo(physical_address, 0);
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return true;
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}
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uint32_t TextureInfo::GetMaxMipLevels() const {
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return 1 + xe::log2_floor(std::max({width + 1, height + 1, depth + 1}));
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}
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const TextureExtent TextureInfo::GetMipExtent(uint32_t mip,
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bool is_guest) const {
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if (mip == 0) {
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return extent;
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}
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uint32_t mip_width, mip_height;
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if (is_guest) {
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mip_width = xe::next_pow2(width + 1) >> mip;
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mip_height = xe::next_pow2(height + 1) >> mip;
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} else {
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mip_width = std::max(1u, (width + 1) >> mip);
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mip_height = std::max(1u, (height + 1) >> mip);
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}
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return TextureExtent::Calculate(format_info(), mip_width, mip_height,
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depth + 1, is_tiled, is_guest);
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}
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void TextureInfo::GetMipSize(uint32_t mip, uint32_t* out_width,
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uint32_t* out_height) const {
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assert_not_null(out_width);
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assert_not_null(out_height);
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if (mip == 0) {
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*out_width = width + 1;
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*out_height = height + 1;
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return;
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}
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uint32_t width_pow2 = xe::next_pow2(width + 1);
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uint32_t height_pow2 = xe::next_pow2(height + 1);
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*out_width = std::max(width_pow2 >> mip, 1u);
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*out_height = std::max(height_pow2 >> mip, 1u);
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}
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uint32_t TextureInfo::GetMipLocation(uint32_t mip, uint32_t* offset_x,
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uint32_t* offset_y, bool is_guest) const {
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if (mip == 0) {
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// Short-circuit. Mip 0 is always stored in base_address.
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if (!has_packed_mips) {
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*offset_x = 0;
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*offset_y = 0;
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} else {
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GetPackedTileOffset(0, offset_x, offset_y);
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}
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return memory.base_address;
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}
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if (!memory.mip_address) {
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// Short-circuit. There is no mip data.
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*offset_x = 0;
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*offset_y = 0;
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return 0;
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}
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uint32_t address_base, address_offset;
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address_base = memory.mip_address;
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address_offset = 0;
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auto bytes_per_block = format_info()->bytes_per_block();
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if (!has_packed_mips) {
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for (uint32_t i = 1; i < mip; i++) {
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address_offset +=
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GetMipExtent(i, is_guest).all_blocks() * bytes_per_block;
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}
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*offset_x = 0;
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*offset_y = 0;
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return address_base + address_offset;
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}
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uint32_t width_pow2 = xe::next_pow2(width + 1);
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uint32_t height_pow2 = xe::next_pow2(height + 1);
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// Walk forward to find the address of the mip.
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uint32_t packed_mip_base = 1;
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for (uint32_t i = packed_mip_base; i < mip; i++, packed_mip_base++) {
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uint32_t mip_width = std::max(width_pow2 >> i, 1u);
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uint32_t mip_height = std::max(height_pow2 >> i, 1u);
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if (std::min(mip_width, mip_height) <= 16) {
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// We've reached the point where the mips are packed into a single tile.
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break;
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}
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address_offset += GetMipExtent(i, is_guest).all_blocks() * bytes_per_block;
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}
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// Now, check if the mip is packed at an offset.
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GetPackedTileOffset(width_pow2 >> mip, height_pow2 >> mip, format_info(),
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mip - packed_mip_base, offset_x, offset_y);
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return address_base + address_offset;
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}
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bool TextureInfo::GetPackedTileOffset(uint32_t width, uint32_t height,
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const FormatInfo* format_info,
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int packed_tile, uint32_t* offset_x,
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uint32_t* offset_y) {
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// Tile size is 32x32, and once textures go <=16 they are packed into a
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// single tile together. The math here is insane. Most sourced
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// from graph paper and looking at dds dumps.
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// 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
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// 0 +.4x4.+ +.....8x8.....+ +............16x16............+
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// 1 +.4x4.+ +.....8x8.....+ +............16x16............+
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// 2 +.4x4.+ +.....8x8.....+ +............16x16............+
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// 3 +.4x4.+ +.....8x8.....+ +............16x16............+
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// 4 x +.....8x8.....+ +............16x16............+
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// 5 +.....8x8.....+ +............16x16............+
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// 6 +.....8x8.....+ +............16x16............+
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// 7 +.....8x8.....+ +............16x16............+
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// 8 2x2 +............16x16............+
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// 9 2x2 +............16x16............+
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// 0 +............16x16............+
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// ... .....
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// This only works for square textures, or textures that are some non-pot
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// <= square. As soon as the aspect ratio goes weird, the textures start to
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// stretch across tiles.
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//
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// The 2x2 and 1x1 squares are packed in their specific positions because
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// each square is the size of at least one block (which is 4x4 pixels max)
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//
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// if (tile_aligned(w) > tile_aligned(h)) {
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// // wider than tall, so packed horizontally
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// } else if (tile_aligned(w) < tile_aligned(h)) {
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// // taller than wide, so packed vertically
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// } else {
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// square
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// }
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// It's important to use logical sizes here, as the input sizes will be
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// for the entire packed tile set, not the actual texture.
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// The minimum dimension is what matters most: if either width or height
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// is <= 16 this mode kicks in.
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uint32_t log2_width = xe::log2_ceil(width);
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uint32_t log2_height = xe::log2_ceil(height);
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if (std::min(log2_width, log2_height) > 4) {
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// Too big, not packed.
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*offset_x = 0;
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*offset_y = 0;
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return false;
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}
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// Find the block offset of the mip.
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if (packed_tile < 3) {
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if (log2_width > log2_height) {
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// Wider than tall. Laid out vertically.
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*offset_x = 0;
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*offset_y = 16 >> packed_tile;
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} else {
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// Taller than wide. Laid out horizontally.
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*offset_x = 16 >> packed_tile;
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*offset_y = 0;
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}
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} else {
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if (log2_width > log2_height) {
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// Wider than tall. Laid out vertically.
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*offset_x = 16 >> (packed_tile - 2);
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*offset_y = 0;
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} else {
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// Taller than wide. Laid out horizontally.
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*offset_x = 0;
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*offset_y = 16 >> (packed_tile - 2);
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}
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}
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*offset_x /= format_info->block_width;
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*offset_y /= format_info->block_height;
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return true;
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}
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bool TextureInfo::GetPackedTileOffset(int packed_tile, uint32_t* offset_x,
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uint32_t* offset_y) const {
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if (!has_packed_mips) {
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*offset_x = 0;
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*offset_y = 0;
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return false;
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}
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return GetPackedTileOffset(xe::next_pow2(width + 1),
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xe::next_pow2(height + 1), format_info(),
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packed_tile, offset_x, offset_y);
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}
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uint64_t TextureInfo::hash() const {
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return XXH3_64bits(this, sizeof(TextureInfo));
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}
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void TextureInfo::SetupMemoryInfo(uint32_t base_address, uint32_t mip_address) {
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uint32_t bytes_per_block = format_info()->bytes_per_block();
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memory.base_address = 0;
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memory.base_size = 0;
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memory.mip_address = 0;
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memory.mip_size = 0;
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if (mip_min_level == 0 && base_address) {
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// There is a base mip level.
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memory.base_address = base_address;
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memory.base_size = GetMipExtent(0, true).visible_blocks() * bytes_per_block;
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}
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if (mip_min_level == 0 && mip_max_level == 0) {
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// Sort circuit. Only one mip.
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return;
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}
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if (mip_min_level == 0 && base_address == mip_address) {
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// TODO(gibbed): This doesn't actually make any sense. Force only one mip.
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// Offending title issues: #26, #45
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return;
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}
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if (mip_min_level > 0) {
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if ((base_address && !mip_address) || (base_address == mip_address)) {
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// Mip data is actually at base address?
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mip_address = base_address;
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base_address = 0;
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} else if (!base_address && mip_address) {
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// Nothing needs to be done.
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} else {
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// WTF?
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assert_always();
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}
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}
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memory.mip_address = mip_address;
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if (!has_packed_mips) {
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for (uint32_t mip = std::max(1u, mip_min_level); mip < mip_max_level;
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mip++) {
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memory.mip_size += GetMipExtent(mip, true).all_blocks() * bytes_per_block;
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}
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memory.mip_size +=
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GetMipExtent(mip_max_level, true).visible_blocks() * bytes_per_block;
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return;
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}
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uint32_t width_pow2 = xe::next_pow2(width + 1);
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uint32_t height_pow2 = xe::next_pow2(height + 1);
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// Walk forward to find the address of the mip.
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uint32_t packed_mip_base = std::max(1u, mip_min_level);
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for (uint32_t mip = packed_mip_base; mip < mip_max_level;
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mip++, packed_mip_base++) {
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uint32_t mip_width = std::max(width_pow2 >> mip, 1u);
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uint32_t mip_height = std::max(height_pow2 >> mip, 1u);
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if (std::min(mip_width, mip_height) <= 16) {
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// We've reached the point where the mips are packed into a single tile.
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break;
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}
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memory.mip_size += GetMipExtent(mip, true).all_blocks() * bytes_per_block;
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}
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}
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} // namespace gpu
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} // namespace xe
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