580 lines
12 KiB
ArmAsm
580 lines
12 KiB
ArmAsm
test_adde_1:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 2
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 3
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 0
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test_adde_1_constant:
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li r4, 1
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li r5, 2
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 3
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 0
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test_adde_2:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 2
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 4
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 0
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test_adde_2_constant:
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li r4, 1
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li r5, 2
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 4
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 0
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test_adde_3:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 0
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test_adde_3_constant:
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li r4, -1
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li r5, 0
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 0
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test_adde_4:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 1
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test_adde_4_constant:
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li r4, -1
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li r5, 0
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 1
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test_adde_5:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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#_ REGISTER_OUT r6 1
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test_adde_5_constant:
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li r4, -1
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li r5, 1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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#_ REGISTER_OUT r6 1
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test_adde_6:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 1
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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#_ REGISTER_OUT r6 1
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test_adde_6_constant:
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li r4, -1
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li r5, 1
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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#_ REGISTER_OUT r6 1
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test_adde_7:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 123
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0x000000000000007A
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 123
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#_ REGISTER_OUT r6 1
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test_adde_7_constant:
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li r4, -1
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li r5, 123
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0x000000000000007A
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 123
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#_ REGISTER_OUT r6 1
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test_adde_8:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 123
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0x000000000000007B
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 123
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#_ REGISTER_OUT r6 1
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test_adde_8_constant:
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li r4, -1
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li r5, 123
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0x000000000000007B
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 123
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#_ REGISTER_OUT r6 1
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test_adde_9:
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#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
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#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r6 1
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test_adde_9_constant:
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li r5, -1
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srdi r4, r5, 1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
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#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r6 1
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test_adde_10:
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#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r6 1
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test_adde_10_constant:
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li r5, -1
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srdi r4, r5, 1
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r6 1
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test_adde_cr_1:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 2
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adde. r3, r4, r5
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mfcr r11
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adde. r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 3
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 0
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#_ REGISTER_OUT r11 0x40000000
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#_ REGISTER_OUT r12 0x20000000
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test_adde_cr_1_constant:
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li r4, 1
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li r5, 2
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adde. r3, r4, r5
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mfcr r11
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adde. r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 3
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 0
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#_ REGISTER_OUT r11 0x40000000
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#_ REGISTER_OUT r12 0x20000000
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test_adde_cr_2:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 2
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde. r3, r4, r5
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mfcr r11
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adde. r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 4
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 0
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#_ REGISTER_OUT r11 0x40000000
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#_ REGISTER_OUT r12 0x20000000
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test_adde_cr_2_constant:
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li r4, 1
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li r5, 2
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde. r3, r4, r5
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mfcr r11
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adde. r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 4
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 0
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#_ REGISTER_OUT r11 0x40000000
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#_ REGISTER_OUT r12 0x20000000
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test_adde_cr_3:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0
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adde. r3, r4, r5
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mfcr r11
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adde. r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 0
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#_ REGISTER_OUT r11 0x80000000
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#_ REGISTER_OUT r12 0x20000000
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test_adde_cr_3_constant:
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li r4, -1
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li r5, 0
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adde. r3, r4, r5
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mfcr r11
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adde. r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 0
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#_ REGISTER_OUT r11 0x80000000
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#_ REGISTER_OUT r12 0x20000000
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test_adde_cr_4:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde. r3, r4, r5
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mfcr r11
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adde. r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 1
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#_ REGISTER_OUT r11 0x20000000
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#_ REGISTER_OUT r12 0x40000000
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test_adde_cr_4_constant:
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li r4, -1
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li r5, 0
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde. r3, r4, r5
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mfcr r11
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adde. r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 1
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#_ REGISTER_OUT r11 0x20000000
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#_ REGISTER_OUT r12 0x40000000
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test_adde_cr_5:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 1
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adde. r3, r4, r5
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mfcr r11
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adde. r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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#_ REGISTER_OUT r6 1
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#_ REGISTER_OUT r11 0x20000000
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#_ REGISTER_OUT r12 0x40000000
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test_adde_cr_5_constant:
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li r4, -1
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li r5, 1
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adde. r3, r4, r5
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mfcr r11
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adde. r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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#_ REGISTER_OUT r6 1
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#_ REGISTER_OUT r11 0x20000000
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#_ REGISTER_OUT r12 0x40000000
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test_adde_cr_6:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 1
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde. r3, r4, r5
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mfcr r11
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adde. r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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#_ REGISTER_OUT r6 1
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#_ REGISTER_OUT r11 0x40000000
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#_ REGISTER_OUT r12 0x40000000
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test_adde_cr_6_constant:
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li r4, -1
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li r5, 1
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde. r3, r4, r5
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mfcr r11
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adde. r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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#_ REGISTER_OUT r6 1
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#_ REGISTER_OUT r11 0x40000000
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#_ REGISTER_OUT r12 0x40000000
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test_adde_cr_7:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 123
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adde. r3, r4, r5
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mfcr r11
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adde. r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0x000000000000007A
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 123
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#_ REGISTER_OUT r6 1
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#_ REGISTER_OUT r11 0x40000000
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#_ REGISTER_OUT r12 0x40000000
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test_adde_cr_7_constant:
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li r4, -1
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li r5, 123
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adde. r3, r4, r5
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mfcr r11
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adde. r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0x000000000000007A
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 123
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#_ REGISTER_OUT r6 1
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#_ REGISTER_OUT r11 0x40000000
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#_ REGISTER_OUT r12 0x40000000
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test_adde_cr_8:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 123
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde. r3, r4, r5
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mfcr r11
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adde. r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0x000000000000007B
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 123
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#_ REGISTER_OUT r6 1
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#_ REGISTER_OUT r11 0x40000000
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#_ REGISTER_OUT r12 0x40000000
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test_adde_cr_8_constant:
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li r4, -1
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li r5, 123
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde. r3, r4, r5
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mfcr r11
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adde. r6, r0, r0
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mfcr r12
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blr
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#_ REGISTER_OUT r3 0x000000000000007B
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 123
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#_ REGISTER_OUT r6 1
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#_ REGISTER_OUT r11 0x40000000
|
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#_ REGISTER_OUT r12 0x40000000
|
|
|
|
test_adde_cr_9:
|
|
#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
|
|
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
|
|
adde. r3, r4, r5
|
|
mfcr r11
|
|
adde. r6, r0, r0
|
|
mfcr r12
|
|
blr
|
|
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
|
|
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
|
|
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
|
|
#_ REGISTER_OUT r6 1
|
|
#_ REGISTER_OUT r11 0x80000000
|
|
#_ REGISTER_OUT r12 0x40000000
|
|
|
|
test_adde_cr_9_constant:
|
|
li r5, -1
|
|
srdi r4, r5, 1
|
|
adde. r3, r4, r5
|
|
mfcr r11
|
|
adde. r6, r0, r0
|
|
mfcr r12
|
|
blr
|
|
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
|
|
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
|
|
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
|
|
#_ REGISTER_OUT r6 1
|
|
#_ REGISTER_OUT r11 0x80000000
|
|
#_ REGISTER_OUT r12 0x40000000
|
|
|
|
test_adde_cr_10:
|
|
#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
|
|
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
|
|
xor r3, r3, r3
|
|
not r3, r3
|
|
addic r3, r3, 1 # CA=1
|
|
adde. r3, r4, r5
|
|
mfcr r11
|
|
adde. r6, r0, r0
|
|
mfcr r12
|
|
blr
|
|
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
|
|
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
|
|
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
|
|
#_ REGISTER_OUT r6 1
|
|
#_ REGISTER_OUT r11 0x80000000
|
|
#_ REGISTER_OUT r12 0x40000000
|
|
|
|
test_adde_cr_10_constant:
|
|
li r5, -1
|
|
srdi r4, r5, 1
|
|
xor r3, r3, r3
|
|
not r3, r3
|
|
addic r3, r3, 1 # CA=1
|
|
adde. r3, r4, r5
|
|
mfcr r11
|
|
adde. r6, r0, r0
|
|
mfcr r12
|
|
blr
|
|
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
|
|
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
|
|
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
|
|
#_ REGISTER_OUT r6 1
|
|
#_ REGISTER_OUT r11 0x80000000
|
|
#_ REGISTER_OUT r12 0x40000000
|