200 lines
3.9 KiB
ArmAsm
200 lines
3.9 KiB
ArmAsm
test_srw_1:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 0
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 0
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test_srw_1_constant:
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li r4, 1
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li r5, 0
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 0
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test_srw_2:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x00000000FFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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test_srw_2_constant:
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li r4, -1
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li r5, 0
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x00000000FFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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test_srw_3:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 1
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x000000007FFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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test_srw_3_constant:
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li r4, -1
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li r5, 1
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x000000007FFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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test_srw_4:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 63
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 63
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test_srw_4_constant:
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li r4, -1
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li r5, 63
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 63
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test_srw_5:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 64
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x00000000FFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 64
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test_srw_5_constant:
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li r4, -1
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li r5, 64
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x00000000FFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 64
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test_srw_6:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 100
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 100
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test_srw_6_constant:
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li r4, -1
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li r5, 100
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 100
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test_srw_7:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 30
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x0000000000000003
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 30
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test_srw_7_constant:
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li r4, -1
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li r5, 30
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x0000000000000003
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 30
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test_srw_8:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 31
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x0000000000000001
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 31
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test_srw_8_constant:
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li r4, -1
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li r5, 31
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x0000000000000001
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 31
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test_srw_9:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 32
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 32
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test_srw_9_constant:
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li r4, -1
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li r5, 32
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 32
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test_srw_10:
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#_ REGISTER_IN r4 0x0000000090003000
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#_ REGISTER_IN r5 36
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0x0000000090003000
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#_ REGISTER_OUT r5 36
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test_srw_10_constant:
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lis r4, 0x9000
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ori r4, r4, 0x3000
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li r5, 36
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFF90003000
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#_ REGISTER_OUT r5 36
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test_srw_11:
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#_ REGISTER_IN r4 0x00000000B0043001
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#_ REGISTER_IN r5 4
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x000000000B004300
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#_ REGISTER_OUT r4 0x00000000B0043001
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#_ REGISTER_OUT r5 4
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test_srw_11_constant:
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lis r4, 0xB004
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ori r4, r4, 0x3001
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li r5, 4
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srw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x000000000B004300
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#_ REGISTER_OUT r4 0xFFFFFFFFB0043001
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#_ REGISTER_OUT r5 4
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