457 lines
14 KiB
C++
457 lines
14 KiB
C++
/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2017 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#ifndef XENIA_GPU_REGISTERS_H_
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#define XENIA_GPU_REGISTERS_H_
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#include <cstdint>
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#include <cstdlib>
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#include "xenia/base/bit_field.h"
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#include "xenia/gpu/xenos.h"
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// Most registers can be found from:
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// https://github.com/UDOOboard/Kernel_Unico/blob/master/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h
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namespace xe {
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namespace gpu {
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enum Register {
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#define XE_GPU_REGISTER(index, type, name) XE_GPU_REG_##name = index,
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#include "xenia/gpu/register_table.inc"
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#undef XE_GPU_REGISTER
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};
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namespace reg {
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/*******************************************************************************
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___ ___ _ _ _____ ___ ___ _
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/ __/ _ \| \| |_ _| _ \/ _ \| |
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| (_| (_) | .` | | | | / (_) | |__
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\___\___/|_|\_| |_| |_|_\\___/|____|
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*******************************************************************************/
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union COHER_STATUS_HOST {
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xe::bf<uint32_t, 0, 8> matching_contexts;
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xe::bf<uint32_t, 8, 1> rb_copy_dest_base_ena;
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xe::bf<uint32_t, 9, 1> dest_base_0_ena;
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xe::bf<uint32_t, 10, 1> dest_base_1_ena;
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xe::bf<uint32_t, 11, 1> dest_base_2_ena;
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xe::bf<uint32_t, 12, 1> dest_base_3_ena;
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xe::bf<uint32_t, 13, 1> dest_base_4_ena;
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xe::bf<uint32_t, 14, 1> dest_base_5_ena;
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xe::bf<uint32_t, 15, 1> dest_base_6_ena;
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xe::bf<uint32_t, 16, 1> dest_base_7_ena;
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xe::bf<uint32_t, 24, 1> vc_action_ena;
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xe::bf<uint32_t, 25, 1> tc_action_ena;
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xe::bf<uint32_t, 26, 1> pglb_action_ena;
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xe::bf<uint32_t, 31, 1> status;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_COHER_STATUS_HOST;
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};
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union WAIT_UNTIL {
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xe::bf<uint32_t, 1, 1> wait_re_vsync;
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xe::bf<uint32_t, 2, 1> wait_fe_vsync;
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xe::bf<uint32_t, 3, 1> wait_vsync;
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xe::bf<uint32_t, 4, 1> wait_dsply_id0;
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xe::bf<uint32_t, 5, 1> wait_dsply_id1;
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xe::bf<uint32_t, 6, 1> wait_dsply_id2;
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xe::bf<uint32_t, 10, 1> wait_cmdfifo;
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xe::bf<uint32_t, 14, 1> wait_2d_idle;
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xe::bf<uint32_t, 15, 1> wait_3d_idle;
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xe::bf<uint32_t, 16, 1> wait_2d_idleclean;
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xe::bf<uint32_t, 17, 1> wait_3d_idleclean;
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xe::bf<uint32_t, 20, 4> cmdfifo_entries;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_WAIT_UNTIL;
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};
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/*******************************************************************************
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___ ___ ___ _ _ ___ _ _ ___ ___ ___
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/ __| __/ _ \| | | | __| \| |/ __| __| _ \
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\__ \ _| (_) | |_| | _|| .` | (__| _|| /
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|___/___\__\_\\___/|___|_|\_|\___|___|_|_\
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*******************************************************************************/
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union SQ_PROGRAM_CNTL {
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// Note from a2xx.xml:
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// Only 0x3F worth of valid register values for VS_NUM_REG and PS_NUM_REG, but
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// high bit is set to indicate "0 registers used".
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xe::bf<uint32_t, 0, 8> vs_num_reg;
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xe::bf<uint32_t, 8, 8> ps_num_reg;
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xe::bf<uint32_t, 16, 1> vs_resource;
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xe::bf<uint32_t, 17, 1> ps_resource;
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xe::bf<uint32_t, 18, 1> param_gen;
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xe::bf<uint32_t, 19, 1> gen_index_pix;
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xe::bf<uint32_t, 20, 4> vs_export_count;
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xe::bf<xenos::VertexShaderExportMode, 24, 3> vs_export_mode;
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xe::bf<uint32_t, 27, 4> ps_export_mode;
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xe::bf<uint32_t, 31, 1> gen_index_vtx;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_SQ_PROGRAM_CNTL;
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};
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union SQ_CONTEXT_MISC {
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xe::bf<uint32_t, 0, 1> inst_pred_optimize;
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xe::bf<uint32_t, 1, 1> sc_output_screen_xy;
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xe::bf<xenos::SampleControl, 2, 2> sc_sample_cntl;
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xe::bf<uint32_t, 8, 8> param_gen_pos;
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xe::bf<uint32_t, 16, 1> perfcounter_ref;
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xe::bf<uint32_t, 17, 1> yeild_optimize; // sic
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xe::bf<uint32_t, 18, 1> tx_cache_sel;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_SQ_CONTEXT_MISC;
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};
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/*******************************************************************************
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__ _____ ___ _____ _____ __
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\ \ / / __| _ \_ _| __\ \/ /
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\ V /| _|| / | | | _| > <
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\_/ |___|_|_\ |_| |___/_/\_\
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___ ___ ___ _ _ ___ ___ ___ _ _ _ ___
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/ __| _ \/ _ \| | | | _ \ __| _ \ /_\ | \| | \
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| (_ | / (_) | |_| | _/ _|| / / _ \| .` | |) |
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\___|_|_\\___/ \___/|_| |___|_|_\ /_/ \_\_|\_|___/
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_____ ___ ___ ___ ___ _ _ _ _____ ___ ___
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|_ _| __/ __/ __| __| | | | /_\_ _/ _ \| _ \
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| | | _|\__ \__ \ _|| |__| |__ / _ \| || (_) | /
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|_| |___|___/___/___|____|____/_/ \_\_| \___/|_|_\
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*******************************************************************************/
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union VGT_OUTPUT_PATH_CNTL {
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xe::bf<xenos::VGTOutputPath, 0, 2> path_select;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_VGT_OUTPUT_PATH_CNTL;
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};
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union VGT_HOS_CNTL {
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xe::bf<xenos::TessellationMode, 0, 2> tess_mode;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_VGT_HOS_CNTL;
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};
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/*******************************************************************************
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___ ___ ___ __ __ ___ _____ _____ _____
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| _ \ _ \_ _| \/ |_ _|_ _|_ _\ \ / / __|
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| _/ /| || |\/| || | | | | | \ V /| _|
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|_| |_|_\___|_| |_|___| |_| |___| \_/ |___|
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_ ___ ___ ___ __ __ ___ _ ___ ___
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/_\ / __/ __| __| \/ | _ ) | | __| _ \
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/ _ \\__ \__ \ _|| |\/| | _ \ |__| _|| /
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/_/ \_\___/___/___|_| |_|___/____|___|_|_\
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*******************************************************************************/
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union PA_SU_POINT_MINMAX {
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// Radius, 12.4 fixed point.
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xe::bf<uint32_t, 0, 16> min_size;
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xe::bf<uint32_t, 16, 16> max_size;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_PA_SU_POINT_MINMAX;
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};
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union PA_SU_POINT_SIZE {
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// 1/2 width or height, 12.4 fixed point.
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xe::bf<uint32_t, 0, 16> height;
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xe::bf<uint32_t, 16, 16> width;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_PA_SU_POINT_SIZE;
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};
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// Setup Unit / Scanline Converter mode cntl
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union PA_SU_SC_MODE_CNTL {
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xe::bf<uint32_t, 0, 1> cull_front;
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xe::bf<uint32_t, 1, 1> cull_back;
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xe::bf<uint32_t, 2, 1> face;
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xe::bf<uint32_t, 3, 2> poly_mode;
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xe::bf<uint32_t, 5, 3> polymode_front_ptype;
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xe::bf<uint32_t, 8, 3> polymode_back_ptype;
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xe::bf<uint32_t, 11, 1> poly_offset_front_enable;
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xe::bf<uint32_t, 12, 1> poly_offset_back_enable;
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xe::bf<uint32_t, 13, 1> poly_offset_para_enable;
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xe::bf<uint32_t, 15, 1> msaa_enable;
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xe::bf<uint32_t, 16, 1> vtx_window_offset_enable;
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xe::bf<uint32_t, 18, 1> line_stipple_enable;
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xe::bf<uint32_t, 19, 1> provoking_vtx_last;
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xe::bf<uint32_t, 20, 1> persp_corr_dis;
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xe::bf<uint32_t, 21, 1> multi_prim_ib_ena;
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xe::bf<uint32_t, 23, 1> quad_order_enable;
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xe::bf<uint32_t, 25, 1> wait_rb_idle_all_tri;
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xe::bf<uint32_t, 26, 1> wait_rb_idle_first_tri_new_state;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_PA_SU_SC_MODE_CNTL;
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};
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// Setup Unit Vertex Control
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union PA_SU_VTX_CNTL {
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xe::bf<uint32_t, 0, 1> pix_center; // 1 = half pixel offset
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xe::bf<uint32_t, 1, 2> round_mode;
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xe::bf<uint32_t, 3, 3> quant_mode;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_PA_SU_VTX_CNTL;
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};
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union PA_SC_MPASS_PS_CNTL {
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xe::bf<uint32_t, 0, 20> mpass_pix_vec_per_pass;
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xe::bf<uint32_t, 31, 1> mpass_ps_ena;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_PA_SC_MPASS_PS_CNTL;
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};
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// Scanline converter viz query
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union PA_SC_VIZ_QUERY {
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xe::bf<uint32_t, 0, 1> viz_query_ena;
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xe::bf<uint32_t, 1, 6> viz_query_id;
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xe::bf<uint32_t, 7, 1> kill_pix_post_early_z;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_PA_SC_VIZ_QUERY;
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};
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// Clipper clip control
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union PA_CL_CLIP_CNTL {
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xe::bf<uint32_t, 0, 1> ucp_ena_0;
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xe::bf<uint32_t, 1, 1> ucp_ena_1;
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xe::bf<uint32_t, 2, 1> ucp_ena_2;
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xe::bf<uint32_t, 3, 1> ucp_ena_3;
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xe::bf<uint32_t, 4, 1> ucp_ena_4;
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xe::bf<uint32_t, 5, 1> ucp_ena_5;
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xe::bf<uint32_t, 14, 2> ps_ucp_mode;
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xe::bf<uint32_t, 16, 1> clip_disable;
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xe::bf<uint32_t, 17, 1> ucp_cull_only_ena;
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xe::bf<uint32_t, 18, 1> boundary_edge_flag_ena;
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xe::bf<uint32_t, 19, 1> dx_clip_space_def;
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xe::bf<uint32_t, 20, 1> dis_clip_err_detect;
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xe::bf<uint32_t, 21, 1> vtx_kill_or;
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xe::bf<uint32_t, 22, 1> xy_nan_retain;
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xe::bf<uint32_t, 23, 1> z_nan_retain;
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xe::bf<uint32_t, 24, 1> w_nan_retain;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_PA_CL_CLIP_CNTL;
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};
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// Viewport transform engine control
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union PA_CL_VTE_CNTL {
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xe::bf<uint32_t, 0, 1> vport_x_scale_ena;
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xe::bf<uint32_t, 1, 1> vport_x_offset_ena;
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xe::bf<uint32_t, 2, 1> vport_y_scale_ena;
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xe::bf<uint32_t, 3, 1> vport_y_offset_ena;
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xe::bf<uint32_t, 4, 1> vport_z_scale_ena;
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xe::bf<uint32_t, 5, 1> vport_z_offset_ena;
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xe::bf<uint32_t, 8, 1> vtx_xy_fmt;
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xe::bf<uint32_t, 9, 1> vtx_z_fmt;
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xe::bf<uint32_t, 10, 1> vtx_w0_fmt;
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xe::bf<uint32_t, 11, 1> perfcounter_ref;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_PA_CL_VTE_CNTL;
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};
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union PA_SC_WINDOW_OFFSET {
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xe::bf<int32_t, 0, 15> window_x_offset;
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xe::bf<int32_t, 16, 15> window_y_offset;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_PA_SC_WINDOW_OFFSET;
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};
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union PA_SC_WINDOW_SCISSOR_TL {
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xe::bf<uint32_t, 0, 14> tl_x;
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xe::bf<uint32_t, 16, 14> tl_y;
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xe::bf<uint32_t, 31, 1> window_offset_disable;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_PA_SC_WINDOW_SCISSOR_TL;
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};
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union PA_SC_WINDOW_SCISSOR_BR {
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xe::bf<uint32_t, 0, 14> br_x;
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xe::bf<uint32_t, 16, 14> br_y;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_PA_SC_WINDOW_SCISSOR_BR;
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};
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/*******************************************************************************
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___ ___
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| _ \ _ )
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|_|_\___/
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*******************************************************************************/
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union RB_MODECONTROL {
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xe::bf<xenos::ModeControl, 0, 3> edram_mode;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_RB_MODECONTROL;
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};
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union RB_SURFACE_INFO {
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xe::bf<uint32_t, 0, 14> surface_pitch;
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xe::bf<MsaaSamples, 16, 2> msaa_samples;
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xe::bf<uint32_t, 18, 14> hiz_pitch;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_RB_SURFACE_INFO;
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};
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union RB_COLORCONTROL {
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xe::bf<CompareFunction, 0, 3> alpha_func;
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xe::bf<uint32_t, 3, 1> alpha_test_enable;
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xe::bf<uint32_t, 4, 1> alpha_to_mask_enable;
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// Everything in between was added on Adreno, not in game PDBs and never set.
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xe::bf<uint32_t, 24, 2> alpha_to_mask_offset0;
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xe::bf<uint32_t, 26, 2> alpha_to_mask_offset1;
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xe::bf<uint32_t, 28, 2> alpha_to_mask_offset2;
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xe::bf<uint32_t, 30, 2> alpha_to_mask_offset3;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_RB_COLORCONTROL;
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};
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union RB_COLOR_INFO {
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xe::bf<uint32_t, 0, 12> color_base;
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xe::bf<ColorRenderTargetFormat, 16, 4> color_format;
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xe::bf<int32_t, 20, 6> color_exp_bias;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_RB_COLOR_INFO;
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// RB_COLOR[1-3]_INFO also use this format.
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};
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union RB_COLOR_MASK {
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xe::bf<uint32_t, 0, 1> write_red0;
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xe::bf<uint32_t, 1, 1> write_green0;
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xe::bf<uint32_t, 2, 1> write_blue0;
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xe::bf<uint32_t, 3, 1> write_alpha0;
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xe::bf<uint32_t, 4, 1> write_red1;
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xe::bf<uint32_t, 5, 1> write_green1;
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xe::bf<uint32_t, 6, 1> write_blue1;
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xe::bf<uint32_t, 7, 1> write_alpha1;
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xe::bf<uint32_t, 8, 1> write_red2;
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xe::bf<uint32_t, 9, 1> write_green2;
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xe::bf<uint32_t, 10, 1> write_blue2;
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xe::bf<uint32_t, 11, 1> write_alpha2;
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xe::bf<uint32_t, 12, 1> write_red3;
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xe::bf<uint32_t, 13, 1> write_green3;
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xe::bf<uint32_t, 14, 1> write_blue3;
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xe::bf<uint32_t, 15, 1> write_alpha3;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_RB_COLOR_MASK;
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};
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union RB_DEPTHCONTROL {
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xe::bf<uint32_t, 0, 1> stencil_enable;
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xe::bf<uint32_t, 1, 1> z_enable;
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xe::bf<uint32_t, 2, 1> z_write_enable;
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// EARLY_Z_ENABLE was added on Adreno.
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xe::bf<CompareFunction, 4, 3> zfunc;
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xe::bf<uint32_t, 7, 1> backface_enable;
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xe::bf<CompareFunction, 8, 3> stencilfunc;
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xe::bf<StencilOp, 11, 3> stencilfail;
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xe::bf<StencilOp, 14, 3> stencilzpass;
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xe::bf<StencilOp, 17, 3> stencilzfail;
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xe::bf<CompareFunction, 20, 3> stencilfunc_bf;
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xe::bf<StencilOp, 23, 3> stencilfail_bf;
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xe::bf<StencilOp, 26, 3> stencilzpass_bf;
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xe::bf<StencilOp, 29, 3> stencilzfail_bf;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_RB_DEPTHCONTROL;
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};
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union RB_STENCILREFMASK {
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xe::bf<uint32_t, 0, 8> stencilref;
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xe::bf<uint32_t, 8, 8> stencilmask;
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xe::bf<uint32_t, 16, 8> stencilwritemask;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_RB_STENCILREFMASK;
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// RB_STENCILREFMASK_BF also uses this format.
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};
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union RB_DEPTH_INFO {
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xe::bf<uint32_t, 0, 12> depth_base;
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xe::bf<DepthRenderTargetFormat, 16, 1> depth_format;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_RB_DEPTH_INFO;
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};
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union RB_COPY_CONTROL {
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xe::bf<uint32_t, 0, 3> copy_src_select;
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xe::bf<xenos::CopySampleSelect, 4, 3> copy_sample_select;
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xe::bf<uint32_t, 8, 1> color_clear_enable;
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xe::bf<uint32_t, 9, 1> depth_clear_enable;
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xe::bf<xenos::CopyCommand, 20, 2> copy_command;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_RB_COPY_CONTROL;
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};
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union RB_COPY_DEST_INFO {
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xe::bf<Endian128, 0, 3> copy_dest_endian;
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xe::bf<uint32_t, 3, 1> copy_dest_array;
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xe::bf<uint32_t, 4, 3> copy_dest_slice;
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xe::bf<ColorFormat, 7, 6> copy_dest_format;
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xe::bf<uint32_t, 13, 3> copy_dest_number;
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xe::bf<int32_t, 16, 6> copy_dest_exp_bias;
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xe::bf<uint32_t, 24, 1> copy_dest_swap;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_RB_COPY_DEST_INFO;
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};
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union RB_COPY_DEST_PITCH {
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xe::bf<uint32_t, 0, 14> copy_dest_pitch;
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xe::bf<uint32_t, 16, 14> copy_dest_height;
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uint32_t value;
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static constexpr uint32_t register_index = XE_GPU_REG_RB_COPY_DEST_PITCH;
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};
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} // namespace reg
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} // namespace gpu
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} // namespace xe
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#endif // XENIA_GPU_REGISTERS_H_
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