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refactor(cpu): fpscr round_single_toward_zero — collapse duplicate-branch ULP step

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Post-P8 review nit: the if/else branches were identical
(`adj_bits - 1` either way). Both positive and negative finite f32
values use the IEEE-754 sign bit as the MSB, and subtracting 1 from
`to_bits()` always reduces magnitude by one ULP. Replace the
mock-conditional with the unconditional form + a comment explaining
why one operation works for both signs.

No behavior change.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
This commit is contained in:
MechaCat02
2026-05-02 14:45:55 +02:00
parent f1166d0f75
commit 09c6c927bd
1 changed files with 6 additions and 1 deletions
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7
crates/xenia-cpu/src/fpscr.rs
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@@ -286,7 +286,12 @@ fn round_single_toward_zero(v: f64) -> f32 {
if rn.is_nan() || rn.is_infinite() || rn == 0.0 { return rn; } if rn.is_nan() || rn.is_infinite() || rn == 0.0 { return rn; }
if rn.abs() as f64 <= v.abs() { return rn; } if rn.abs() as f64 <= v.abs() { return rn; }
let adj_bits = rn.to_bits(); let adj_bits = rn.to_bits();
let lower = if rn.is_sign_positive() { adj_bits - 1 } else { adj_bits - 1 }; // Both positive and negative finite f32 values have the IEEE-754 sign
// bit as the MSB; subtracting 1 from `to_bits()` always reduces the
// magnitude by one ULP (clearing the lowest mantissa bit, with carry
// never reaching the sign bit since adj_bits is already not-zero,
// not-inf, not-NaN, and we already returned early for those).
let lower = adj_bits - 1;
f32::from_bits(lower) f32::from_bits(lower)
} }