[iterate-3T] Real UV interpolation + per-draw textures: shader/UV/bind chain complete
Build the full texture-sampling chain for the publisher splash so the textured logo CAN sample real artwork at the guest's real UVs. Measured with an env-gated frontbuffer readback (since removed): the chain is correct end-to-end, but the sampled K8888 1280x768 texture is ALL-ZERO in the UI window's reachable boot range — the artwork is produced by an EDRAM resolve (RT->texture copy) that ours does not yet perform (resolves=0). So this lands the correct shader/UV/bind work and isolates the remaining blocker to the resolve gap, not the shader path. Translator (xenia-gpu/src/translator.rs), all UI-translator-only: - Real Xenos export-index model (replaces the AllocKind heuristic that collapsed every VS export to one color slot and DROPPED the texcoord). When export_data is set the 6-bit vector_dest IS the export index: VS 62=oPos, 0..15=interps; PS 0=RT0. The logo VS exports oPos(62), interp0(color), interp1(UV) distinctly. - Real interpolator passthrough: VsOut carries 8 interpolator locations; the PS seeds r[i] = in.interp[i] (Xenos PS-input-GPR mapping) so tfetch samples at the real interpolated texcoord (r1) instead of (0,0). - vfetch format 6 (k_16_16) packed-16 unpack + per-attribute dword offset, so the 3 vfetches sharing one fetch-constant (pos/UV/color in a 6-dword vertex) read the right attribute. Previously rejected the whole logo VS to the interpreter. - QuadList/RectangleList host->guest vertex-index remap in the VS (replay is non-indexed): QuadList 6 host verts -> guest [0,1,2,0,2,3] (full quad). fetch.rs: decode vfetch `offset` (dword2[8:15], dwords), `is_signed`, `is_normalized`. Per-draw textures: DrawCapture carries the decoded texture(s) (keyed off the active PS's tfetch slots, attached in gpu_system after decode); render.rs::dispatch_xenos_captures uploads + binds each capture's texture via the host texture cache before its draw, instead of one last-draw primary_texture. Determinism: all changes feed only the UI translator/capture path; frame_captures is None headless. `check -n50m --gpu-inline --stable-digest --expect` byte- identical (exit 0). 681 tests pass (+2 regression: logo VS now translates with interpolators; PS seeds interps into registers). Temp readback/dump probes removed. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
@@ -66,6 +66,13 @@ pub struct DrawCapture {
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/// already carries the render-target → wgpu Y-flip (negated).
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pub ndc_scale: [f32; 2],
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pub ndc_offset: [f32; 2],
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/// iterate-3T: the decoded texture(s) this draw's active pixel shader
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/// samples, keyed off its real `tfetch` fetch-constant slots (the 3M
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/// decoder makes these decode). The UI uploads + binds the FIRST entry
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/// per-draw so the textured logo samples the real artwork instead of the
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/// magenta stub. Empty for flat (no-tfetch) draws. Populated by
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/// `gpu_system` after decode (left empty by `build`).
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pub textures: Vec<(crate::texture_cache::TextureKey, Vec<u8>)>,
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}
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/// iterate-3S: compute the guest→host NDC XY transform for a draw, mirroring
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@@ -287,5 +294,6 @@ pub fn build(
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has_real_vertices: has_real,
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ndc_scale,
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ndc_offset,
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textures: Vec::new(),
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}
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}
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@@ -1413,6 +1413,18 @@ impl GpuSystem {
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}
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}
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}
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// iterate-3T: attach this draw's decoded textures to the just-
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// captured draw so the UI can bind the real artwork per-draw
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// (keyed off the active PS's real tfetch slots) instead of a
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// single last-draw `primary_texture`. UI-only (`frame_captures`
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// is `None` headless); does not touch the deterministic core.
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if !self.last_draw_textures.is_empty()
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&& let Some(caps) = self.frame_captures.as_mut()
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&& let Some(last) = caps.last_mut()
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{
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last.textures = self.last_draw_textures.clone();
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}
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}
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pm4::PM4_SET_CONSTANT | pm4::PM4_SET_SHADER_CONSTANTS => {
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// payload[0] = offset_type — bits[10:0] index, bits[23:16] type
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@@ -115,9 +115,21 @@ struct XenosConstants {
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@group(1) @binding(0) var xenos_tex : texture_2d<f32>;
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@group(1) @binding(1) var xenos_samp : sampler;
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// iterate-3T: real interpolator passthrough. The Xenos VS exports up to 16
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// interpolators (export index 0..15); the PS reads interpolator i from its
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// general register r[i]. We carry 8 interpolator vec4s (covers Sylpheed's
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// splash: r0=color, r1=texcoord). `color` retained as an alias of interp0 so
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// older single-color paths keep working.
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struct VsOut {
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@builtin(position) position: vec4<f32>,
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@location(0) color: vec4<f32>,
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@location(0) interp0: vec4<f32>,
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@location(1) interp1: vec4<f32>,
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@location(2) interp2: vec4<f32>,
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@location(3) interp3: vec4<f32>,
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@location(4) interp4: vec4<f32>,
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@location(5) interp5: vec4<f32>,
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@location(6) interp6: vec4<f32>,
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@location(7) interp7: vec4<f32>,
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};
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struct FsOut {
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@@ -200,19 +212,56 @@ impl EmitCtx {
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self.push("var ps: f32 = 0.0;");
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match self.stage {
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Stage::Vertex => {
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// iterate-3T: host→guest vertex-index remap for primitives the
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// replay draws non-indexed as a flat triangle list. wgpu has no
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// QuadList/RectangleList topology, so the host issues 6 vertices
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// per quad/rect and we map them back to the guest's 4/3 source
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// vertices here (mirrors `primitive.rs` index rewrite, but in the
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// VS since the replay path is non-indexed):
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// QuadList(13): 6 host verts → guest [0,1,2, 0,2,3]
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// RectangleList(8): drawn as one triangle [0,1,2] (the 4th
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// corner needs cross-vertex synthesis — TODO), so host
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// indices >=3 fold onto the existing triangle.
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// Other prims pass through unchanged.
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self.push("var gvidx: u32 = vidx;");
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self.push("if (draw_ctx.prim_kind == 13u) {");
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self.indent += 1;
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self.push("let q = vidx % 6u; let qbase = (vidx / 6u) * 4u;");
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self.push("var lut = array<u32, 6>(0u, 1u, 2u, 0u, 2u, 3u);");
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self.push("gvidx = qbase + lut[q];");
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self.indent -= 1;
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self.push("} else if (draw_ctx.prim_kind == 8u) {");
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self.indent += 1;
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self.push("let t = vidx % 3u; let rbase = (vidx / 3u) * 3u;");
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self.push("gvidx = rbase + t;");
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self.indent -= 1;
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self.push("}");
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// Seed r0 with vertex index for simple shaders that read it.
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self.push("r[0] = vec4<f32>(f32(vidx), 0.0, 0.0, 1.0);");
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// Synthetic export slots — match the interpreter's layout so
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// the fallback path and translator path produce the same
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// visual output on shaders both support.
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self.push("r[0] = vec4<f32>(f32(gvidx), 0.0, 0.0, 1.0);");
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// iterate-3T: real export model. Xenos export index 62 = oPos;
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// indices 0..15 = interpolators. We hold position + 8
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// interpolator vec4s; `emit_export` writes the right slot keyed
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// on the export index. Seed interp0 to white so a VS that only
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// exports position still yields a visible (non-zero) color.
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self.push("var opos: vec4<f32> = vec4<f32>(0.0, 0.0, 0.0, 1.0);");
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self.push("var ocolor: vec4<f32> = vec4<f32>(1.0, 1.0, 1.0, 1.0);");
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self.push("var ointerp: array<vec4<f32>, 8>;");
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self.push("for (var i = 0u; i < 8u; i = i + 1u) { ointerp[i] = vec4<f32>(0.0, 0.0, 0.0, 1.0); }");
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self.push("ointerp[0] = vec4<f32>(1.0, 1.0, 1.0, 1.0);");
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}
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Stage::Pixel => {
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// Seed r0.xy with interpolated color lane so trivial shaders
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// that read r0 still produce something.
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self.push("r[0] = in.color;");
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self.push("var ocolor0: vec4<f32> = in.color;");
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// iterate-3T: the PS reads interpolator i from general register
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// r[i] (Xenos PS input GPR mapping). Seed r0..r7 from the VS's
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// interpolators so e.g. the logo PS's texcoord (r1) and color
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// (r0) arrive correctly; tfetch then samples at the real UV.
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self.push("r[0] = in.interp0;");
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self.push("r[1] = in.interp1;");
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self.push("r[2] = in.interp2;");
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self.push("r[3] = in.interp3;");
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self.push("r[4] = in.interp4;");
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self.push("r[5] = in.interp5;");
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self.push("r[6] = in.interp6;");
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self.push("r[7] = in.interp7;");
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self.push("var ocolor0: vec4<f32> = in.interp0;");
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}
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}
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@@ -269,7 +318,14 @@ impl EmitCtx {
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self.indent -= 1;
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self.push("}");
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self.push("out.position = opos;");
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self.push("out.color = ocolor;");
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self.push("out.interp0 = ointerp[0];");
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self.push("out.interp1 = ointerp[1];");
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self.push("out.interp2 = ointerp[2];");
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self.push("out.interp3 = ointerp[3];");
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self.push("out.interp4 = ointerp[4];");
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self.push("out.interp5 = ointerp[5];");
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self.push("out.interp6 = ointerp[6];");
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self.push("out.interp7 = ointerp[7];");
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self.push("return out;");
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}
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Stage::Pixel => {
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@@ -398,20 +454,35 @@ impl EmitCtx {
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}
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fn emit_export(&mut self, dst_reg: u8, alloc: AllocKind, expr: &str, mask: u8) {
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// Xenos's export "register" indexing within an alloc range is
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// normally (alloc_base + offset). Since our CF stream doesn't
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// carry per-export slot offsets cleanly, use `alloc` to pick the
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// target.
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let lhs = match (self.stage, alloc) {
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(Stage::Vertex, AllocKind::Position) => "opos",
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(Stage::Vertex, AllocKind::Interpolators) => "ocolor",
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(Stage::Vertex, AllocKind::Colors) => "ocolor",
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(Stage::Vertex, _) => "ocolor", // fall through — any other alloc
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(Stage::Pixel, AllocKind::Colors) => "ocolor0",
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(Stage::Pixel, _) => "ocolor0",
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// iterate-3T: real Xenos export-index model (replaces the `AllocKind`
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// heuristic, which collapsed every VS export to a single color slot and
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// dropped the texcoord interpolator → tfetch sampled (0,0) → flat).
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// When `export_data` is set the 6-bit vector_dest IS the export index:
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// VS: 62 = oPos, 63 = oPointSize/edge (ignored), 0..15 = interpolators.
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// PS: 0..3 = color render targets (we honor RT0).
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let _ = alloc;
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match self.stage {
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Stage::Vertex => {
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let lhs = if dst_reg == 62 {
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"opos".to_string()
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} else if dst_reg <= 15 {
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// Clamp to the 8 interpolator slots we carry; higher slots
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// are unused by Sylpheed's splash.
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let i = (dst_reg as usize).min(7);
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format!("ointerp[{i}u]")
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} else {
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// oPointSize (63) / unknown export slot — discard.
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return;
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};
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let _ = dst_reg; // per-slot export indexing reserved for a richer v2
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self.emit_masked_write(lhs, expr, mask);
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self.emit_masked_write(&lhs, expr, mask);
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}
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Stage::Pixel => {
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// Only RT0 (export index 0) is wired to the single host target.
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if dst_reg == 0 {
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self.emit_masked_write("ocolor0", expr, mask);
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}
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}
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}
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}
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fn emit_vfetch(&mut self, vf: &crate::ucode::fetch::VertexFetch) -> Result<(), &'static str> {
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@@ -426,22 +497,38 @@ impl EmitCtx {
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// GPUBUG-102: the fetch constant holds the endian field in dword_1's
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// low 2 bits; Xbox 360 vertex data is big-endian, so `gpu_swap` undoes
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// it per component.
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let (comps, stride): (u32, u32) = match vf.format {
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36 => (1, 1), // k_32_FLOAT
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37 => (2, 2), // k_32_32_FLOAT
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57 => (3, 3), // k_32_32_32_FLOAT
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38 => (4, 4), // k_32_32_32_32_FLOAT
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// (comps, dwords_read) per format. Float formats are 1 dword/component;
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// iterate-3T adds the packed-16 `k_16_16` (format 6) used for the logo
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// UV interpolator — 2 components packed into ONE dword.
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#[derive(PartialEq)]
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enum Pack {
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Float, // N f32 lanes, N dwords
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Norm16x2, // 2× u16 normalized into [0,1], 1 dword (k_16_16)
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}
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let (comps, dwords_read, pack): (u32, u32, Pack) = match vf.format {
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36 => (1, 1, Pack::Float), // k_32_FLOAT
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37 => (2, 2, Pack::Float), // k_32_32_FLOAT
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57 => (3, 3, Pack::Float), // k_32_32_32_FLOAT
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38 => (4, 4, Pack::Float), // k_32_32_32_32_FLOAT
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6 => (2, 1, Pack::Norm16x2), // k_16_16 (UV)
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_ => return Err(reject::VFETCH_FMT),
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};
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// A stride of 0 in the instruction means "use the fetch-constant
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// stride"; fall back to the tightly packed component count.
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let stride = if vf.stride != 0 { vf.stride as u32 } else { stride };
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// stride"; fall back to the tightly packed dword count.
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let stride = if vf.stride != 0 { vf.stride as u32 } else { dwords_read };
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// iterate-3T: per-attribute dword offset within the vertex (vfetches
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// sharing one fetch constant read different attributes).
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let attr_off = vf.offset;
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let fetch_const = (vf.raw[0] >> 5) & 0x1F;
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let src_reg = vf.src_register & 0x7F;
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let dst_reg = vf.dest_register & 0x7F;
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// is_signed selects [-1,1] vs [0,1] for normalized integer formats.
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let signed = vf.is_signed;
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// Build the per-component reads; unread lanes default to 0/0/0/1 so an
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// XY-only position keeps W=1 (and Z=0).
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let lane = |i: u32| -> String {
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match pack {
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Pack::Float => {
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if i < comps {
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format!("bitcast<f32>(gpu_swap(vertex_buffer[addr + {i}u], endian))")
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} else if i == 3 {
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@@ -449,8 +536,31 @@ impl EmitCtx {
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} else {
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"0.0".to_string()
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}
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}
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Pack::Norm16x2 => {
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// One dword holds [u16 lo | u16 hi] after the endian swap.
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// Component 0 = low halfword, component 1 = high halfword.
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if i == 0 {
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if signed {
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"(max(f32(i32(w16 << 16u) >> 16u) / 32767.0, -1.0))".to_string()
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} else {
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"(f32(w16 & 0xFFFFu) / 65535.0)".to_string()
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}
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} else if i == 1 {
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if signed {
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"(max(f32(i32(w16) >> 16u) / 32767.0, -1.0))".to_string()
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} else {
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"(f32(w16 >> 16u) / 65535.0)".to_string()
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}
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} else if i == 3 {
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"1.0".to_string()
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} else {
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"0.0".to_string()
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}
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}
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}
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};
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let read_bound = comps - 1;
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let read_bound = dwords_read - 1;
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// GPUBUG-108 (iterate-3S): for the captured-geometry path the CPU
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// uploads a vertex window that begins EXACTLY at the fetch base, so the
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// base within `vertex_buffer` is 0 and vertex i sits at `i * stride`.
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@@ -464,6 +574,13 @@ impl EmitCtx {
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// real window is present (`vertex_base_dwords != 0`); only the
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// synthetic/no-window fallback consults the uniform fetch constant.
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let endian_term = format!("xenos_consts.fetch[{}u] & 0x3u", fetch_const * 2 + 1);
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// For packed-16 we read one dword into `w16` (post endian-swap) and the
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// `lane()` exprs above unpack the two halfwords.
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let w16_decl = if pack == Pack::Norm16x2 {
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"let w16 = gpu_swap(vertex_buffer[addr], endian); "
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} else {
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""
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};
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self.push(&format!(
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"{{ let endian = {endian_term}; \
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let vidx = u32(r[{src_reg}u].x); \
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@@ -471,9 +588,10 @@ impl EmitCtx {
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if (draw_ctx.vertex_base_dwords == 0u) {{ \
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base = (xenos_consts.fetch[{fc0_idx}u] & 0xFFFFFFFCu) >> 2u; \
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}} \
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let addr = base + vidx * {stride}u; \
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let addr = base + vidx * {stride}u + {attr_off}u; \
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let n = arrayLength(&vertex_buffer); \
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if (addr + {read_bound}u < n) {{ \
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{w16_decl}\
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r[{dst_reg}u] = vec4<f32>({l0}, {l1}, {l2}, {l3}); \
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}} }}",
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fc0_idx = fetch_const * 2,
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@@ -626,6 +744,54 @@ mod tests {
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use crate::ucode::alu::{sop, vop};
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use crate::ucode::control_flow::ControlFlowInstruction;
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/// iterate-3T: the real publisher-logo VS (`vs_key 0x03b7b020`, captured
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/// from the live boot) must now TRANSLATE — pre-3T it rejected with
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/// `vfetch_fmt` because (a) the `k_16_16` color stream (format 6) was
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/// unsupported and (b) the export-index model (62=oPos, 0/1=interpolators)
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/// was a wrong AllocKind heuristic. This locks in the format-6 + per-
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/// attribute-offset + export-index work so the UV interpolator reaches the
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/// pixel shader (texcoord in r1) instead of collapsing to a single color.
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#[test]
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fn real_logo_vs_translates_with_interpolators() {
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let ucode: [u32; 30] = [
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0x70153003, 0x00001200, 0xC2000000, 0x00001006, 0x00001200, 0xC4000000,
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0x00002007, 0x00002200, 0x00000000, 0x2DF82000, 0x00393A88, 0x00000006,
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0x05F81000, 0x4006060A, 0x00000306, 0x05F80000, 0x40253FC8, 0x00000406,
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0xC80F803E, 0x00000000, 0xC2020200, 0xC8038001, 0x00B0B000, 0xC2000000,
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0xC80F8000, 0x00000000, 0xC2010100, 0x00000000, 0x00000000, 0x00000000,
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];
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let p = crate::ucode::parse_shader(&ucode);
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let body = match translate(&p, Stage::Vertex) {
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Translation::Ok(b) => b,
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Translation::Reject(r) => panic!("logo VS rejected: {r}"),
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};
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// Position must come from the export-index-62 path (`opos`) and the
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// UV/color interpolators must be exported as distinct slots.
|
||||
assert!(body.contains("opos ="), "no position export: {body}");
|
||||
assert!(body.contains("ointerp[0u]"), "no interp0 export: {body}");
|
||||
assert!(body.contains("ointerp[1u]"), "no interp1 export: {body}");
|
||||
// The k_16_16 attribute must unpack via the packed-16 helper.
|
||||
assert!(body.contains("w16"), "no packed-16 unpack for k_16_16: {body}");
|
||||
}
|
||||
|
||||
/// The logo pixel shader (`ps_key 0x03b79001`) samples its texture at the
|
||||
/// interpolated texcoord register r1 — which the PS now seeds from the VS
|
||||
/// interpolator `in.interp1` (Xenos PS-input-GPR mapping). Verifies the UV
|
||||
/// chain so tfetch samples the real UV instead of (0,0).
|
||||
#[test]
|
||||
fn ps_seeds_interpolators_into_registers() {
|
||||
// A trivial PS that just exports — we only assert the preamble wiring.
|
||||
let p = crate::ucode::ParsedShader {
|
||||
cf: vec![ControlFlowInstruction::Exit],
|
||||
instructions: vec![],
|
||||
};
|
||||
let body = match translate(&p, Stage::Pixel) {
|
||||
Translation::Ok(b) => b,
|
||||
Translation::Reject(r) => panic!("trivial PS rejected: {r}"),
|
||||
};
|
||||
assert!(body.contains("r[1] = in.interp1;"), "PS must seed r1 from interp1: {body}");
|
||||
}
|
||||
|
||||
fn synthetic_trivial_shader() -> ParsedShader {
|
||||
// Single Exec clause: ALU add r0 = r0 + r0; scalar_op = RETAIN_PREV
|
||||
// with full write-mask on vector, zero on scalar. Alloc(Position)
|
||||
@@ -799,6 +965,9 @@ mod tests {
|
||||
dest_write_mask: 0xF,
|
||||
format: 38, // k_32_32_32_32_FLOAT (4 floats)
|
||||
stride: 4,
|
||||
offset: 0,
|
||||
is_signed: false,
|
||||
is_normalized: true,
|
||||
raw: [0; 3],
|
||||
};
|
||||
ctx.emit_vfetch(&vf).expect("emit_vfetch");
|
||||
|
||||
@@ -34,6 +34,19 @@ pub struct VertexFetch {
|
||||
pub format: u8,
|
||||
/// Dword stride between consecutive vertices (dword2[0:7]).
|
||||
pub stride: u8,
|
||||
/// iterate-3T: dword offset of THIS attribute within the vertex stride
|
||||
/// (dword2[16:38] in canary's `VertexFetchInstruction`; the low 23 bits).
|
||||
/// A 6-dword vertex with position@0 + UV@2 + extra@3 needs this so the
|
||||
/// three vfetches sharing one fetch-constant read different attributes
|
||||
/// instead of all reading offset 0.
|
||||
pub offset: u32,
|
||||
/// iterate-3T: `is_signed` (dword2 bit 24 in canary) — selects signed vs
|
||||
/// unsigned interpretation of packed integer formats.
|
||||
pub is_signed: bool,
|
||||
/// iterate-3T: `is_normalized` — canary inverts it: dword2 bit 25 set means
|
||||
/// the value is taken as an *integer* (un-normalized); clear means
|
||||
/// normalized to [0,1] / [-1,1]. We store the normalized sense directly.
|
||||
pub is_normalized: bool,
|
||||
pub raw: [u32; 3],
|
||||
}
|
||||
|
||||
@@ -81,9 +94,15 @@ pub fn decode_fetch(words: [u32; 3]) -> FetchInstruction {
|
||||
src_register: ((w0 >> 5) & 0x3F) as u8,
|
||||
dest_register: ((w0 >> 12) & 0x3F) as u8,
|
||||
dest_write_mask: (w1 & 0xF) as u8,
|
||||
// dword1[16:21] = VertexFormat; dword2[0:7] = dword stride.
|
||||
// dword1[16:21] = VertexFormat. dword2: stride[0:7],
|
||||
// offset (in dwords) [8:?] — empirically the attribute offset of
|
||||
// the textured logo VS lands in dword2[8:15] (pos@4, UV@3,
|
||||
// 3-float@0 in a 6-dword vertex). signed/normalized live higher.
|
||||
format: ((w1 >> 16) & 0x3F) as u8,
|
||||
stride: (w2 & 0xFF) as u8,
|
||||
offset: (w2 >> 8) & 0xFF,
|
||||
is_signed: ((w1 >> 24) & 1) != 0,
|
||||
is_normalized: ((w1 >> 25) & 1) == 0,
|
||||
raw: words,
|
||||
}),
|
||||
op::TEXTURE_FETCH => FetchInstruction::Texture(TextureFetch {
|
||||
|
||||
@@ -748,6 +748,39 @@ impl RenderState {
|
||||
label: Some("xenos capture replay"),
|
||||
});
|
||||
for cap in captures {
|
||||
// iterate-3T: bind this draw's REAL decoded texture (keyed off the
|
||||
// active PS's tfetch slot, attached in `gpu_system`) so the textured
|
||||
// logo samples the artwork. `None` reverts to the magenta stub for
|
||||
// flat draws. Each `set_texture_view` rebuilds the tex bind group;
|
||||
// the subsequent `render_one*` reads it, so per-draw binding works
|
||||
// even though all draws share one encoder.
|
||||
{
|
||||
let Self {
|
||||
device,
|
||||
queue,
|
||||
xenos_pipeline,
|
||||
host_texture_cache,
|
||||
..
|
||||
} = self;
|
||||
match cap.textures.first() {
|
||||
Some((key, bytes)) => {
|
||||
// Stable version: identical (key,bytes) across draws
|
||||
// reuse the uploaded wgpu texture (the splash artwork is
|
||||
// static). A genuine content change arrives as a new key
|
||||
// (base_address/dims) from the decoder.
|
||||
let cached = xenia_gpu::texture_cache::CachedTexture {
|
||||
key: *key,
|
||||
version_when_uploaded: 1,
|
||||
bytes: bytes.clone(),
|
||||
};
|
||||
host_texture_cache.upload(device, queue, &cached);
|
||||
if let Some(view) = host_texture_cache.view_for(key) {
|
||||
xenos_pipeline.set_texture_view(device, Some(view));
|
||||
}
|
||||
}
|
||||
None => xenos_pipeline.set_texture_view(device, None),
|
||||
}
|
||||
}
|
||||
let raw_vs = shader_blobs.get(&cap.vs_key).cloned().unwrap_or_default();
|
||||
let raw_ps = shader_blobs.get(&cap.ps_key).cloned().unwrap_or_default();
|
||||
let parsed_vs = xenia_gpu::ucode::parse_shader(&raw_vs);
|
||||
|
||||
Reference in New Issue
Block a user