fix(cpu): PPCBUG-424+425 vmaddfp128/vmaddcfp128 operand swap + va128 field fix

PPCBUG-424: vmaddfp128 computed VA×VB+VD instead of ISA-mandated VA×VD+VB.
PPCBUG-425: vmaddcfp128 computed VD×VB+VA instead of ISA-mandated VA×VD+VB.

Root-cause discovered while writing the operand-order regression tests:
va128() was extracting PPC bits 6-10 (the same field as vd128's low 5 bits),
not PPC bits 11-15 where VA lives in VX128 form. This meant va128() silently
aliased vd128 for any instruction where VA != VD, making the operand swap
invisible in the existing denorm-flush test (which used VA == VD == v2).

Fixes in this commit:
- decoder.rs: va128() now extracts PPC bits 11-15 (host bits 20-16) + bit29.
  The vmx128_va128_uses_bit29 test encoding updated to match the correct field.
- interpreter.rs: vmaddfp128 changed from ai.mul_add(bi,di) to ai.mul_add(di,bi)
  (VA×VD+VB). vmaddcfp128 changed from di.mul_add(bi,ai) to ai.mul_add(di,bi).
  vmaddfp128_flushes_denormal_inputs redesigned with distinct VA/VD/VB registers
  (v1/v2/v3) so the flush test is independent of the accessor fix.
  New vmaddfp128_operand_order_va_times_vd_plus_vb and
  vmaddcfp128_operand_order_va_times_vd_plus_vb tests verify 2×3+10=16.
- disasm_goldens.rs + vmx128_registers.json: vmaddfp128/vmaddcfp128/vnmsubfp128
  golden raws updated to properly encode VA at PPC bits 11-15 (new raws:
  0x146328D4 / 0x14632914 / 0x14632954). vperm128 / vsrw128 golden operands
  updated to reflect correct VA extraction (v4 instead of v3/v0).

Affects all VMX128 binary ops that call va128(): vaddfp128, vsubfp128,
vmulfp128, vmaddfp128, vmaddcfp128, vnmsubfp128, vperm128, vsrw128 etc.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>

crates/xenia-cpu/tests/golden/vmx128_registers.json

@@ -75,21 +75,21 @@
       "raw": "0x14642801",
       "addr": "0x82000000",
       "mnemonic": "vperm128",
-      "operands": "v3, v3, v5, 0"
+      "operands": "v3, v4, v5, 0"
     },
     {
       "label": "encoding vd_hi=00: actually vsrw128",
       "raw": "0x180461D0",
       "addr": "0x82000000",
       "mnemonic": "vsrw128",
-      "operands": "v0, v0, v12"
+      "operands": "v0, v4, v12"
     },
     {
       "label": "encoding vd_hi=10: actually vsrw128 v32",
       "raw": "0x180465D0",
       "addr": "0x82000000",
       "mnemonic": "vsrw128",
-      "operands": "v32, v0, v12"
+      "operands": "v32, v4, v12"
     },
     {
       "label": "encoding vd_hi=01: actually vpermwi128",
@@ -114,21 +114,21 @@
     },
     {
       "label": "vmaddfp128 v3, v35, v5, v3",
-      "raw": "0x146028D4",
+      "raw": "0x146328D4",
       "addr": "0x82000000",
       "mnemonic": "vmaddfp128",
       "operands": "v3, v35, v5, v3"
     },
     {
       "label": "vmaddcfp128 v3, v35, v3, v5",
-      "raw": "0x14602914",
+      "raw": "0x14632914",
       "addr": "0x82000000",
       "mnemonic": "vmaddcfp128",
       "operands": "v3, v35, v3, v5"
     },
     {
       "label": "vnmsubfp128 v3, v35, v3, v5",
-      "raw": "0x14602954",
+      "raw": "0x14632954",
       "addr": "0x82000000",
       "mnemonic": "vnmsubfp128",
       "operands": "v3, v35, v3, v5"