xenia-gpu: end-to-end Xenos pipeline (PM4, ucode, EDRAM, resolve)

First real GPU implementation. Ring/PM4 frontend (ring_view,
ring_drain, pm4) drains the command processor; gpu_system owns the
threaded backend (DrainFence RPC + parker/fence helpers from M1) and
the MMIO-mapped register block (mmio_region).

Xenos shader frontend: ucode/{alu,control_flow,fetch,mod}.rs decode
the Xbox 360 microcode, translator.rs lowers it onto the WGSL
xenos_interp interpreter shader (shaders/xenos_interp.wgsl).
shader_metrics.rs counts decode/translate work.

Render state: draw_state, primitive, render_target_cache,
texture_cache, tiled_address (Xenos's swizzled tiled-memory layout),
xenos_constants (register field constants), edram (the 10 MiB EDRAM
model with MSAA), and resolve.rs (TILE_FLUSH copy-out — clear-resolve
plus bitwise-equivalent 32 bpp + 64 bpp paths landed). handle.rs
owns the typed GPU-resource handles the kernel hands out.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
2026-05-01 16:29:38 +02:00
parent 5f0d6487ea
commit 79eb52c378
24 changed files with 10984 additions and 18 deletions

View File

@@ -1,21 +1,49 @@
//! Xenos GPU emulation for xenia-rs.
//!
//! Modules:
//! - [`pm4`]: packet format decoder + Type-3 opcode set.
//! - [`ring_view`]: ring-buffer bookkeeping (base/size/read/write pointers).
//! - [`register_file`]: 0x6000-entry register array backing the CP + state.
//! - [`gpu_system`]: top-level `GpuSystem` + PM4 executor running one packet
//! per call (see the plan's P2 for the design rationale).
//!
//! Legacy module `ring_drain` and `command_processor` are retained while P3+
//! migrations finish; they will be removed once every caller is on
//! [`gpu_system::GpuSystem`].
pub mod command_processor;
pub mod draw_state;
pub mod edram;
pub mod gpu_system;
pub mod handle;
pub mod mmio_region;
pub mod pm4;
pub mod primitive;
pub mod register_file;
pub mod ring_drain;
pub mod ring_view;
pub mod render_target_cache;
pub mod resolve;
pub mod shader_metrics;
pub mod shaders;
pub mod texture_cache;
pub mod tiled_address;
pub mod translator;
pub mod ucode;
pub mod xenos_constants;
/// Stub GPU system for initial implementation.
pub struct GpuSystem {
pub register_file: register_file::RegisterFile,
}
impl GpuSystem {
pub fn new() -> Self {
Self {
register_file: register_file::RegisterFile::new(),
}
}
}
impl Default for GpuSystem {
fn default() -> Self {
Self::new()
}
}
pub use gpu_system::{
ExecOutcome, GpuBlock, GpuMmio, GpuStats, GpuSystem, InterruptSource, PendingInterrupt,
ShaderBlob, SwapNotification, WaitCmp,
};
pub use handle::{
DrainReply, GpuBackend, GpuCommand, GpuDigestSnapshot, GpuHandle, GpuWorker,
shutdown_and_join_with_timeout, spawn_gpu_worker, spawn_noop_worker,
};
pub use mmio_region::build_region as build_mmio_region;
pub use pm4::{
PacketHeader, PacketKind, PM4_INTERRUPT, PM4_NOP, PM4_XE_SWAP, SWAP_SIGNATURE,
type3_opcode_name,
};
pub use ring_drain::{DrainResult, drain};
pub use ring_view::RingBufferView;