xenia-gpu: end-to-end Xenos pipeline (PM4, ucode, EDRAM, resolve)
First real GPU implementation. Ring/PM4 frontend (ring_view,
ring_drain, pm4) drains the command processor; gpu_system owns the
threaded backend (DrainFence RPC + parker/fence helpers from M1) and
the MMIO-mapped register block (mmio_region).
Xenos shader frontend: ucode/{alu,control_flow,fetch,mod}.rs decode
the Xbox 360 microcode, translator.rs lowers it onto the WGSL
xenos_interp interpreter shader (shaders/xenos_interp.wgsl).
shader_metrics.rs counts decode/translate work.
Render state: draw_state, primitive, render_target_cache,
texture_cache, tiled_address (Xenos's swizzled tiled-memory layout),
xenos_constants (register field constants), edram (the 10 MiB EDRAM
model with MSAA), and resolve.rs (TILE_FLUSH copy-out — clear-resolve
plus bitwise-equivalent 32 bpp + 64 bpp paths landed). handle.rs
owns the typed GPU-resource handles the kernel hands out.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
557
crates/xenia-gpu/src/translator.rs
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557
crates/xenia-gpu/src/translator.rs
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@@ -0,0 +1,557 @@
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//! Xenos → WGSL direct translator (P7).
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//!
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//! Replaces the runtime uber-shader interpreter (P3b/P3c) for shaders whose
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//! feature set we cover. Emits a *standalone* WGSL module per shader
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//! instead of walking a ucode buffer at draw time — pipeline compilation
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//! happens once, then every subsequent dispatch is a direct `draw()`.
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//!
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//! The translator is deliberately narrow: when it encounters an opcode /
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//! fetch format / CF shape it doesn't know, it returns [`None`] and the
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//! caller falls back to the interpreter. This keeps the op-coverage work
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//! incremental — future commits can add one opcode at a time without
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//! invalidating the scaffolding.
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//!
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//! Current coverage (v1):
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//! * Linear CF: `Exec`/`ExecEnd`, `Alloc`, `Exit`. No loops / branches /
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//! calls / predicate-gated clauses.
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//! * ALU vector: `ADD`, `MUL`, `MAX`, `MIN`, `MAD`, `DP4`, `DP3`,
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//! `DP2_ADD`, `SEQ`, `SGT`, `SGE`, `SNE`, `FRC`, `FLOOR`.
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//! * ALU scalar: `ADDS`, `MULS`, `MAXS`, `MINS`, `RCP`, `RETAIN_PREV`.
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//! * Vertex fetch: `R32G32B32A32_FLOAT` only.
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//! * Texture fetch: 2D via the single `@group(1)` slot (same one P5/M6
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//! binds).
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//! * Exports: VS writes position + interpolator 0 (color); PS writes
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//! color0.
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//!
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//! When a shader exceeds this subset, [`translate`] returns `None` and
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//! `gpu.shader.translate_reject{reason}` is bumped by the caller.
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use crate::ucode::alu::{decode_alu, sop, vop, AluInstruction};
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use crate::ucode::control_flow::{AllocKind, ControlFlowInstruction};
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use crate::ucode::fetch::{decode_fetch, FetchInstruction};
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use crate::ucode::ParsedShader;
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/// Shader stage we're emitting for.
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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pub enum Stage {
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Vertex,
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Pixel,
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}
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/// Success or refusal from the translator. On refusal, the caller falls
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/// back to the runtime uber-shader interpreter.
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#[derive(Debug)]
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pub enum Translation {
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/// The emitted WGSL body for *this stage only*. Both VS + PS get
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/// wrapped into one module via [`combine_stages`].
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Ok(String),
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/// Translator saw an op/pattern it doesn't handle; fallback.
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Reject(&'static str),
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}
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/// Full WGSL module for a (VS, PS) pair ready to hand to
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/// `wgpu::Device::create_shader_module`. Shares the header across the two
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/// bodies so bindings, struct declarations, and helpers aren't duplicated.
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pub fn combine_stages(vs_body: &str, ps_body: &str) -> String {
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let mut out = String::with_capacity(4096 + vs_body.len() + ps_body.len());
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out.push_str(MODULE_HEADER);
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out.push_str(vs_body);
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out.push_str(ps_body);
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out
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}
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/// Translate a single shader stage. Returns `None` on any unsupported
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/// feature with a short reason string that the caller plumbs into the
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/// `gpu.shader.translate_reject{reason}` metric.
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pub fn translate(parsed: &ParsedShader, stage: Stage) -> Translation {
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let mut ctx = EmitCtx::new(stage);
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// Emit the stage entry function body.
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if let Err(reason) = ctx.emit_stage_body(parsed) {
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return Translation::Reject(reason);
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}
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Translation::Ok(ctx.finish())
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}
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/// Reject reasons; kept as static &'str for zero-alloc metrics.
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pub mod reject {
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pub const VEC_OP_UNSUPPORTED: &str = "vec_op_unsupported";
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pub const SCL_OP_UNSUPPORTED: &str = "scl_op_unsupported";
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pub const CF_LOOP: &str = "cf_loop";
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pub const CF_COND: &str = "cf_cond";
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pub const CF_CALL: &str = "cf_call";
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pub const CF_UNKNOWN: &str = "cf_unknown";
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pub const VFETCH_FMT: &str = "vfetch_fmt";
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pub const TFETCH_NON2D: &str = "tfetch_non2d";
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pub const INSTR_OOB: &str = "instr_oob";
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}
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/// Shader-module preamble (bindings, helpers, struct defs). The bindings
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/// mirror the xenos pipeline's `@group(0)` + `@group(1)` layout from P5/M6
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/// so we can use **the same bind-group slots** — only the pipeline object
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/// differs between interpreter mode and translator mode.
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const MODULE_HEADER: &str = r#"
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struct XenosDrawConstants {
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draw_index: u32,
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vertex_count: u32,
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prim_kind: u32,
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_pad: u32,
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};
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struct XenosConstants {
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alu: array<vec4<f32>, 512>,
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fetch: array<u32, 256>,
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bool_consts: array<u32, 8>,
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loop_consts: array<u32, 32>,
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};
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@group(0) @binding(0) var<uniform> draw_ctx : XenosDrawConstants;
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@group(0) @binding(1) var<storage, read> xenos_consts : XenosConstants;
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@group(0) @binding(2) var<storage, read> vs_ucode : array<u32>;
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@group(0) @binding(3) var<storage, read> ps_ucode : array<u32>;
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@group(0) @binding(4) var<storage, read> vertex_buffer : array<u32>;
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@group(1) @binding(0) var xenos_tex : texture_2d<f32>;
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@group(1) @binding(1) var xenos_samp : sampler;
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struct VsOut {
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@builtin(position) position: vec4<f32>,
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@location(0) color: vec4<f32>,
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};
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struct FsOut {
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@location(0) color0: vec4<f32>,
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};
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// Helper: reciprocal guarded against divide-by-zero.
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fn xe_rcp(x: f32) -> f32 {
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return select(0.0, 1.0 / x, x != 0.0);
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}
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"#;
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struct EmitCtx {
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stage: Stage,
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out: String,
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indent: usize,
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}
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impl EmitCtx {
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fn new(stage: Stage) -> Self {
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Self {
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stage,
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out: String::with_capacity(2048),
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indent: 0,
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}
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}
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fn finish(self) -> String {
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self.out
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}
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fn push(&mut self, s: &str) {
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for _ in 0..self.indent {
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self.out.push_str(" ");
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}
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self.out.push_str(s);
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self.out.push('\n');
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}
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fn emit_stage_body(&mut self, parsed: &ParsedShader) -> Result<(), &'static str> {
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// Entry function + struct header.
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match self.stage {
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Stage::Vertex => {
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self.push("@vertex");
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self.push("fn vs_main(@builtin(vertex_index) vidx: u32) -> VsOut {");
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}
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Stage::Pixel => {
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self.push("@fragment");
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self.push("fn fs_main(in: VsOut) -> FsOut {");
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}
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}
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self.indent = 1;
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// Register file + ps chain + export slots. All local `var`s so each
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// invocation gets its own state; translator-emitted code doesn't
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// need `var<private>` because we don't share across function calls.
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self.push("var r: array<vec4<f32>, 128>;");
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self.push("for (var i = 0u; i < 128u; i = i + 1u) { r[i] = vec4<f32>(0.0); }");
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self.push("var ps: f32 = 0.0;");
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match self.stage {
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Stage::Vertex => {
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// Seed r0 with vertex index for simple shaders that read it.
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self.push("r[0] = vec4<f32>(f32(vidx), 0.0, 0.0, 1.0);");
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// Synthetic export slots — match the interpreter's layout so
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// the fallback path and translator path produce the same
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// visual output on shaders both support.
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self.push("var opos: vec4<f32> = vec4<f32>(0.0, 0.0, 0.0, 1.0);");
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self.push("var ocolor: vec4<f32> = vec4<f32>(1.0, 1.0, 1.0, 1.0);");
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}
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Stage::Pixel => {
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// Seed r0.xy with interpolated color lane so trivial shaders
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// that read r0 still produce something.
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self.push("r[0] = in.color;");
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self.push("var ocolor0: vec4<f32> = in.color;");
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}
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}
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let mut current_alloc = AllocKind::Other;
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for clause in &parsed.cf {
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match clause {
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ControlFlowInstruction::Exec {
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address,
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count,
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sequence,
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is_end,
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predicated,
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..
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} => {
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if *predicated {
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return Err(reject::CF_COND);
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}
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self.emit_exec(parsed, *address, *count, *sequence, current_alloc)?;
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if *is_end {
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break;
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}
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}
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ControlFlowInstruction::Alloc { kind, .. } => {
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current_alloc = *kind;
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}
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ControlFlowInstruction::Exit => break,
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ControlFlowInstruction::LoopStart { .. }
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| ControlFlowInstruction::LoopEnd { .. } => return Err(reject::CF_LOOP),
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ControlFlowInstruction::CondJmp { .. } => return Err(reject::CF_COND),
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ControlFlowInstruction::CondCall { .. } | ControlFlowInstruction::Return => {
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return Err(reject::CF_CALL);
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}
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ControlFlowInstruction::Unknown { .. } => return Err(reject::CF_UNKNOWN),
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}
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}
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match self.stage {
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Stage::Vertex => {
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self.push("var out: VsOut;");
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self.push("out.position = opos;");
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self.push("out.color = ocolor;");
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self.push("return out;");
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}
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Stage::Pixel => {
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self.push("var out: FsOut;");
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self.push("out.color0 = ocolor0;");
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self.push("return out;");
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}
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}
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self.indent = 0;
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self.push("}");
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Ok(())
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}
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fn emit_exec(
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&mut self,
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parsed: &ParsedShader,
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address: u32,
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count: u32,
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sequence: u32,
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current_alloc: AllocKind,
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) -> Result<(), &'static str> {
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for i in 0..(count as usize) {
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let triple_idx = address as usize + i;
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let base = triple_idx * 3;
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if base + 2 >= parsed.instructions.len() {
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return Err(reject::INSTR_OOB);
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}
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let words = [
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parsed.instructions[base],
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parsed.instructions[base + 1],
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parsed.instructions[base + 2],
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];
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let is_fetch = ((sequence >> (i * 2 + 1)) & 1) != 0;
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if is_fetch {
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match decode_fetch(words) {
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FetchInstruction::Vertex(vf) => self.emit_vfetch(&vf)?,
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FetchInstruction::Texture(tf) => {
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if tf.dimension != 1 {
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return Err(reject::TFETCH_NON2D);
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}
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self.emit_tfetch(&tf);
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}
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FetchInstruction::Unknown { .. } => return Err(reject::VFETCH_FMT),
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}
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} else {
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let alu = decode_alu(words);
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self.emit_alu(&alu, current_alloc)?;
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}
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}
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Ok(())
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}
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fn emit_alu(
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&mut self,
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alu: &AluInstruction,
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current_alloc: AllocKind,
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) -> Result<(), &'static str> {
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let a = format!("r[{}u]", alu.src_a & 0x7F);
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let b = format!("r[{}u]", alu.src_b & 0x7F);
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let c = format!("r[{}u]", alu.src_c & 0x7F);
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// Vector pipe.
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if alu.vector_write_mask != 0 {
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let expr = vector_expr(alu.vector_opcode, &a, &b, &c)
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.ok_or(reject::VEC_OP_UNSUPPORTED)?;
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let dst_reg = alu.vector_dest & 0x7F;
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if alu.vector_dest_is_export {
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self.emit_export(dst_reg, current_alloc, &expr, alu.vector_write_mask);
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} else {
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self.emit_masked_write(&format!("r[{dst_reg}u]"), &expr, alu.vector_write_mask);
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}
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}
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// Scalar pipe. Binary ops use (src_a.x, src_b.x); ps-variants use
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// src_a.x + running ps. `scl_src_a` mirrors the interpreter's
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// `scalar_src_is_ps` selector.
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let scl_src_a = if alu.scalar_src_is_ps {
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"ps".to_string()
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} else {
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format!("{}.x", a)
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};
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let scl_src_b = format!("{}.x", b);
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let expr = scalar_expr(alu.scalar_opcode, &scl_src_a, &scl_src_b, "ps")
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.ok_or(reject::SCL_OP_UNSUPPORTED)?;
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self.push(&format!("ps = {expr};"));
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if alu.scalar_write_mask != 0 {
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let v = "vec4<f32>(ps, ps, ps, ps)";
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let dst_reg = alu.scalar_dest & 0x7F;
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self.emit_masked_write(&format!("r[{dst_reg}u]"), v, alu.scalar_write_mask);
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}
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Ok(())
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}
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fn emit_masked_write(&mut self, lhs: &str, rhs: &str, mask: u8) {
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if mask == 0xF {
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self.push(&format!("{lhs} = {rhs};"));
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return;
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}
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self.push(&"{".to_string());
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self.indent += 1;
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self.push(&format!("let _prev = {lhs};"));
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self.push(&format!("let _new = {rhs};"));
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let mut components = Vec::new();
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let letters = ['x', 'y', 'z', 'w'];
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for (i, c) in letters.iter().enumerate() {
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if (mask >> i) & 1 == 1 {
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components.push(format!("_new.{c}"));
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} else {
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components.push(format!("_prev.{c}"));
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}
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}
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self.push(&format!(
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"{lhs} = vec4<f32>({}, {}, {}, {});",
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components[0], components[1], components[2], components[3]
|
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));
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self.indent -= 1;
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self.push("}");
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}
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fn emit_export(&mut self, dst_reg: u8, alloc: AllocKind, expr: &str, mask: u8) {
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// Xenos's export "register" indexing within an alloc range is
|
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// normally (alloc_base + offset). Since our CF stream doesn't
|
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// carry per-export slot offsets cleanly, use `alloc` to pick the
|
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// target.
|
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let lhs = match (self.stage, alloc) {
|
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(Stage::Vertex, AllocKind::Position) => "opos",
|
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(Stage::Vertex, AllocKind::Interpolators) => "ocolor",
|
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(Stage::Vertex, AllocKind::Colors) => "ocolor",
|
||||
(Stage::Vertex, _) => "ocolor", // fall through — any other alloc
|
||||
(Stage::Pixel, AllocKind::Colors) => "ocolor0",
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||||
(Stage::Pixel, _) => "ocolor0",
|
||||
};
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let _ = dst_reg; // per-slot export indexing reserved for a richer v2
|
||||
self.emit_masked_write(lhs, expr, mask);
|
||||
}
|
||||
|
||||
fn emit_vfetch(&mut self, vf: &crate::ucode::fetch::VertexFetch) -> Result<(), &'static str> {
|
||||
// v1: treat all vertex fetches as R32G32B32A32_FLOAT, stride = 4
|
||||
// dwords. Matches the interpreter's MVP semantics; unlocks more
|
||||
// formats alongside the CPU texture cache's format expansion.
|
||||
let fetch_const = (vf.raw[0] >> 5) & 0x1F;
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let src_reg = vf.src_register & 0x7F;
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||||
let dst_reg = vf.dest_register & 0x7F;
|
||||
self.push(&format!(
|
||||
"{{ let fc0 = xenos_consts.fetch[{}u]; \
|
||||
let base = (fc0 & 0xFFFFFFFCu) >> 2u; \
|
||||
let vidx = u32(r[{src_reg}u].x); \
|
||||
let addr = base + vidx * 4u; \
|
||||
let n = arrayLength(&vertex_buffer); \
|
||||
if (addr + 3u < n) {{ \
|
||||
r[{dst_reg}u] = vec4<f32>( \
|
||||
bitcast<f32>(vertex_buffer[addr + 0u]), \
|
||||
bitcast<f32>(vertex_buffer[addr + 1u]), \
|
||||
bitcast<f32>(vertex_buffer[addr + 2u]), \
|
||||
bitcast<f32>(vertex_buffer[addr + 3u])); \
|
||||
}} }}",
|
||||
fetch_const * 2,
|
||||
));
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn emit_tfetch(&mut self, tf: &crate::ucode::fetch::TextureFetch) {
|
||||
// v1: sample the single bound texture; UV = r[src].xy. P5's cache
|
||||
// publishes the `fetch_const=0` texture into `@group(1)`; slot
|
||||
// mismatch is a silent magenta for now.
|
||||
let src_reg = tf.src_register & 0x7F;
|
||||
let dst_reg = tf.dest_register & 0x7F;
|
||||
self.push(&format!(
|
||||
"r[{dst_reg}u] = textureSampleLevel(xenos_tex, xenos_samp, r[{src_reg}u].xy, 0.0);"
|
||||
));
|
||||
}
|
||||
}
|
||||
|
||||
fn vector_expr(op: u8, a: &str, b: &str, c: &str) -> Option<String> {
|
||||
let s = match op {
|
||||
vop::ADD => format!("({a} + {b})"),
|
||||
vop::MUL => format!("({a} * {b})"),
|
||||
vop::MAX => format!("max({a}, {b})"),
|
||||
vop::MIN => format!("min({a}, {b})"),
|
||||
vop::MAD => format!("({a} * {b} + {c})"),
|
||||
vop::DOT4 => format!("vec4<f32>(dot({a}, {b}))"),
|
||||
vop::DOT3 => format!("vec4<f32>(dot({a}.xyz, {b}.xyz))"),
|
||||
vop::DOT2_ADD => format!(
|
||||
"vec4<f32>({a}.x * {b}.x + {a}.y * {b}.y + {c}.x)"
|
||||
),
|
||||
vop::SEQ => format!(
|
||||
"vec4<f32>(select(0.0,1.0,{a}.x=={b}.x), select(0.0,1.0,{a}.y=={b}.y), select(0.0,1.0,{a}.z=={b}.z), select(0.0,1.0,{a}.w=={b}.w))"
|
||||
),
|
||||
vop::SGT => format!(
|
||||
"vec4<f32>(select(0.0,1.0,{a}.x>{b}.x), select(0.0,1.0,{a}.y>{b}.y), select(0.0,1.0,{a}.z>{b}.z), select(0.0,1.0,{a}.w>{b}.w))"
|
||||
),
|
||||
vop::SGE => format!(
|
||||
"vec4<f32>(select(0.0,1.0,{a}.x>={b}.x), select(0.0,1.0,{a}.y>={b}.y), select(0.0,1.0,{a}.z>={b}.z), select(0.0,1.0,{a}.w>={b}.w))"
|
||||
),
|
||||
vop::SNE => format!(
|
||||
"vec4<f32>(select(0.0,1.0,{a}.x!={b}.x), select(0.0,1.0,{a}.y!={b}.y), select(0.0,1.0,{a}.z!={b}.z), select(0.0,1.0,{a}.w!={b}.w))"
|
||||
),
|
||||
vop::FRC => format!("fract({a})"),
|
||||
vop::FLOOR => format!("floor({a})"),
|
||||
_ => return None,
|
||||
};
|
||||
Some(s)
|
||||
}
|
||||
|
||||
fn scalar_expr(op: u8, a: &str, b: &str, prev: &str) -> Option<String> {
|
||||
let s = match op {
|
||||
sop::ADDS => format!("({a} + {b})"),
|
||||
sop::ADDS_PREV => format!("({a} + {prev})"),
|
||||
sop::MULS => format!("({a} * {b})"),
|
||||
sop::MULS_PREV => format!("({a} * {prev})"),
|
||||
sop::MAXS => format!("max({a}, {b})"),
|
||||
sop::MINS => format!("min({a}, {b})"),
|
||||
sop::RCP => format!("xe_rcp({a})"),
|
||||
sop::RETAIN_PREV => prev.to_string(),
|
||||
_ => return None,
|
||||
};
|
||||
Some(s)
|
||||
}
|
||||
|
||||
#[cfg(test)]
|
||||
mod tests {
|
||||
use super::*;
|
||||
use crate::ucode::alu::{sop, vop};
|
||||
use crate::ucode::control_flow::ControlFlowInstruction;
|
||||
|
||||
fn synthetic_trivial_shader() -> ParsedShader {
|
||||
// Single Exec clause: ALU add r0 = r0 + r0; scalar_op = RETAIN_PREV
|
||||
// with full write-mask on vector, zero on scalar. Alloc(Position)
|
||||
// precedes so the ALU's export (if it were one) would target oPos.
|
||||
let w2 = (vop::ADD as u32)
|
||||
| ((sop::RETAIN_PREV as u32) << 6)
|
||||
| (0xF << 12) // vector_write_mask
|
||||
| (0u32 << 16); // vector_dest = 0
|
||||
ParsedShader {
|
||||
cf: vec![
|
||||
ControlFlowInstruction::Alloc {
|
||||
size: 1,
|
||||
kind: AllocKind::Position,
|
||||
},
|
||||
ControlFlowInstruction::Exec {
|
||||
address: 0,
|
||||
count: 1,
|
||||
sequence: 0,
|
||||
is_end: true,
|
||||
predicated: false,
|
||||
predicate_condition: false,
|
||||
},
|
||||
],
|
||||
instructions: vec![0, 0, w2],
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn trivial_shader_translates() {
|
||||
let shader = synthetic_trivial_shader();
|
||||
match translate(&shader, Stage::Vertex) {
|
||||
Translation::Ok(body) => {
|
||||
assert!(body.contains("fn vs_main"));
|
||||
assert!(body.contains("r[0u] = (r[0u] + r[0u]);"));
|
||||
assert!(body.contains("return out;"));
|
||||
}
|
||||
Translation::Reject(r) => panic!("rejected: {r}"),
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn combined_module_parses_as_wgsl() {
|
||||
let shader = synthetic_trivial_shader();
|
||||
let vs = match translate(&shader, Stage::Vertex) {
|
||||
Translation::Ok(body) => body,
|
||||
Translation::Reject(r) => panic!("VS rejected: {r}"),
|
||||
};
|
||||
let ps = match translate(&shader, Stage::Pixel) {
|
||||
Translation::Ok(body) => body,
|
||||
Translation::Reject(r) => panic!("PS rejected: {r}"),
|
||||
};
|
||||
let module = combine_stages(&vs, &ps);
|
||||
// naga is pinned as a dev-dep in this crate; if this fails the
|
||||
// translator is emitting invalid WGSL.
|
||||
match naga::front::wgsl::parse_str(&module) {
|
||||
Ok(_) => {}
|
||||
Err(e) => panic!(
|
||||
"emitted WGSL failed to parse:\n{}\n--- module ---\n{}",
|
||||
e, module
|
||||
),
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn loop_clause_rejected() {
|
||||
let shader = ParsedShader {
|
||||
cf: vec![ControlFlowInstruction::LoopStart {
|
||||
address: 0,
|
||||
loop_id: 0,
|
||||
}],
|
||||
instructions: vec![],
|
||||
};
|
||||
assert!(matches!(
|
||||
translate(&shader, Stage::Vertex),
|
||||
Translation::Reject(reject::CF_LOOP)
|
||||
));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn unsupported_op_rejected() {
|
||||
let w2 = (29u32) // VOP_MAX_A, not in v1 subset
|
||||
| ((sop::RETAIN_PREV as u32) << 6)
|
||||
| (0xF << 12);
|
||||
let shader = ParsedShader {
|
||||
cf: vec![ControlFlowInstruction::Exec {
|
||||
address: 0,
|
||||
count: 1,
|
||||
sequence: 0,
|
||||
is_end: true,
|
||||
predicated: false,
|
||||
predicate_condition: false,
|
||||
}],
|
||||
instructions: vec![0, 0, w2],
|
||||
};
|
||||
assert!(matches!(
|
||||
translate(&shader, Stage::Vertex),
|
||||
Translation::Reject(reject::VEC_OP_UNSUPPORTED)
|
||||
));
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user