xenia-gpu: end-to-end Xenos pipeline (PM4, ucode, EDRAM, resolve)
First real GPU implementation. Ring/PM4 frontend (ring_view,
ring_drain, pm4) drains the command processor; gpu_system owns the
threaded backend (DrainFence RPC + parker/fence helpers from M1) and
the MMIO-mapped register block (mmio_region).
Xenos shader frontend: ucode/{alu,control_flow,fetch,mod}.rs decode
the Xbox 360 microcode, translator.rs lowers it onto the WGSL
xenos_interp interpreter shader (shaders/xenos_interp.wgsl).
shader_metrics.rs counts decode/translate work.
Render state: draw_state, primitive, render_target_cache,
texture_cache, tiled_address (Xenos's swizzled tiled-memory layout),
xenos_constants (register field constants), edram (the 10 MiB EDRAM
model with MSAA), and resolve.rs (TILE_FLUSH copy-out — clear-resolve
plus bitwise-equivalent 32 bpp + 64 bpp paths landed). handle.rs
owns the typed GPU-resource handles the kernel hands out.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
249
crates/xenia-gpu/src/ucode/mod.rs
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249
crates/xenia-gpu/src/ucode/mod.rs
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//! Xenos (ATI R500-family) shader microcode decoder.
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//!
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//! Ground truth: `xenia-canary/src/xenia/gpu/ucode.h`. We parse only what a
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//! shader *interpreter* (P3 uber-shader) needs: control-flow clauses, ALU
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//! instructions (vector + scalar pipes), and fetch instructions (vertex +
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//! texture). The uber-shader consumes this IR directly; when a WGSL-emitting
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//! translator comes online in P7, it reuses the same parser.
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//!
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//! ## Binary layout
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//!
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//! A compiled shader has two sections back-to-back:
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//!
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//! 1. **Control-flow block** — `cf_count` 64-bit clause pairs. Canary packs
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//! two clauses into three 32-bit words:
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//! ```text
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//! word0 word1 word2
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//! [-CF_A (48)-][-CF_B (48)-]
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//! ```
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//! Word 0 is the low 32 of CF_A; word 1's low 16 bits finish CF_A and
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//! its high 16 bits start CF_B; word 2 holds CF_B's remaining 32 bits.
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//!
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//! 2. **Instruction block** — variable-size array of 96-bit ALU / fetch
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//! instructions. Each control-flow clause of kind `Exec*` references a
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//! contiguous range of these by `(address, count)` in dwords * 3.
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//!
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//! We read big-endian dwords straight out of guest memory (the `raw`
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//! `&[u32]` slice is already host-endian-corrected by the PM4 executor that
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//! cached the shader blob). See `ucode.h:218-256` for the exec clause bit
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//! layout and `:700-877` for the fetch/ALU mix.
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pub mod alu;
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pub mod control_flow;
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pub mod fetch;
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use self::alu::AluInstruction;
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use self::control_flow::{AllocKind, ControlFlowInstruction, decode_cf_pair};
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use self::fetch::FetchInstruction;
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/// CF-clause kind codes encoded into the WGSL-facing packed shader. Kept
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/// in sync with `shaders/xenos_interp.wgsl`'s `CF_KIND_*` constants.
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pub mod cf_kind {
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pub const EXEC: u32 = 0;
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pub const EXEC_END: u32 = 1;
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pub const ALLOC: u32 = 2;
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pub const EXIT: u32 = 3;
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pub const LOOP_START: u32 = 4;
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pub const LOOP_END: u32 = 5;
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pub const COND_JMP: u32 = 6;
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pub const COND_CALL: u32 = 7;
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pub const RETURN: u32 = 8;
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pub const UNKNOWN: u32 = 15;
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}
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/// Alloc-kind codes, packed into the aux dword of an `Alloc` clause.
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pub mod cf_alloc_kind {
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pub const POSITION: u32 = 0;
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pub const INTERPOLATORS: u32 = 1;
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pub const COLORS: u32 = 2;
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pub const MEMEXPORT: u32 = 3;
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pub const OTHER: u32 = 4;
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}
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/// Pack a [`ParsedShader`] into the dense dword layout the WGSL runtime
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/// interpreter expects:
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///
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/// ```text
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/// [0] cf_count
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/// [1 .. 1 + cf_count*3] CF table: (kind, primary, aux) triples per clause
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/// [1 + cf_count*3 ..] raw 3-dword instruction stream (ALU/fetch)
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/// ```
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///
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/// The CF table lets WGSL walk clauses without reconstructing bit-packed
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/// layouts on the GPU. Semantics per `kind`:
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///
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/// | kind | primary | aux |
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/// |-------------|----------------------------|------------------------------|
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/// | EXEC/EXEC_END | address (in triples) | (sequence<<8) \| count |
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/// | ALLOC | alloc_kind (see cf_alloc_kind) | size |
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/// | EXIT | 0 | 0 |
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/// | LOOP_START | address | loop_id |
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/// | LOOP_END | address | loop_id |
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/// | COND_JMP | target | predicate flags |
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/// | COND_CALL | target | 0 |
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/// | RETURN | 0 | 0 |
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/// | UNKNOWN | opcode | 0 |
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pub fn pack_for_wgsl(parsed: &ParsedShader) -> Vec<u32> {
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let cf_count = parsed.cf.len() as u32;
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let mut out = Vec::with_capacity(1 + (cf_count as usize) * 3 + parsed.instructions.len());
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out.push(cf_count);
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for clause in &parsed.cf {
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let (kind, primary, aux) = encode_cf(*clause);
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out.push(kind);
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out.push(primary);
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out.push(aux);
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}
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out.extend_from_slice(&parsed.instructions);
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out
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}
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fn encode_cf(c: ControlFlowInstruction) -> (u32, u32, u32) {
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use ControlFlowInstruction::*;
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match c {
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Exec {
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address,
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count,
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sequence,
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is_end,
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predicated,
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predicate_condition,
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} => {
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let pred_bits = (predicated as u32) | ((predicate_condition as u32) << 1);
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let kind = if is_end { cf_kind::EXEC_END } else { cf_kind::EXEC }
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| (pred_bits << 8);
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(kind, address, (sequence << 8) | count)
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}
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Alloc { size, kind } => {
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let akind = match kind {
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AllocKind::Position => cf_alloc_kind::POSITION,
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AllocKind::Interpolators => cf_alloc_kind::INTERPOLATORS,
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AllocKind::Colors => cf_alloc_kind::COLORS,
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AllocKind::Memexport => cf_alloc_kind::MEMEXPORT,
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AllocKind::Other => cf_alloc_kind::OTHER,
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};
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(cf_kind::ALLOC, akind, size)
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}
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Exit => (cf_kind::EXIT, 0, 0),
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LoopStart { address, loop_id } => (cf_kind::LOOP_START, address, loop_id),
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LoopEnd { address, loop_id } => (cf_kind::LOOP_END, address, loop_id),
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CondJmp {
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target,
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predicated,
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predicate_condition,
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} => {
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let pred_bits = (predicated as u32) | ((predicate_condition as u32) << 1);
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(cf_kind::COND_JMP, target, pred_bits)
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}
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CondCall { target } => (cf_kind::COND_CALL, target, 0),
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Return => (cf_kind::RETURN, 0, 0),
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Unknown { opcode } => (cf_kind::UNKNOWN, opcode as u32, 0),
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}
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}
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/// One instruction word set from the instruction-block section. Xenos packs
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/// ALU and fetch instructions identically (96 bits each); the owning exec
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/// clause's "sequence" bitmap decides which is which.
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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pub enum DecodedInstruction {
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/// ALU pipe (vector ALU + optional co-issued scalar ALU).
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Alu(AluInstruction),
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/// Vertex or texture fetch.
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Fetch(FetchInstruction),
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}
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/// Parsed shader: the control-flow clause list + the raw 32-bit instruction
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/// words. The uber-shader / translator is expected to index into
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/// `instructions` based on `(clause.address * 3, clause.count * 3)`.
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#[derive(Debug, Clone, Default)]
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pub struct ParsedShader {
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pub cf: Vec<ControlFlowInstruction>,
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/// Raw instruction dwords. Each 3-dword triple is one ALU or fetch
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/// instruction; the owning `Exec` clause's `sequence` bitmap picks the
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/// kind.
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pub instructions: Vec<u32>,
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}
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/// Decode a shader blob. `raw_dwords` is a host-endian slice of the entire
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/// microcode buffer (control flow + instructions). Heuristic: CF dword count
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/// is encoded in the first word's low 12 bits of the last exec clause —
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/// canary iterates until it hits a clause of kind `Exit`. We do the same.
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pub fn parse_shader(raw_dwords: &[u32]) -> ParsedShader {
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let mut cf = Vec::new();
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// CF clauses are 48-bit (word1 lo 16 + word0 = 48 or so per canary's
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// layout). Walk pairs of 3 dwords per pair of clauses.
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let mut i = 0usize;
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while i + 2 < raw_dwords.len() {
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let a = decode_cf_pair(raw_dwords[i], raw_dwords[i + 1], raw_dwords[i + 2]);
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let (first, second) = a;
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let seen_exit = matches!(
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first,
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ControlFlowInstruction::Exit | ControlFlowInstruction::Unknown { .. }
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) || matches!(
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second,
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ControlFlowInstruction::Exit | ControlFlowInstruction::Unknown { .. }
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);
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cf.push(first);
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cf.push(second);
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i += 3;
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if seen_exit {
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break;
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}
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}
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// Everything after `i` dwords is the instruction block.
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let instructions = raw_dwords[i..].to_vec();
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ParsedShader { cf, instructions }
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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#[test]
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fn empty_blob_parses_empty() {
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let p = parse_shader(&[]);
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assert!(p.cf.is_empty());
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assert!(p.instructions.is_empty());
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}
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#[test]
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fn pack_for_wgsl_layout_is_correct() {
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// Build a tiny ParsedShader by hand and verify the packed form.
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let parsed = ParsedShader {
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cf: vec![
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ControlFlowInstruction::Exec {
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address: 0x10,
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count: 3,
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sequence: 0b1010,
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is_end: false,
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predicated: false,
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predicate_condition: false,
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},
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ControlFlowInstruction::Exit,
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],
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instructions: vec![0x1111, 0x2222, 0x3333],
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};
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let packed = pack_for_wgsl(&parsed);
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assert_eq!(packed[0], 2, "cf_count");
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// First clause: EXEC, address=0x10, aux = (sequence<<8)|count = 0x0A03
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assert_eq!(packed[1] & 0xFF, cf_kind::EXEC);
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assert_eq!(packed[2], 0x10);
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assert_eq!(packed[3], (0b1010 << 8) | 3);
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// Second clause: EXIT
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assert_eq!(packed[4] & 0xFF, cf_kind::EXIT);
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// Instruction block starts at 1 + 2*3 = 7
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assert_eq!(packed[7..], [0x1111, 0x2222, 0x3333]);
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}
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#[test]
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fn trivial_exit_clause_stops_parsing() {
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// Two clauses: [NOP (kind=0), EXIT (kind=1)] encoded per canary.
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// Exit clause is opcode 1 in the top 4 bits of the upper 16 bits.
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let w0 = 0u32; // clause A body
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let w1 = (1u32 << 12) << 16; // upper 16 bits = 0x1000 → opcode=1 (EXIT) for clause A
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let w2 = 0u32;
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let p = parse_shader(&[w0, w1, w2, 0xDEAD_BEEF]);
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assert!(!p.cf.is_empty());
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// Exit detected → remaining dword is instruction data.
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assert_eq!(p.instructions, vec![0xDEAD_BEEF]);
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}
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}
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