wip(probe): throwaway iterate-iterate-2AZ-vsync probe instrumentation

Uncommitted experimental probe code preserved for handoff. Per running
memory these probes are inert/throwaway diagnostics, not production fixes.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

crates/xenia-app/src/main.rs

@@ -2451,6 +2451,23 @@ fn coord_pre_round(
     // restores the ~60 Hz rate at the cost of bit-exact run reproducibility,
     // which is acceptable under `--parallel` (M11 already documented
     // `--parallel` as non-deterministic by design).
+    // 2.AZ — lockstep v-sync clock source.
+    //
+    // CORRECTION to the 2.AX framing (this iterate, measured): the lockstep
+    // ticker's instruction-count clock does NOT freeze after the post-boot
+    // wedge. `stats.instruction_count` is monotone & global and climbs the
+    // whole run (reaches the full -n budget) because the "wedge" is not a
+    // true all-blocked stall — tids 7/8/9/10 stay `Ready` and spin, so
+    // instructions keep retiring and the ticker keeps crossing the 150k
+    // threshold (~3 333 crossings @ -n 500M). The measured ~73-v-sync/run
+    // cap on *delivered* interrupts is the INJECTOR throughput
+    // (INTERRUPT_QUEUE_CAP=4 + one drain/round in
+    // `try_inject_graphics_interrupt`), NOT the clock. And even a delivered
+    // r3==0 VSync ISR never signals Event 0x10e8 — it takes the opt_callback
+    // `+44` path, a confirmed structural dead-end (2.AV/2.AX). So the
+    // cadence clock is NOT the wedge gate; the original instruction-count
+    // source is retained (driving a timebase ticker off `max_timebase`
+    // PLATEAUS when the lead thread blocks and regresses delivery 73→13).
     let fired = if kernel.parallel_active {
         kernel.interrupts.tick_vsync_wallclock()
     } else {