xenia-cpu: VMX128, FPSCR, decoder split, scheduler, decode/block caches
Split the monolithic interpreter into cohesive modules: dedicated decoder (decoder.rs) producing 8-byte DecodedInstr; opcode tables (opcode.rs); explicit traps (trap.rs); FPSCR helpers (fpscr.rs); overflow/carry helpers (overflow.rs); a 4 KiB-page-versioned decode cache and basic-block cache (block_cache.rs); and a full VMX/VMX128 implementation (vmx.rs) covering AltiVec + Xenon's 128-bit extensions. Add the parallel-execution substrate behind --parallel: a 7-party phaser (phaser.rs) for round-based barrier sync, ReservationTable (reservation.rs) for guest LL/SC, and the per-HW-thread scheduler core (scheduler.rs) that owns ThreadRefs, runqueues, and pending IRQs. Disassembler is now the single source of truth: disasm.rs gains the full base + extended + VMX128 mnemonic set, with golden JSON fixtures and a disasm_goldens test suite. Add a criterion-style interpreter bench. context.rs grows the per-thread state the new modules need (reservation slot, FPSCR, vector regs). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
@@ -77,6 +77,9 @@ impl DecodedInstr {
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/// OE bit (bit 21) - overflow enable
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#[inline] pub fn oe(&self) -> bool { extract_bits(self.raw, 21, 21) != 0 }
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/// TO field (bits 6-10) for tw/twi/td/tdi trap instructions.
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#[inline] pub fn to(&self) -> u32 { extract_bits(self.raw, 6, 10) }
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/// MB, ME fields for rotate instructions
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#[inline] pub fn mb(&self) -> u32 { extract_bits(self.raw, 21, 25) }
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#[inline] pub fn me(&self) -> u32 { extract_bits(self.raw, 26, 30) }
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@@ -142,6 +145,24 @@ impl DecodedInstr {
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#[inline] pub fn nb(&self) -> u32 { extract_bits(self.raw, 16, 20) }
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}
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/// Extract the 5-bit `UIMM` (`VX128_3`) / `IMM` (`VX128_4`) field. Canary
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/// packs both formats with LSB-bits 16-20 holding the field, which is
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/// MSB bits 11-15 in our `extract_bits` convention. For `vpkd3d128` /
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/// `vupkd3d128` the decoded selector is `type = UIMM >> 2` (3 bits; valid
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/// values 0-6 per [`crate::vmx::D3dPackType`], 7 is undocumented /
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/// undefined in canary) and `pack = UIMM & 0x3` (output-slot layout for
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/// `vpkd3d128` only, `vupkd3d128` ignores it).
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///
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/// First-Pixels M3: the interpreter previously used a hand-rolled
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/// `(instr.raw >> 6) & 0x7` that was **LSB-numbered** and extracted
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/// bits from a completely different part of the word (the
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/// secondary-opcode region). Centralizing the extractor here matches
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/// canary's `FormatVX128_{3,4}::{UIMM,IMM}` field semantics exactly.
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#[inline]
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pub fn extract_vx128_uimm5(raw: u32) -> u32 {
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extract_bits(raw, 11, 15)
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}
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/// Decode a 32-bit PPC instruction into its opcode.
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/// Direct translation of the C++ LookupOpcode from ppc_opcode_lookup_gen.cc.
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pub fn decode(raw: u32, addr: u32) -> DecodedInstr {
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@@ -149,6 +170,123 @@ pub fn decode(raw: u32, addr: u32) -> DecodedInstr {
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DecodedInstr { opcode, raw, addr }
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}
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// Perf tier-2 — direct-mapped PC-keyed decode cache.
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//
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// The interpreter hot path spends ~15-25% of its time in `decode()`
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// parsing the raw u32 and walking the primary+secondary opcode tables.
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// For non-self-modifying guest code — the common case past the XEX
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// loader — `decode(raw, pc)` is purely a function of `(raw, pc)` and
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// the output is `Copy + 16B`. A direct-mapped cache indexed by
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// `(pc >> 2) & MASK` gives the interpreter a 1-comparison fast path,
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// at the cost of one branch and a 1.5 MiB region of memory.
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//
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// Invalidation piggybacks on `xenia_memory::GuestMemory::page_version`
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// (P5 texture-cache invalidation): every cache entry carries the page
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// version that was active at decode time; on lookup we compare against
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// the current version of the containing 4 KiB page. Any write to the
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// page bumps the counter, so the next decode on that PC is a miss that
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// refills.
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/// Number of direct-mapped entries. 2^16 = 65,536 slots, one PPC
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/// instruction address per slot — enough for every hot code path in a
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/// typical Xbox 360 title to stay resident without collision.
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const DECODE_CACHE_SIZE: usize = 1 << 16;
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const DECODE_CACHE_MASK: u32 = (DECODE_CACHE_SIZE - 1) as u32;
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#[derive(Clone, Copy)]
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struct DecodeCacheEntry {
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/// Guest PC this entry was decoded at. Used as the tag on lookup; a
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/// mismatch means the slot was last populated by a different PC that
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/// shares the same low-16 index.
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pc: u32,
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/// Page version at decode time (from `GuestMemory::page_version(pc)`).
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/// Zero means "unused slot" since real page versions start at 1.
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page_version: u64,
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decoded: DecodedInstr,
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}
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impl DecodeCacheEntry {
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const fn empty() -> Self {
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// `Invalid` is the decoder's "unrecognized opcode" sentinel; we
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// use it here as the empty-slot marker. Real misses compare `pc`,
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// not the opcode, so the sentinel choice is cosmetic.
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Self {
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pc: 0,
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page_version: 0,
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decoded: DecodedInstr {
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opcode: PpcOpcode::Invalid,
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raw: 0,
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addr: 0,
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},
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}
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}
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}
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/// Direct-mapped PC-keyed decode cache. One instance shared across all
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/// HW threads (PC is thread-independent; entries are read-only once
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/// filled). Not thread-safe — the single scheduler thread owns it.
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pub struct DecodeCache {
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slots: Box<[DecodeCacheEntry]>,
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hits: u64,
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misses: u64,
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invalidations: u64,
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}
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impl Default for DecodeCache {
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fn default() -> Self {
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Self::new()
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}
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}
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impl DecodeCache {
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pub fn new() -> Self {
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Self {
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slots: vec![DecodeCacheEntry::empty(); DECODE_CACHE_SIZE].into_boxed_slice(),
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hits: 0,
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misses: 0,
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invalidations: 0,
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}
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}
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/// Look up (or fill) the decoded form of the instruction at `pc`.
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/// `raw` is the fetched instruction word; `current_page_version` is
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/// `mem.page_version(pc)` — the caller has it cheaper than we do,
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/// since they're already touching `mem` to fetch `raw`.
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#[inline]
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pub fn lookup(&mut self, pc: u32, raw: u32, current_page_version: u64) -> DecodedInstr {
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let idx = ((pc >> 2) & DECODE_CACHE_MASK) as usize;
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// Safety: `idx` is masked into `[0, DECODE_CACHE_SIZE)` so the
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// slice access is always in-bounds. Opt-out of the bounds check
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// for the hot path.
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let entry = unsafe { self.slots.get_unchecked_mut(idx) };
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if entry.pc == pc && entry.page_version == current_page_version {
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self.hits += 1;
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return entry.decoded;
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}
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if entry.pc == pc && entry.page_version != current_page_version {
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self.invalidations += 1;
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}
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self.misses += 1;
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let decoded = decode(raw, pc);
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*entry = DecodeCacheEntry {
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pc,
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page_version: current_page_version,
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decoded,
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};
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decoded
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}
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pub fn hits(&self) -> u64 {
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self.hits
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}
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pub fn misses(&self) -> u64 {
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self.misses
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}
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pub fn invalidations(&self) -> u64 {
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self.invalidations
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}
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}
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fn lookup_opcode(code: u32) -> PpcOpcode {
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match extract_bits(code, 0, 5) {
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2 => PpcOpcode::tdi,
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@@ -781,6 +919,57 @@ mod tests {
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assert_eq!(instr.d(), 0x20);
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}
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#[test]
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fn decode_cache_miss_fills_then_hit() {
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let mut cache = DecodeCache::new();
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let raw: u32 = (14 << 26) | (3 << 21) | (1 << 16) | 0x10;
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let pc = 0x8200_0000u32;
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let first = cache.lookup(pc, raw, 1);
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assert_eq!(first.opcode, PpcOpcode::addi);
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assert_eq!(cache.hits(), 0);
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assert_eq!(cache.misses(), 1);
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// Same pc, same version → cache hit, no new decode.
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let second = cache.lookup(pc, raw, 1);
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assert_eq!(second.opcode, PpcOpcode::addi);
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assert_eq!(cache.hits(), 1);
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assert_eq!(cache.misses(), 1);
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}
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#[test]
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fn decode_cache_stale_version_refills() {
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let mut cache = DecodeCache::new();
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// First fill with an `addi`.
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let raw_addi: u32 = (14 << 26) | (3 << 21) | (1 << 16) | 0x10;
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let pc = 0x8200_0000u32;
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cache.lookup(pc, raw_addi, 1);
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// Guest rewrote the page: same pc, different raw + bumped version.
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// Cache must refill — not return the stale `addi`.
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let raw_lwz: u32 = (32 << 26) | (5 << 21) | (1 << 16) | 0x20;
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let refreshed = cache.lookup(pc, raw_lwz, 2);
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assert_eq!(refreshed.opcode, PpcOpcode::lwz);
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assert_eq!(cache.invalidations(), 1);
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assert_eq!(cache.misses(), 2);
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}
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#[test]
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fn decode_cache_pc_collision_refills() {
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// Two PCs that hash to the same slot (pc >> 2 low 16 bits equal)
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// must not alias. Slot index = ((pc >> 2) & 0xFFFF) — pick two
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// PCs 4 * 2^16 bytes apart.
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let mut cache = DecodeCache::new();
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let pc_a = 0x8200_0000u32;
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let pc_b = pc_a.wrapping_add(0x0004_0000u32); // (>> 2) differs by 2^16
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let raw_addi: u32 = (14 << 26) | (3 << 21) | (1 << 16) | 0x10;
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let raw_lwz: u32 = (32 << 26) | (5 << 21) | (1 << 16) | 0x20;
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cache.lookup(pc_a, raw_addi, 1);
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// Different pc but same slot → miss + refill.
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cache.lookup(pc_b, raw_lwz, 1);
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// First pc comes back → miss + refill (slot was taken by pc_b).
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let back = cache.lookup(pc_a, raw_addi, 1);
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assert_eq!(back.opcode, PpcOpcode::addi);
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assert_eq!(cache.misses(), 3);
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}
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#[test]
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fn test_decode_branch() {
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// b +0x100 => opcode 18, LI=0x40 (shifted left 2 = 0x100), AA=0, LK=0
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@@ -816,4 +1005,103 @@ mod tests {
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assert_eq!(extract_bits(0x8000_0000, 0, 0), 1);
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assert_eq!(extract_bits(0x0000_0001, 31, 31), 1);
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}
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// VMX128 register-name extraction. Locks the canonical bit positions
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// (decoder.rs is the single source of truth — the analysis crate's
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// old `ppc.rs` had different positions, which produced wrong printed
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// register names; the bug was silent because the interpreter never
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// used those extractors). Each test poke-bits exactly the slots the
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// accessor reads and asserts the assembled register number.
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fn vmx128_test_word(va21: u32, vd6_10: u32, vd21: u32, vd22: u32,
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vb16_20: u32, vb28: u32, vb30: u32) -> u32 {
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// PPC bit i -> LSB position 31-i.
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(vd6_10 << (31 - 10))
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| (va21 << (31 - 21)) // va128 high bit at PPC 29 in some forms — kept 0 here
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| (vd21 << (31 - 21))
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| (vd22 << (31 - 22))
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| (vb16_20 << (31 - 20))
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| (vb28 << (31 - 28))
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| (vb30 << (31 - 30))
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}
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#[test]
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fn vmx128_vd128_low_5_bits_only() {
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// vd_lo = 0..31, vd_b21 = 0, vd_b22 = 0 → vd128 = vd_lo
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for r in 0..32u32 {
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let raw = (r as u32) << (31 - 10);
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let d = DecodedInstr { opcode: PpcOpcode::Invalid, raw, addr: 0 };
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assert_eq!(d.vd128(), r as usize, "vd_lo={r}");
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}
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}
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#[test]
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fn vmx128_vd128_bit21_adds_32() {
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// vd_lo = 0, vd_b21 = 1, vd_b22 = 0 → vd128 = 32
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let raw = (0u32 << (31 - 10)) | (1u32 << (31 - 21));
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let d = DecodedInstr { opcode: PpcOpcode::Invalid, raw, addr: 0 };
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assert_eq!(d.vd128(), 32);
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}
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#[test]
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fn vmx128_vd128_bit22_adds_64() {
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// vd_lo = 0, vd_b21 = 0, vd_b22 = 1 → vd128 = 64
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let raw = (0u32 << (31 - 10)) | (1u32 << (31 - 22));
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let d = DecodedInstr { opcode: PpcOpcode::Invalid, raw, addr: 0 };
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assert_eq!(d.vd128(), 64);
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}
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#[test]
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fn vmx128_vd128_full_127() {
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// vd_lo = 31, vd_b21 = 1, vd_b22 = 1 → vd128 = 127
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let raw = (31u32 << (31 - 10))
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| (1u32 << (31 - 21))
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| (1u32 << (31 - 22));
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let d = DecodedInstr { opcode: PpcOpcode::Invalid, raw, addr: 0 };
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assert_eq!(d.vd128(), 127);
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}
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#[test]
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fn vmx128_va128_uses_bit29() {
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// va128 = bits 6-10 + bit 29. va_lo = 7, bit 29 = 1 → va128 = 7 | 32 = 39.
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let raw = (7u32 << (31 - 10)) | (1u32 << (31 - 29));
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let d = DecodedInstr { opcode: PpcOpcode::Invalid, raw, addr: 0 };
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assert_eq!(d.va128(), 39);
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}
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#[test]
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fn vmx128_vb128_uses_bits28_and_30() {
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// vb128 = bits 16-20 + bit 28 + bit 30. Low 5 = 5, bit 28 = 1 → +32, bit 30 = 1 → +64.
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let raw = (5u32 << (31 - 20))
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| (1u32 << (31 - 28))
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| (1u32 << (31 - 30));
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let d = DecodedInstr { opcode: PpcOpcode::Invalid, raw, addr: 0 };
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assert_eq!(d.vb128(), 5 | 32 | 64);
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}
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#[test]
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fn vmx128_vs128_aliases_vd128() {
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// vs128 must always equal vd128.
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for r in [0u32, 31, 32, 64, 96, 127] {
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let lo = r & 0x1F;
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let b21 = (r >> 5) & 1;
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let b22 = (r >> 6) & 1;
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let raw = (lo << (31 - 10))
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| (b21 << (31 - 21))
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| (b22 << (31 - 22));
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let d = DecodedInstr { opcode: PpcOpcode::Invalid, raw, addr: 0 };
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assert_eq!(d.vd128(), r as usize, "vd128 mismatch for r={r}");
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assert_eq!(d.vs128(), r as usize, "vs128 mismatch for r={r}");
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assert_eq!(d.vd128(), d.vs128());
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}
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}
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#[test]
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#[allow(dead_code)]
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fn _vmx128_test_word_helper_compiles() {
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// Keep the helper validated against the real accessor.
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let raw = vmx128_test_word(0, 5, 1, 1, 0, 0, 0);
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let d = DecodedInstr { opcode: PpcOpcode::Invalid, raw, addr: 0 };
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assert_eq!(d.vd128(), 5 | 32 | 64);
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}
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}
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