xenia-cpu: VMX128, FPSCR, decoder split, scheduler, decode/block caches
Split the monolithic interpreter into cohesive modules: dedicated decoder (decoder.rs) producing 8-byte DecodedInstr; opcode tables (opcode.rs); explicit traps (trap.rs); FPSCR helpers (fpscr.rs); overflow/carry helpers (overflow.rs); a 4 KiB-page-versioned decode cache and basic-block cache (block_cache.rs); and a full VMX/VMX128 implementation (vmx.rs) covering AltiVec + Xenon's 128-bit extensions. Add the parallel-execution substrate behind --parallel: a 7-party phaser (phaser.rs) for round-based barrier sync, ReservationTable (reservation.rs) for guest LL/SC, and the per-HW-thread scheduler core (scheduler.rs) that owns ThreadRefs, runqueues, and pending IRQs. Disassembler is now the single source of truth: disasm.rs gains the full base + extended + VMX128 mnemonic set, with golden JSON fixtures and a disasm_goldens test suite. Add a criterion-style interpreter bench. context.rs grows the per-thread state the new modules need (reservation slot, FPSCR, vector regs). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
384
crates/xenia-cpu/src/fpscr.rs
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384
crates/xenia-cpu/src/fpscr.rs
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@@ -0,0 +1,384 @@
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//! FPSCR (Floating-Point Status and Control Register) maintenance.
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//!
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//! Scope per project plan: rounding modes honoured, plus the exception bits
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//! games actually read (FX, FEX, VX, OX, UX, ZX, XX, FI, FPRF). Enabled-
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//! exception dispatch (FE[0,1], VE/OE/UE/ZE/XE) is *not* modelled — games
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//! running on Xenon almost never take FP traps.
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//!
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//! Bit layout (PowerISA, MSB-0 numbering; stored in a u32 with bit 31 = MSB):
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//!
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//! | PPC bit | u32 mask | Name |
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//! |---------|-------------------------|-------------|
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//! | 0 | `1<<31` | FX |
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//! | 1 | `1<<30` | FEX |
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//! | 2 | `1<<29` | VX (summary)|
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//! | 3 | `1<<28` | OX |
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//! | 4 | `1<<27` | UX |
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//! | 5 | `1<<26` | ZX |
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//! | 6 | `1<<25` | XX |
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//! | 7 | `1<<24` | VXSNAN |
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//! | 8 | `1<<23` | VXISI |
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//! | 9 | `1<<22` | VXIDI |
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//! | 10 | `1<<21` | VXZDZ |
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//! | 11 | `1<<20` | VXIMZ |
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//! | 12 | `1<<19` | VXVC |
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//! | 13 | `1<<18` | FR |
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//! | 14 | `1<<17` | FI |
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//! | 15..19 | `0xF8000 >> 15` @ 15..19 | FPRF (5 bits)|
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//! | 21 | `1<<10` | VXSOFT |
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//! | 22 | `1<<9` | VXSQRT |
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//! | 23 | `1<<8` | VXCVI |
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//! | 30..31 | `0x3` | RN (2 bits) |
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use crate::context::PpcContext;
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pub const FX: u32 = 1 << 31;
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pub const FEX: u32 = 1 << 30;
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pub const VX: u32 = 1 << 29;
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pub const OX: u32 = 1 << 28;
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pub const UX: u32 = 1 << 27;
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pub const ZX: u32 = 1 << 26;
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pub const XX: u32 = 1 << 25;
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pub const VXSNAN: u32 = 1 << 24;
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pub const VXISI: u32 = 1 << 23;
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pub const VXIDI: u32 = 1 << 22;
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pub const VXZDZ: u32 = 1 << 21;
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pub const VXIMZ: u32 = 1 << 20;
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pub const VXVC: u32 = 1 << 19;
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pub const FR: u32 = 1 << 18;
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pub const FI: u32 = 1 << 17;
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pub const FPRF_MASK: u32 = 0x1F << 12; // bits 15..19
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pub const VXSOFT: u32 = 1 << 10;
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pub const VXSQRT: u32 = 1 << 9;
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pub const VXCVI: u32 = 1 << 8;
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pub const RN_MASK: u32 = 0x3;
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/// Union of all VX* bits (used for the VX summary recomputation).
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pub const VX_ALL: u32 = VXSNAN | VXISI | VXIDI | VXZDZ | VXIMZ | VXVC | VXSOFT | VXSQRT | VXCVI;
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/// FPRF classification codes (5-bit, placed in FPSCR bits 15..19).
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/// The high bit ("C" in PowerISA) distinguishes ±zero/±denormal/QNaN from
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/// ±normal/±inf. The next 4 bits are (FL, FG, FE, FU) = (less, greater, equal, unordered).
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pub mod fprf {
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pub const QNAN: u8 = 0b1_0001;
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pub const NEG_INF: u8 = 0b0_1001;
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pub const NEG_NORMAL: u8 = 0b0_1000;
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pub const NEG_DENORMAL: u8 = 0b1_1000;
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pub const NEG_ZERO: u8 = 0b1_0010;
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pub const POS_ZERO: u8 = 0b0_0010;
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pub const POS_DENORMAL: u8 = 0b1_0100;
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pub const POS_NORMAL: u8 = 0b0_0100;
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pub const POS_INF: u8 = 0b0_0101;
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}
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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pub enum RoundingMode {
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NearestEven, // RN=00
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TowardZero, // RN=01
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TowardPosInf, // RN=10
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TowardNegInf, // RN=11
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}
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pub fn rounding_mode(ctx: &PpcContext) -> RoundingMode {
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match ctx.fpscr & RN_MASK {
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0 => RoundingMode::NearestEven,
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1 => RoundingMode::TowardZero,
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2 => RoundingMode::TowardPosInf,
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_ => RoundingMode::TowardNegInf,
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}
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}
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/// Classify a finite f64 into its FPRF 5-bit code.
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pub fn classify_fprf(v: f64) -> u8 {
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if v.is_nan() {
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fprf::QNAN
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} else if v.is_infinite() {
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if v.is_sign_negative() { fprf::NEG_INF } else { fprf::POS_INF }
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} else if v == 0.0 {
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if v.is_sign_negative() { fprf::NEG_ZERO } else { fprf::POS_ZERO }
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} else if v.is_subnormal() {
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if v.is_sign_negative() { fprf::NEG_DENORMAL } else { fprf::POS_DENORMAL }
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} else if v.is_sign_negative() { fprf::NEG_NORMAL } else { fprf::POS_NORMAL }
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}
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/// Write FPRF into FPSCR, preserving other bits.
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pub fn set_fprf(ctx: &mut PpcContext, code: u8) {
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ctx.fpscr = (ctx.fpscr & !FPRF_MASK) | ((code as u32 & 0x1F) << 12);
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}
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/// Set one or more exception bits on FPSCR, maintaining FX (sticky set on any
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/// new exception) and VX (summary of VX* bits).
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pub fn set_exception(ctx: &mut PpcContext, bits: u32) {
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let prev = ctx.fpscr;
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let new = prev | bits;
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// FX is sticky-set if any new non-sticky bit transitions to 1. PPC defines
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// FX as "any of OX, UX, ZX, XX, VX* newly set". Compute the transition set.
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let transition = (new & !prev) & (OX | UX | ZX | XX | VX_ALL);
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let mut updated = new;
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if transition != 0 {
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updated |= FX;
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}
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// Recompute VX summary from any VX* bits currently set.
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if (updated & VX_ALL) != 0 { updated |= VX; }
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ctx.fpscr = updated;
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}
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/// Classify the inputs of a floating-point arithmetic op and set appropriate
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/// VX* bits. Returns true if any invalid-operation was detected (caller may
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/// want to write a default QNaN result).
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///
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/// Detected cases:
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/// * any SNaN input → VXSNAN
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/// * infinity - infinity (same sign) → VXISI
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/// * 0 / 0 → VXZDZ
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/// * infinity / infinity → VXIDI
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/// * 0 * infinity → VXIMZ
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pub fn check_invalid_add(ctx: &mut PpcContext, a: f64, b: f64, sub: bool) -> bool {
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let mut bits = 0u32;
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if is_snan(a) || is_snan(b) { bits |= VXSNAN; }
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if a.is_infinite() && b.is_infinite() {
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// For add: VXISI iff same-sign(a,b) negated — inf - inf
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// For sub: VXISI iff same-sign(a,b) — (+inf) - (+inf) or (-inf) - (-inf)
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let both_pos = a.is_sign_positive() && b.is_sign_positive();
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let both_neg = a.is_sign_negative() && b.is_sign_negative();
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if sub {
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if both_pos || both_neg { bits |= VXISI; }
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} else {
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// add: opposite signs cancel to inf-inf
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if a.is_sign_positive() != b.is_sign_positive() { bits |= VXISI; }
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}
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}
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if bits != 0 { set_exception(ctx, bits); return true; }
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false
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}
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pub fn check_invalid_mul(ctx: &mut PpcContext, a: f64, b: f64) -> bool {
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let mut bits = 0u32;
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if is_snan(a) || is_snan(b) { bits |= VXSNAN; }
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let zero_times_inf =
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(a == 0.0 && b.is_infinite()) || (b == 0.0 && a.is_infinite());
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if zero_times_inf { bits |= VXIMZ; }
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if bits != 0 { set_exception(ctx, bits); return true; }
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false
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}
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pub fn check_invalid_div(ctx: &mut PpcContext, a: f64, b: f64) -> bool {
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let mut bits = 0u32;
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if is_snan(a) || is_snan(b) { bits |= VXSNAN; }
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if a == 0.0 && b == 0.0 { bits |= VXZDZ; }
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if a.is_infinite() && b.is_infinite() { bits |= VXIDI; }
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if bits != 0 { set_exception(ctx, bits); return true; }
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false
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}
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/// Divide-by-zero (finite nonzero / 0) — sets ZX but not VX.
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pub fn check_zero_divide(ctx: &mut PpcContext, a: f64, b: f64) {
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if b == 0.0 && a != 0.0 && !a.is_nan() && !a.is_infinite() {
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set_exception(ctx, ZX);
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}
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}
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/// Post-op: classify the result and update FPRF + detect overflow/underflow/inexact.
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/// `inputs_finite` lets us suppress OX for ops whose output is infinite because
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/// an input already was.
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pub fn update_after_op(ctx: &mut PpcContext, result: f64, inputs_were_finite: bool) {
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let mut bits = 0u32;
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if result.is_infinite() && inputs_were_finite {
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bits |= OX;
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}
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if result.is_subnormal() {
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bits |= UX;
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}
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if bits != 0 { set_exception(ctx, bits); }
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set_fprf(ctx, classify_fprf(result));
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}
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/// Test whether an f64 is a signalling NaN.
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/// In IEEE 754-2008 (binary64), the signalling bit is the high bit of the
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/// mantissa. SNaN has it clear, QNaN has it set. NaN with high mantissa bit
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/// clear (and mantissa nonzero) is an SNaN.
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pub fn is_snan(x: f64) -> bool {
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if !x.is_nan() { return false; }
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let bits = x.to_bits();
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// Highest mantissa bit (bit 51) clear ⇒ SNaN. Mantissa nonzero always true for NaN.
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(bits & (1u64 << 51)) == 0
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}
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/// Round an f64 to f32 honouring FPSCR[RN]. Uses the current hardware
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/// rounding mode when RN=0 (nearest-even, the PPC default), otherwise
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/// emulates the directed rounding via bit-manipulation.
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pub fn round_to_single(ctx: &PpcContext, v: f64) -> f64 {
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match rounding_mode(ctx) {
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RoundingMode::NearestEven => (v as f32) as f64,
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RoundingMode::TowardZero => round_single_toward_zero(v) as f64,
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RoundingMode::TowardPosInf => round_single_toward_pos_inf(v) as f64,
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RoundingMode::TowardNegInf => round_single_toward_neg_inf(v) as f64,
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}
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}
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/// Round an f64 to an i64 integer honouring FPSCR[RN]. Used by fctidx.
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pub fn round_to_i64(ctx: &PpcContext, v: f64) -> i64 {
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match rounding_mode(ctx) {
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RoundingMode::NearestEven => {
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// Round-half-to-even (banker's rounding).
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let r = v.round();
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// Rust's f64::round is round-half-away-from-zero. Correct ties to even:
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let diff = (v - v.trunc()).abs();
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if (diff - 0.5).abs() < f64::EPSILON {
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let floor = v.floor();
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if (floor as i64) & 1 == 0 { floor as i64 } else { v.ceil() as i64 }
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} else {
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r as i64
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}
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}
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RoundingMode::TowardZero => v.trunc() as i64,
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RoundingMode::TowardPosInf => v.ceil() as i64,
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RoundingMode::TowardNegInf => v.floor() as i64,
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}
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}
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/// Round an f64 to an i32 integer honouring FPSCR[RN]. Used by fctiwx.
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pub fn round_to_i32(ctx: &PpcContext, v: f64) -> i32 {
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round_to_i64(ctx, v).clamp(i32::MIN as i64, i32::MAX as i64) as i32
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}
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// ------ directed rounding helpers (f64 → f32) ------
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fn round_single_toward_zero(v: f64) -> f32 {
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// Default f64→f32 is round-to-nearest-even. Emulate truncation:
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// take the default rounded value; if the absolute rounded magnitude
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// exceeds |v|, bump down by one ULP toward zero.
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let rn = v as f32;
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if rn.is_nan() || rn.is_infinite() || rn == 0.0 { return rn; }
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if rn.abs() as f64 <= v.abs() { return rn; }
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let adj_bits = rn.to_bits();
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let lower = if rn.is_sign_positive() { adj_bits - 1 } else { adj_bits - 1 };
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f32::from_bits(lower)
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}
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fn round_single_toward_pos_inf(v: f64) -> f32 {
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let rn = v as f32;
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if rn.is_nan() || rn.is_infinite() { return rn; }
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if (rn as f64) >= v { return rn; }
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// rn < v — bump up by one ULP in the +direction.
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let b = rn.to_bits();
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let nb = if rn.is_sign_negative() { b - 1 } else { b + 1 };
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f32::from_bits(nb)
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}
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fn round_single_toward_neg_inf(v: f64) -> f32 {
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let rn = v as f32;
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if rn.is_nan() || rn.is_infinite() { return rn; }
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if (rn as f64) <= v { return rn; }
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// rn > v — bump down.
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let b = rn.to_bits();
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let nb = if rn.is_sign_negative() { b + 1 } else { b - 1 };
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f32::from_bits(nb)
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}
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/// Drop-in replacement for the old `update_cr1_from_fpscr`. Reads the
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/// currently-maintained FPSCR bits (FX, FEX, VX, OX) into CR1.
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pub fn update_cr1(ctx: &mut PpcContext) {
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ctx.cr[1].lt = (ctx.fpscr & FX) != 0;
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ctx.cr[1].gt = (ctx.fpscr & FEX) != 0;
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ctx.cr[1].eq = (ctx.fpscr & VX) != 0;
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ctx.cr[1].so = (ctx.fpscr & OX) != 0;
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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fn ctx() -> PpcContext { PpcContext::new() }
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#[test]
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fn rn_default_is_nearest() {
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assert_eq!(rounding_mode(&ctx()), RoundingMode::NearestEven);
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}
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#[test]
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fn rn_bits_decode() {
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let mut c = ctx();
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c.fpscr = 0x1;
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assert_eq!(rounding_mode(&c), RoundingMode::TowardZero);
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c.fpscr = 0x2;
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assert_eq!(rounding_mode(&c), RoundingMode::TowardPosInf);
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c.fpscr = 0x3;
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assert_eq!(rounding_mode(&c), RoundingMode::TowardNegInf);
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}
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#[test]
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fn fprf_classifies_correctly() {
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assert_eq!(classify_fprf(1.0), fprf::POS_NORMAL);
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assert_eq!(classify_fprf(-1.0), fprf::NEG_NORMAL);
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assert_eq!(classify_fprf(0.0), fprf::POS_ZERO);
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assert_eq!(classify_fprf(-0.0), fprf::NEG_ZERO);
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assert_eq!(classify_fprf(f64::INFINITY), fprf::POS_INF);
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assert_eq!(classify_fprf(f64::NEG_INFINITY), fprf::NEG_INF);
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assert_eq!(classify_fprf(f64::NAN), fprf::QNAN);
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assert_eq!(classify_fprf(f64::from_bits(1)), fprf::POS_DENORMAL);
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}
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#[test]
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fn fx_is_sticky_on_new_exception() {
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let mut c = ctx();
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set_exception(&mut c, OX);
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assert_ne!(c.fpscr & FX, 0);
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// Clear FX/OX manually.
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c.fpscr &= !(FX | OX);
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// Re-set OX; FX should re-latch.
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set_exception(&mut c, OX);
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assert_ne!(c.fpscr & FX, 0);
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}
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#[test]
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fn vx_summary_set_on_any_vx_bit() {
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let mut c = ctx();
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set_exception(&mut c, VXSNAN);
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assert_ne!(c.fpscr & VX, 0);
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assert_ne!(c.fpscr & VXSNAN, 0);
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}
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#[test]
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fn round_to_single_nearest_is_identity_on_representable() {
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let c = ctx();
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assert_eq!(round_to_single(&c, 1.0_f64), 1.0_f64);
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}
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#[test]
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fn round_to_i32_clamps_out_of_range() {
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let c = ctx();
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assert_eq!(round_to_i32(&c, 1e20_f64), i32::MAX);
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assert_eq!(round_to_i32(&c, -1e20_f64), i32::MIN);
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}
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#[test]
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fn round_to_i64_nearest_even_on_tie() {
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let c = ctx();
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assert_eq!(round_to_i64(&c, 2.5_f64), 2);
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assert_eq!(round_to_i64(&c, 3.5_f64), 4);
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assert_eq!(round_to_i64(&c, -2.5_f64), -2);
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}
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#[test]
|
||||
fn check_invalid_add_detects_inf_minus_inf() {
|
||||
let mut c = ctx();
|
||||
assert!(check_invalid_add(&mut c, f64::INFINITY, f64::INFINITY, true));
|
||||
assert_ne!(c.fpscr & VXISI, 0);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn check_invalid_div_detects_zero_over_zero() {
|
||||
let mut c = ctx();
|
||||
assert!(check_invalid_div(&mut c, 0.0, 0.0));
|
||||
assert_ne!(c.fpscr & VXZDZ, 0);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn snan_detection() {
|
||||
// SNaN in binary64: sign=0, exp=all-ones, mantissa nonzero with bit 51 clear.
|
||||
let snan = f64::from_bits(0x7FF0_0000_0000_0001);
|
||||
assert!(is_snan(snan));
|
||||
assert!(!is_snan(f64::NAN));
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user