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xenia-cpu: VMX128, FPSCR, decoder split, scheduler, decode/block caches

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Split the monolithic interpreter into cohesive modules: dedicated
decoder (decoder.rs) producing 8-byte DecodedInstr; opcode tables
(opcode.rs); explicit traps (trap.rs); FPSCR helpers (fpscr.rs);
overflow/carry helpers (overflow.rs); a 4 KiB-page-versioned decode
cache and basic-block cache (block_cache.rs); and a full VMX/VMX128
implementation (vmx.rs) covering AltiVec + Xenon's 128-bit extensions.

Add the parallel-execution substrate behind --parallel: a 7-party
phaser (phaser.rs) for round-based barrier sync, ReservationTable
(reservation.rs) for guest LL/SC, and the per-HW-thread scheduler
core (scheduler.rs) that owns ThreadRefs, runqueues, and pending IRQs.

Disassembler is now the single source of truth: disasm.rs gains the
full base + extended + VMX128 mnemonic set, with golden JSON fixtures
and a disasm_goldens test suite. Add a criterion-style interpreter
bench. context.rs grows the per-thread state the new modules need
(reservation slot, FPSCR, vector regs).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
2026-05-01 16:27:43 +02:00
parent e9b2b57a44
commit c36cca14f9
20 changed files with 12284 additions and 458 deletions
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571
crates/xenia-cpu/tests/golden/base_mnemonics.json Normal file
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{
"rows": [
{
"label": "add r3,r4,r5",
"raw": "0x7C642A14",
"addr": "0x82000000",
"mnemonic": "add",
"operands": "r3, r4, r5"
},
{
"label": "add. r3,r4,r5",
"raw": "0x7C642A15",
"addr": "0x82000000",
"mnemonic": "add.",
"operands": "r3, r4, r5"
},
{
"label": "addo r3,r4,r5",
"raw": "0x7C642E14",
"addr": "0x82000000",
"mnemonic": "addo",
"operands": "r3, r4, r5"
},
{
"label": "addo. r3,r4,r5",
"raw": "0x7C642E15",
"addr": "0x82000000",
"mnemonic": "addo.",
"operands": "r3, r4, r5"
},
{
"label": "neg r3,r4",
"raw": "0x7C6400D0",
"addr": "0x82000000",
"mnemonic": "neg",
"operands": "r3, r4"
},
{
"label": "mullw r3,r4,r5",
"raw": "0x7C6429D6",
"addr": "0x82000000",
"mnemonic": "mullw",
"operands": "r3, r4, r5"
},
{
"label": "divw r3,r4,r5",
"raw": "0x7C642BD6",
"addr": "0x82000000",
"mnemonic": "divw",
"operands": "r3, r4, r5"
},
{
"label": "mulhw. r3,r4,r5",
"raw": "0x7C642897",
"addr": "0x82000000",
"mnemonic": "mulhw.",
"operands": "r3, r4, r5"
},
{
"label": "mulhwu. r3,r4,r5",
"raw": "0x7C642817",
"addr": "0x82000000",
"mnemonic": "mulhwu.",
"operands": "r3, r4, r5"
},
{
"label": "mulld r3,r4,r5",
"raw": "0x7C6429D2",
"addr": "0x82000000",
"mnemonic": "mulld",
"operands": "r3, r4, r5"
},
{
"label": "and r3,r4,r5",
"raw": "0x7C832838",
"addr": "0x82000000",
"mnemonic": "and",
"operands": "r3, r4, r5"
},
{
"label": "or r3,r4,r5 (non-mr: rs!=rb)",
"raw": "0x7C832B78",
"addr": "0x82000000",
"mnemonic": "or",
"operands": "r3, r4, r5"
},
{
"label": "xor r3,r4,r5",
"raw": "0x7C832A78",
"addr": "0x82000000",
"mnemonic": "xor",
"operands": "r3, r4, r5"
},
{
"label": "nor r3,r4,r5",
"raw": "0x7C8328F8",
"addr": "0x82000000",
"mnemonic": "nor",
"operands": "r3, r4, r5"
},
{
"label": "nand r3,r4,r5",
"raw": "0x7C832BB8",
"addr": "0x82000000",
"mnemonic": "nand",
"operands": "r3, r4, r5"
},
{
"label": "eqv r3,r4,r5",
"raw": "0x7C832A38",
"addr": "0x82000000",
"mnemonic": "eqv",
"operands": "r3, r4, r5"
},
{
"label": "andc r3,r4,r5",
"raw": "0x7C832878",
"addr": "0x82000000",
"mnemonic": "andc",
"operands": "r3, r4, r5"
},
{
"label": "orc r3,r4,r5",
"raw": "0x7C832B38",
"addr": "0x82000000",
"mnemonic": "orc",
"operands": "r3, r4, r5"
},
{
"label": "slw r3,r4,r5",
"raw": "0x7C832830",
"addr": "0x82000000",
"mnemonic": "slw",
"operands": "r3, r4, r5"
},
{
"label": "srw r3,r4,r5",
"raw": "0x7C832C30",
"addr": "0x82000000",
"mnemonic": "srw",
"operands": "r3, r4, r5"
},
{
"label": "sraw r3,r4,r5",
"raw": "0x7C832E30",
"addr": "0x82000000",
"mnemonic": "sraw",
"operands": "r3, r4, r5"
},
{
"label": "sld r3,r4,r5",
"raw": "0x7C832836",
"addr": "0x82000000",
"mnemonic": "sld",
"operands": "r3, r4, r5"
},
{
"label": "srd r3,r4,r5",
"raw": "0x7C832C36",
"addr": "0x82000000",
"mnemonic": "srd",
"operands": "r3, r4, r5"
},
{
"label": "srawi r3,r4,16",
"raw": "0x7C838670",
"addr": "0x82000000",
"mnemonic": "srawi",
"operands": "r3, r4, 16"
},
{
"label": "stwcx. r3,r4,r5",
"raw": "0x7C64292D",
"addr": "0x82000000",
"mnemonic": "stwcx.",
"operands": "r3, r4, r5"
},
{
"label": "stdcx. r3,r4,r5",
"raw": "0x7C6429AD",
"addr": "0x82000000",
"mnemonic": "stdcx.",
"operands": "r3, r4, r5"
},
{
"label": "lwarx r3,r4,r5",
"raw": "0x7C642828",
"addr": "0x82000000",
"mnemonic": "lwarx",
"operands": "r3, r4, r5"
},
{
"label": "ldarx r3,r4,r5",
"raw": "0x7C6428A8",
"addr": "0x82000000",
"mnemonic": "ldarx",
"operands": "r3, r4, r5"
},
{
"label": "cmpwi cr0, r3, 16",
"raw": "0x2C030010",
"addr": "0x82000000",
"mnemonic": "cmpi",
"operands": "0, r3, 16",
"ext_mnemonic": "cmpwi",
"ext_operands": "r3, 16"
},
{
"label": "cmpwi cr2, r3, 16",
"raw": "0x2D030010",
"addr": "0x82000000",
"mnemonic": "cmpi",
"operands": "cr2, 0, r3, 16",
"ext_mnemonic": "cmpwi",
"ext_operands": "cr2, r3, 16"
},
{
"label": "cmplwi cr0, r3, 16",
"raw": "0x28030010",
"addr": "0x82000000",
"mnemonic": "cmpli",
"operands": "0, r3, 0x10",
"ext_mnemonic": "cmplwi",
"ext_operands": "r3, 0x10"
},
{
"label": "cmpw r3,r4 in cr0",
"raw": "0x7C032000",
"addr": "0x82000000",
"mnemonic": "cmp",
"operands": "0, r3, r4",
"ext_mnemonic": "cmpw",
"ext_operands": "r3, r4"
},
{
"label": "cmpd r3,r4",
"raw": "0x7C232000",
"addr": "0x82000000",
"mnemonic": "cmp",
"operands": "1, r3, r4",
"ext_mnemonic": "cmpd",
"ext_operands": "r3, r4"
},
{
"label": "cmplw r3,r4",
"raw": "0x7C032040",
"addr": "0x82000000",
"mnemonic": "cmpl",
"operands": "0, r3, r4",
"ext_mnemonic": "cmplw",
"ext_operands": "r3, r4"
},
{
"label": "addi r3, r1, 16",
"raw": "0x38610010",
"addr": "0x82000000",
"mnemonic": "addi",
"operands": "r3, r1, 16"
},
{
"label": "addis r3, r1, 0x100 (ra!=0)",
"raw": "0x3C610100",
"addr": "0x82000000",
"mnemonic": "addis",
"operands": "r3, r1, 0x100"
},
{
"label": "mulli r3, r4, 5",
"raw": "0x1C640005",
"addr": "0x82000000",
"mnemonic": "mulli",
"operands": "r3, r4, 5"
},
{
"label": "subfic r3, r4, 5",
"raw": "0x20640005",
"addr": "0x82000000",
"mnemonic": "subfic",
"operands": "r3, r4, 5"
},
{
"label": "addic r3, r4, 16",
"raw": "0x30640010",
"addr": "0x82000000",
"mnemonic": "addic",
"operands": "r3, r4, 16"
},
{
"label": "addic. r3, r4, 16",
"raw": "0x34640010",
"addr": "0x82000000",
"mnemonic": "addic.",
"operands": "r3, r4, 16"
},
{
"label": "ori r4, r3, 0x10 (non-nop)",
"raw": "0x60640010",
"addr": "0x82000000",
"mnemonic": "ori",
"operands": "r4, r3, 0x10"
},
{
"label": "oris r4, r3, 0x10",
"raw": "0x64640010",
"addr": "0x82000000",
"mnemonic": "oris",
"operands": "r4, r3, 0x10"
},
{
"label": "xori r4, r3, 0x10",
"raw": "0x68640010",
"addr": "0x82000000",
"mnemonic": "xori",
"operands": "r4, r3, 0x10"
},
{
"label": "andi. r4, r3, 0x10",
"raw": "0x70640010",
"addr": "0x82000000",
"mnemonic": "andi.",
"operands": "r4, r3, 0x10"
},
{
"label": "lwz r5, 0x20(r1)",
"raw": "0x80A10020",
"addr": "0x82000000",
"mnemonic": "lwz",
"operands": "r5, 32(r1)"
},
{
"label": "stw r5, 0x20(r1)",
"raw": "0x90A10020",
"addr": "0x82000000",
"mnemonic": "stw",
"operands": "r5, 32(r1)"
},
{
"label": "lbz r5, 0x20(r1)",
"raw": "0x88A10020",
"addr": "0x82000000",
"mnemonic": "lbz",
"operands": "r5, 32(r1)"
},
{
"label": "lhz r5, 0x20(r1)",
"raw": "0xA0A10020",
"addr": "0x82000000",
"mnemonic": "lhz",
"operands": "r5, 32(r1)"
},
{
"label": "lfs f5, 0x20(r1)",
"raw": "0xC0A10020",
"addr": "0x82000000",
"mnemonic": "lfs",
"operands": "f5, 32(r1)"
},
{
"label": "lfd f5, 0x20(r1)",
"raw": "0xC8A10020",
"addr": "0x82000000",
"mnemonic": "lfd",
"operands": "f5, 32(r1)"
},
{
"label": "stfd f5, 0x20(r1)",
"raw": "0xD8A10020",
"addr": "0x82000000",
"mnemonic": "stfd",
"operands": "f5, 32(r1)"
},
{
"label": "ld r5, 0x20(r1)",
"raw": "0xE8A10020",
"addr": "0x82000000",
"mnemonic": "ld",
"operands": "r5, 32(r1)"
},
{
"label": "std r5, 0x20(r1)",
"raw": "0xF8A10020",
"addr": "0x82000000",
"mnemonic": "std",
"operands": "r5, 32(r1)"
},
{
"label": "sync 0 (extends to sync)",
"raw": "0x7C0004AC",
"addr": "0x82000000",
"mnemonic": "sync",
"operands": ""
},
{
"label": "isync",
"raw": "0x4C00012C",
"addr": "0x82000000",
"mnemonic": "isync",
"operands": ""
},
{
"label": "eieio",
"raw": "0x7C0006AC",
"addr": "0x82000000",
"mnemonic": "eieio",
"operands": ""
},
{
"label": "dcbst r1, r2",
"raw": "0x7C01106C",
"addr": "0x82000000",
"mnemonic": "dcbst",
"operands": "r1, r2"
},
{
"label": "dcbf r1, r2",
"raw": "0x7C0110AC",
"addr": "0x82000000",
"mnemonic": "dcbf",
"operands": "r1, r2"
},
{
"label": "dcbt r1, r2",
"raw": "0x7C01122C",
"addr": "0x82000000",
"mnemonic": "dcbt",
"operands": "r1, r2"
},
{
"label": "dcbz r1, r2",
"raw": "0x7C0117EC",
"addr": "0x82000000",
"mnemonic": "dcbz",
"operands": "r1, r2"
},
{
"label": "dcbz128 r1, r2",
"raw": "0x7C2117EC",
"addr": "0x82000000",
"mnemonic": "dcbz128",
"operands": "r1, r2"
},
{
"label": "crnor 4,5,6 (no simplify)",
"raw": "0x4C853042",
"addr": "0x82000000",
"mnemonic": "crnor",
"operands": "4*cr1+lt, 4*cr1+gt, 4*cr1+eq"
},
{
"label": "crand 4,5,6",
"raw": "0x4C853202",
"addr": "0x82000000",
"mnemonic": "crand",
"operands": "4*cr1+lt, 4*cr1+gt, 4*cr1+eq"
},
{
"label": "cror 4,5,6 (no simplify)",
"raw": "0x4C853382",
"addr": "0x82000000",
"mnemonic": "cror",
"operands": "4*cr1+lt, 4*cr1+gt, 4*cr1+eq"
},
{
"label": "tw 11, r3, r4 (uncommon TO)",
"raw": "0x7D632008",
"addr": "0x82000000",
"mnemonic": "tw",
"operands": "11, r3, r4"
},
{
"label": "tdi 11, r3, 123",
"raw": "0x0963007B",
"addr": "0x82000000",
"mnemonic": "tdi",
"operands": "11, r3, 123"
},
{
"label": "mtcrf 0xFF, r5 → mtcr",
"raw": "0x7CAFF120",
"addr": "0x82000000",
"mnemonic": "mtcrf",
"operands": "0xFF, r5",
"ext_mnemonic": "mtcr",
"ext_operands": "r5"
},
{
"label": "mfcr r5",
"raw": "0x7CA00026",
"addr": "0x82000000",
"mnemonic": "mfcr",
"operands": "r5"
},
{
"label": "mfmsr r5",
"raw": "0x7CA000A6",
"addr": "0x82000000",
"mnemonic": "mfmsr",
"operands": "r5"
},
{
"label": "mtmsr r5",
"raw": "0x7CA00124",
"addr": "0x82000000",
"mnemonic": "mtmsr",
"operands": "r5"
},
{
"label": "mtmsrd r5",
"raw": "0x7CA00164",
"addr": "0x82000000",
"mnemonic": "mtmsrd",
"operands": "r5"
},
{
"label": "fadd f3, f4, f5",
"raw": "0xFC64282A",
"addr": "0x82000000",
"mnemonic": "fadd",
"operands": "f3, f4, f5"
},
{
"label": "fsub f3, f4, f5",
"raw": "0xFC642828",
"addr": "0x82000000",
"mnemonic": "fsub",
"operands": "f3, f4, f5"
},
{
"label": "fdiv f3, f4, f5",
"raw": "0xFC642824",
"addr": "0x82000000",
"mnemonic": "fdiv",
"operands": "f3, f4, f5"
},
{
"label": "fmul f3, f0, f5 (encoded)",
"raw": "0xFCE02832",
"addr": "0x82000000",
"mnemonic": "fmul",
"operands": "f7, f0, f0"
},
{
"label": "fneg f3, f4",
"raw": "0xFC640050",
"addr": "0x82000000",
"mnemonic": "fneg",
"operands": "f3, f0"
},
{
"label": "fmr f3, f4",
"raw": "0xFC640090",
"addr": "0x82000000",
"mnemonic": "fmr",
"operands": "f3, f0"
},
{
"label": "mtfsf 0xFF, f5 (Rc=0)",
"raw": "0xFDFE2D8E",
"addr": "0x82000000",
"mnemonic": "mtfsf",
"operands": "0xFF, f5"
},
{
"label": "mtfsf. 0xFF, f5 (Rc=1)",
"raw": "0xFDFE2D8F",
"addr": "0x82000000",
"mnemonic": "mtfsf.",
"operands": "0xFF, f5"
}
]
}