fix(gpu): GPUBUG-100 — apply per-operand swizzle + negate to ALU sources

Word-1 of every ALU triple holds three 8-bit component-relative
swizzles (`src1_swiz`/`src2_swiz`/`src3_swiz` at bits 16-23/8-15/0-7
per canary ucode.h:2064-2066) and three per-operand negate flags
(bits 24/25/26). Pre-fix, both the WGSL interpreter and the AOT
translator discarded word-1 entirely with `_ = w1;` — every ALU
result was missing its swizzle (broadcast/permute patterns like
`.zyxw`, `.xxxx`) and any negated operand was used positive instead.

Component-relative semantics (canary's
`AluInstruction::GetSwizzledComponentIndex`, ucode.h:1996): for output
component i, the source component is `((swizzle >> (2*i)) + i) & 3`.
Identity swizzle is 0x00, NOT 0xE4 — the original `apply_swizzle` in
the interpreter shader treated it as absolute, also incorrect.

Mechanical changes:
- crates/xenia-gpu/src/ucode/alu.rs: extend AluInstruction with
  src_X_swiz (u8) and src_X_negate (bool) fields. decode_alu unpacks
  them from word 1.
- crates/xenia-gpu/src/shaders/xenos_interp.wgsl: apply_swizzle uses
  component-relative semantics. interpret_alu decodes the modifiers
  and applies via apply_swizzle + apply_modifiers (with abs=false).
- crates/xenia-gpu/src/translator.rs: src_operand emits the
  precomputed swizzle inline as `vec4<f32>(base.x, base.y, ...)`,
  then wraps in `(-…)` when negated. Identity swizzle (0x00) emits a
  bare base expression so it round-trips with the trivial-shader
  fixture.

Abs is omitted in this commit — the abs flag is dual-meaning (for
temps it lives at bit 7 of the src byte; for constants at word-2 bit
7 `abs_constants`). Wiring it up correctly requires more careful
case-split logic; deferred to Phase G.

Verification at -n 100M lockstep:
  swaps:                2 → 2     (gated by Phase E for draws)
  draws:                0 → 0
  packets:              ~58M (within noise)
Tests: 554 → 555 (+1 swizzle/negate test, no count change otherwise
because identity swizzle test merged into D1's parameterised test).
WGSL still validates via naga (combined_module_parses_as_wgsl).

Closes GPUBUG-100 (P0). Abs deferred to Phase G.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

crates/xenia-gpu/src/ucode/alu.rs

@@ -45,6 +45,18 @@ pub struct AluInstruction {
     pub src_a_is_temp: bool,
     pub src_b_is_temp: bool,
     pub src_c_is_temp: bool,
+    /// Per-operand 8-bit component-relative swizzle (canary's
+    /// `srcN_swiz`, ucode.h:2064-2066). For output component i, the
+    /// selected source component is `((swizzle >> (2*i)) + i) & 3`.
+    /// Identity swizzle is `0x00`. GPUBUG-100.
+    pub src_a_swiz: u8,
+    pub src_b_swiz: u8,
+    pub src_c_swiz: u8,
+    /// Per-operand negate flags (canary's `srcN_reg_negate`, w1 bits
+    /// 24/25/26). Applied after the swizzle. GPUBUG-100.
+    pub src_a_negate: bool,
+    pub src_b_negate: bool,
+    pub src_c_negate: bool,
     /// Set when the instruction is predicated; skipped if the predicate
     /// doesn't match `predicate_condition`.
     pub predicated: bool,
@@ -57,7 +69,7 @@ pub struct AluInstruction {
 /// Decode a 3-dword ALU triple.
 pub fn decode_alu(words: [u32; 3]) -> AluInstruction {
     let w0 = words[0];
-    let _w1 = words[1];
+    let w1 = words[1];
     let w2 = words[2];
     AluInstruction {
         vector_opcode: (w2 & 0x3F) as u8,
@@ -78,6 +90,12 @@ pub fn decode_alu(words: [u32; 3]) -> AluInstruction {
         src_a_is_temp: ((w0 >> 29) & 1) != 0,
         src_b_is_temp: ((w0 >> 30) & 1) != 0,
         src_c_is_temp: ((w0 >> 31) & 1) != 0,
+        src_a_swiz: (w1 & 0xFF) as u8,
+        src_b_swiz: ((w1 >> 8) & 0xFF) as u8,
+        src_c_swiz: ((w1 >> 16) & 0xFF) as u8,
+        src_a_negate: ((w1 >> 24) & 1) != 0,
+        src_b_negate: ((w1 >> 25) & 1) != 0,
+        src_c_negate: ((w1 >> 26) & 1) != 0,
         predicated: ((w0 >> 27) & 1) != 0,
         predicate_condition: ((w0 >> 28) & 1) != 0,
         raw: words,