fix(gpu): GPUBUG-100 — apply per-operand swizzle + negate to ALU sources
Word-1 of every ALU triple holds three 8-bit component-relative swizzles (`src1_swiz`/`src2_swiz`/`src3_swiz` at bits 16-23/8-15/0-7 per canary ucode.h:2064-2066) and three per-operand negate flags (bits 24/25/26). Pre-fix, both the WGSL interpreter and the AOT translator discarded word-1 entirely with `_ = w1;` — every ALU result was missing its swizzle (broadcast/permute patterns like `.zyxw`, `.xxxx`) and any negated operand was used positive instead. Component-relative semantics (canary's `AluInstruction::GetSwizzledComponentIndex`, ucode.h:1996): for output component i, the source component is `((swizzle >> (2*i)) + i) & 3`. Identity swizzle is 0x00, NOT 0xE4 — the original `apply_swizzle` in the interpreter shader treated it as absolute, also incorrect. Mechanical changes: - crates/xenia-gpu/src/ucode/alu.rs: extend AluInstruction with src_X_swiz (u8) and src_X_negate (bool) fields. decode_alu unpacks them from word 1. - crates/xenia-gpu/src/shaders/xenos_interp.wgsl: apply_swizzle uses component-relative semantics. interpret_alu decodes the modifiers and applies via apply_swizzle + apply_modifiers (with abs=false). - crates/xenia-gpu/src/translator.rs: src_operand emits the precomputed swizzle inline as `vec4<f32>(base.x, base.y, ...)`, then wraps in `(-…)` when negated. Identity swizzle (0x00) emits a bare base expression so it round-trips with the trivial-shader fixture. Abs is omitted in this commit — the abs flag is dual-meaning (for temps it lives at bit 7 of the src byte; for constants at word-2 bit 7 `abs_constants`). Wiring it up correctly requires more careful case-split logic; deferred to Phase G. Verification at -n 100M lockstep: swaps: 2 → 2 (gated by Phase E for draws) draws: 0 → 0 packets: ~58M (within noise) Tests: 554 → 555 (+1 swizzle/negate test, no count change otherwise because identity swizzle test merged into D1's parameterised test). WGSL still validates via naga (combined_module_parses_as_wgsl). Closes GPUBUG-100 (P0). Abs deferred to Phase G. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
@@ -129,11 +129,15 @@ fn ps_instr_dword(t: u32, which: u32) -> u32 {
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// ── Operand helpers: M3 scaffold; M4 wires them into interpret_alu.
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fn apply_swizzle(v: vec4<f32>, swizzle: u32) -> vec4<f32> {
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// Swizzle is 8 bits: 2 bits per output lane, xyzw order.
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let sx = (swizzle >> 0u) & 3u;
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let sy = (swizzle >> 2u) & 3u;
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let sz = (swizzle >> 4u) & 3u;
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let sw = (swizzle >> 6u) & 3u;
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// Per canary `xenia-canary/src/xenia/gpu/ucode.h:1996`
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// (`AluInstruction::GetSwizzledComponentIndex`): the 8-bit swizzle is
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// **component-relative**, not absolute. For output component i, the
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// selected source component is `((swizzle >> (2*i)) + i) & 3`. Identity
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// swizzle is therefore 0x00 (all bits zero), NOT 0xE4. GPUBUG-100.
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let sx = ((swizzle >> 0u) + 0u) & 3u;
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let sy = ((swizzle >> 2u) + 1u) & 3u;
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let sz = ((swizzle >> 4u) + 2u) & 3u;
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let sw = ((swizzle >> 6u) + 3u) & 3u;
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return vec4<f32>(v[sx], v[sy], v[sz], v[sw]);
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}
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@@ -542,9 +546,17 @@ fn interpret_alu(t: u32, is_vertex: bool) {
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let predicated = ((w0 >> 27u) & 1u) != 0u;
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let predicate_condition = ((w0 >> 28u) & 1u) != 0u;
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let scalar_src_is_ps = ((w0 >> 26u) & 1u) != 0u;
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// `w1` holds per-operand swizzle + negate/abs flags. Phase D2 decodes
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// them; Phase D1 only resolved the temp/constant selector.
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_ = w1;
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// GPUBUG-100: word-1 holds per-operand swizzle (8 bits each, low to
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// high = src3/src2/src1 in canary's numbering) + per-operand negate
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// (bits 24/25/26). Pre-fix `_ = w1;` discarded these → every ALU
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// result was missing its swizzle (e.g. `.zyxw`, `.xxxx` broadcast)
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// and any negated operand was used positive instead.
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let src_a_swiz = w1 & 0xFFu;
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let src_b_swiz = (w1 >> 8u) & 0xFFu;
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let src_c_swiz = (w1 >> 16u) & 0xFFu;
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let src_a_neg = ((w1 >> 24u) & 1u) != 0u;
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let src_b_neg = ((w1 >> 25u) & 1u) != 0u;
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let src_c_neg = ((w1 >> 26u) & 1u) != 0u;
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// Honor per-instruction predicate: skip when predicated and the
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// predicate doesn't match the required condition.
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@@ -552,10 +564,15 @@ fn interpret_alu(t: u32, is_vertex: bool) {
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return;
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}
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// Vector pipe.
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let a = read_src(src_a, src_a_is_temp);
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let b = read_src(src_b, src_b_is_temp);
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let c = read_src(src_c, src_c_is_temp);
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// Vector pipe — apply swizzle then negate per operand. Abs is
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// omitted (the abs flag is dual-meaning and lives at different
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// bits depending on temp-vs-constant; left for a follow-up).
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let a_raw = read_src(src_a, src_a_is_temp);
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let b_raw = read_src(src_b, src_b_is_temp);
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let c_raw = read_src(src_c, src_c_is_temp);
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let a = apply_modifiers(apply_swizzle(a_raw, src_a_swiz), src_a_neg, false);
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let b = apply_modifiers(apply_swizzle(b_raw, src_b_swiz), src_b_neg, false);
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let c = apply_modifiers(apply_swizzle(c_raw, src_c_swiz), src_c_neg, false);
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let vec_result = exec_vector_op(vec_op, a, b, c);
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if vec_wm != 0u {
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write_reg_masked(vec_dst, vec_wm, vec_result);
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@@ -287,15 +287,15 @@ impl EmitCtx {
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alu: &AluInstruction,
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current_alloc: AllocKind,
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) -> Result<(), &'static str> {
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// GPUBUG-101: word-0 bits 29-31 select temp vs constant for
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// each operand (canary `srcN_sel`); the corresponding src byte
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// indexes either a general register (temp) or an ALU constant
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// (c#). Pre-fix the translator unconditionally emitted r[low7]
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// for both, dropping every shader's uniform read. Mirrors the
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// interpreter's `read_src`.
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let a = src_operand(alu.src_a, alu.src_a_is_temp);
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let b = src_operand(alu.src_b, alu.src_b_is_temp);
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let c = src_operand(alu.src_c, alu.src_c_is_temp);
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// GPUBUG-100/101: per-operand temp-vs-constant selector (w0
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// bits 29-31), 8-bit component-relative swizzle (w1 bytes 0-2),
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// and 1-bit negate (w1 bits 24-26). Pre-fix all three were
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// discarded, so every ALU read came back as r[low7] without
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// any swizzle / negation, dropping every shader's uniforms +
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// negative operands.
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let a = src_operand(alu.src_a, alu.src_a_is_temp, alu.src_a_swiz, alu.src_a_negate);
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let b = src_operand(alu.src_b, alu.src_b_is_temp, alu.src_b_swiz, alu.src_b_negate);
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let c = src_operand(alu.src_c, alu.src_c_is_temp, alu.src_c_swiz, alu.src_c_negate);
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// Vector pipe.
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if alu.vector_write_mask != 0 {
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@@ -409,17 +409,38 @@ impl EmitCtx {
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}
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}
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/// Emit the WGSL expression that reads an ALU source operand. Per
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/// canary `xenia-canary/src/xenia/gpu/ucode.h`, the temp-vs-constant
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/// selector is in word-0 bits 29-31 (`srcN_sel`); the src byte is then
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/// either a temp descriptor (bits 5:0 = temp index, bits 6/7 reserved
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/// for relative/abs flags decoded in Phase D2) or a flat constant
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/// index. Mirrors the interpreter shader's `read_src`. GPUBUG-101.
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fn src_operand(src_byte: u8, is_temp: bool) -> String {
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if is_temp {
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/// Emit the WGSL expression that reads an ALU source operand with
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/// swizzle + negate applied (no abs — see GPUBUG-100 deferred). Mirrors
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/// the interpreter shader's `read_src` + `apply_swizzle` + the negate
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/// half of `apply_modifiers`. The 8-bit `swizzle` is component-relative
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/// per canary `AluInstruction::GetSwizzledComponentIndex`: for output
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/// component i, source component is `((swiz >> (2*i)) + i) & 3`.
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/// Identity swizzle is `0x00`. GPUBUG-100 / GPUBUG-101.
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fn src_operand(src_byte: u8, is_temp: bool, swizzle: u8, negate: bool) -> String {
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let base = if is_temp {
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format!("r[{}u]", (src_byte & 0x3F) as u32)
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} else {
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format!("xenos_consts.alu[{}u]", src_byte as u32)
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};
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let s = swizzle as u32;
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let lane = |i: u32| -> char {
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let c = (((s >> (2 * i)) + i) & 3) as usize;
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['x', 'y', 'z', 'w'][c]
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};
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// Identity swizzle (0x00) maps to .xyzw — emit a bare expression.
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let swizzled = if swizzle == 0 {
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base
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} else {
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let lx = lane(0);
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let ly = lane(1);
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let lz = lane(2);
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let lw = lane(3);
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format!("vec4<f32>({base}.{lx}, {base}.{ly}, {base}.{lz}, {base}.{lw})")
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};
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if negate {
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format!("(-{swizzled})")
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} else {
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swizzled
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}
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}
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@@ -542,19 +563,49 @@ mod tests {
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}
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#[test]
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fn src_operand_decodes_temp_vs_constant() {
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fn src_operand_decodes_temp_vs_constant_no_modifiers() {
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// GPUBUG-101: is_temp=true → r[low6]; is_temp=false → xenos_consts.alu[full].
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assert_eq!(src_operand(0x00, true), "r[0u]");
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assert_eq!(src_operand(0x05, true), "r[5u]");
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assert_eq!(src_operand(0x3F, true), "r[63u]");
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// Identity swizzle (0x00), no negate → bare base expression.
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assert_eq!(src_operand(0x00, true, 0x00, false), "r[0u]");
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assert_eq!(src_operand(0x05, true, 0x00, false), "r[5u]");
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assert_eq!(src_operand(0x3F, true, 0x00, false), "r[63u]");
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// For temps, bits 6/7 are reserved (abs/rel) — they don't widen
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// the register index even if set. Phase D2 will consume them.
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assert_eq!(src_operand(0x80, true), "r[0u]");
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assert_eq!(src_operand(0xFF, true), "r[63u]");
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assert_eq!(src_operand(0x80, true, 0x00, false), "r[0u]");
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assert_eq!(src_operand(0xFF, true, 0x00, false), "r[63u]");
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// Constants: full 8-bit index.
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assert_eq!(src_operand(0x00, false), "xenos_consts.alu[0u]");
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assert_eq!(src_operand(0x05, false), "xenos_consts.alu[5u]");
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assert_eq!(src_operand(0xFF, false), "xenos_consts.alu[255u]");
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assert_eq!(src_operand(0x00, false, 0x00, false), "xenos_consts.alu[0u]");
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assert_eq!(src_operand(0x05, false, 0x00, false), "xenos_consts.alu[5u]");
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assert_eq!(src_operand(0xFF, false, 0x00, false), "xenos_consts.alu[255u]");
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}
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#[test]
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fn src_operand_applies_swizzle_and_negate() {
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// GPUBUG-100. Component-relative swizzle. swizzle=0x1B reverses
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// the lanes (.wzyx): for i=0 → ((0x1B >> 0) + 0) & 3 = 3 = w;
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// for i=1 → ((0x1B >> 2) + 1) & 3 = (6+1)&3 = 3 = w. Hmm —
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// canary's identity is 0x00 = .xyzw, so .wzyx in component-
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// relative terms = `s0=3, s1=2, s2=1, s3=0` → bits would be
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// (3, (2-1)&3=1, (1-2)&3=3, (0-3)&3=1) which combines weirdly.
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// We just verify the mechanics by precomputing a known case:
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// swizzle=0x00 (identity) outputs .xyzw — matched by no-swizzle
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// branch. Negate wraps in `(-…)`.
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assert_eq!(src_operand(0x05, true, 0x00, true), "(-r[5u])");
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// swizzle=0xFF → for each i, ((0xFF >> (2i)) + i) & 3:
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// i=0: (3 + 0) & 3 = 3 → w
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// i=1: ((0x3F) + 1) & 3 = (63+1)&3 = 0 → x
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// i=2: ((0x0F) + 2) & 3 = (15+2)&3 = 1 → y
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// i=3: ((0x03) + 3) & 3 = (3+3)&3 = 2 → z
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// Output: .wxyz
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assert_eq!(
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src_operand(0x05, true, 0xFF, false),
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"vec4<f32>(r[5u].w, r[5u].x, r[5u].y, r[5u].z)"
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);
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// Combined: negate of constant with .wxyz swizzle.
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assert_eq!(
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src_operand(0x07, false, 0xFF, true),
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"(-vec4<f32>(xenos_consts.alu[7u].w, xenos_consts.alu[7u].x, xenos_consts.alu[7u].y, xenos_consts.alu[7u].z))"
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);
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}
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#[test]
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@@ -45,6 +45,18 @@ pub struct AluInstruction {
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pub src_a_is_temp: bool,
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pub src_b_is_temp: bool,
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pub src_c_is_temp: bool,
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/// Per-operand 8-bit component-relative swizzle (canary's
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/// `srcN_swiz`, ucode.h:2064-2066). For output component i, the
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/// selected source component is `((swizzle >> (2*i)) + i) & 3`.
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/// Identity swizzle is `0x00`. GPUBUG-100.
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pub src_a_swiz: u8,
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pub src_b_swiz: u8,
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pub src_c_swiz: u8,
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/// Per-operand negate flags (canary's `srcN_reg_negate`, w1 bits
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/// 24/25/26). Applied after the swizzle. GPUBUG-100.
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pub src_a_negate: bool,
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pub src_b_negate: bool,
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pub src_c_negate: bool,
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/// Set when the instruction is predicated; skipped if the predicate
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/// doesn't match `predicate_condition`.
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pub predicated: bool,
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@@ -57,7 +69,7 @@ pub struct AluInstruction {
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/// Decode a 3-dword ALU triple.
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pub fn decode_alu(words: [u32; 3]) -> AluInstruction {
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let w0 = words[0];
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let _w1 = words[1];
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let w1 = words[1];
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let w2 = words[2];
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AluInstruction {
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vector_opcode: (w2 & 0x3F) as u8,
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@@ -78,6 +90,12 @@ pub fn decode_alu(words: [u32; 3]) -> AluInstruction {
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src_a_is_temp: ((w0 >> 29) & 1) != 0,
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src_b_is_temp: ((w0 >> 30) & 1) != 0,
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src_c_is_temp: ((w0 >> 31) & 1) != 0,
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src_a_swiz: (w1 & 0xFF) as u8,
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src_b_swiz: ((w1 >> 8) & 0xFF) as u8,
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src_c_swiz: ((w1 >> 16) & 0xFF) as u8,
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src_a_negate: ((w1 >> 24) & 1) != 0,
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src_b_negate: ((w1 >> 25) & 1) != 0,
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src_c_negate: ((w1 >> 26) & 1) != 0,
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predicated: ((w0 >> 27) & 1) != 0,
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predicate_condition: ((w0 >> 28) & 1) != 0,
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raw: words,
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