Initial commit: xenia-rs workspace for Xbox 360 RE
Rust reimplementation of the xenia Xbox 360 emulator targeting reverse- engineering and preservation, initially scoped to Project Sylpheed. Includes: - XEX2 loader (LZX decompression, AES decryption, PE parsing) - XISO / XGD2 disc image VFS - PPC interpreter with 200+ opcodes and VMX128 decoding - Static analyzer: functions, cross-references, labels, asm + SQLite output - HLE kernel covering the xboxkrnl/xam subset used by Sylpheed init - Debugger with in-memory and SQLite-backed execution tracing - `xenia-rs` CLI with extract/dis/exec commands that produce cumulative, superset SQLite databases and opt-in instruction/import/branch traces Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
This commit is contained in:
MechaCat02
276
crates/xenia-cpu/src/disasm.rs
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276
crates/xenia-cpu/src/disasm.rs
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use crate::decoder::DecodedInstr;
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use crate::opcode::PpcOpcode;
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use std::fmt::Write;
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/// Disassemble a decoded instruction into PPC assembly text.
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pub fn disassemble(instr: &DecodedInstr) -> String {
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let mut out = String::new();
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match instr.opcode {
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// Branch instructions
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PpcOpcode::bx => {
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let target = if instr.aa() {
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instr.li() as u32
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} else {
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instr.addr.wrapping_add(instr.li() as u32)
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};
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let mnemonic = if instr.lk() { "bl" } else { "b" };
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write!(out, "{} 0x{:08X}", mnemonic, target).unwrap();
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}
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PpcOpcode::bcx => {
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let bo = instr.bo();
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let bi = instr.bi();
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let target = if instr.aa() {
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instr.bd() as u32
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} else {
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instr.addr.wrapping_add(instr.bd() as u32)
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};
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let mnemonic = if instr.lk() { "bcl" } else { "bc" };
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write!(out, "{} {},{},0x{:08X}", mnemonic, bo, bi, target).unwrap();
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}
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PpcOpcode::bclrx => {
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let mnemonic = if instr.lk() { "bclrl" } else { "bclr" };
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write!(out, "{} {},{}", mnemonic, instr.bo(), instr.bi()).unwrap();
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}
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PpcOpcode::bcctrx => {
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let mnemonic = if instr.lk() { "bcctrl" } else { "bcctr" };
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write!(out, "{} {},{}", mnemonic, instr.bo(), instr.bi()).unwrap();
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}
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// System call
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PpcOpcode::sc => {
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write!(out, "sc").unwrap();
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}
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// D-form load/store
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PpcOpcode::lwz | PpcOpcode::lwzu | PpcOpcode::lbz | PpcOpcode::lbzu |
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PpcOpcode::lhz | PpcOpcode::lhzu | PpcOpcode::lha | PpcOpcode::lhau |
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PpcOpcode::lfs | PpcOpcode::lfsu | PpcOpcode::lfd | PpcOpcode::lfdu => {
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write!(out, "{:?} r{},{}(r{})", instr.opcode, instr.rd(), instr.d(), instr.ra()).unwrap();
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}
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PpcOpcode::stw | PpcOpcode::stwu | PpcOpcode::stb | PpcOpcode::stbu |
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PpcOpcode::sth | PpcOpcode::sthu |
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PpcOpcode::stfs | PpcOpcode::stfsu | PpcOpcode::stfd | PpcOpcode::stfdu => {
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write!(out, "{:?} r{},{}(r{})", instr.opcode, instr.rs(), instr.d(), instr.ra()).unwrap();
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}
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// D-form immediate ALU
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PpcOpcode::addi | PpcOpcode::addis | PpcOpcode::addic | PpcOpcode::addicx |
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PpcOpcode::subficx | PpcOpcode::mulli => {
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write!(out, "{:?} r{},r{},{}", instr.opcode, instr.rd(), instr.ra(), instr.simm16()).unwrap();
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}
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// D-form immediate logical
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PpcOpcode::ori | PpcOpcode::oris | PpcOpcode::xori | PpcOpcode::xoris |
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PpcOpcode::andix | PpcOpcode::andisx => {
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write!(out, "{:?} r{},r{},0x{:04X}", instr.opcode, instr.ra(), instr.rs(), instr.uimm16()).unwrap();
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}
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// Compare
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PpcOpcode::cmpi => {
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write!(out, "cmp{}i cr{},r{},{}", if instr.l() { "d" } else { "w" },
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instr.crfd(), instr.ra(), instr.simm16()).unwrap();
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}
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PpcOpcode::cmpli => {
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write!(out, "cmpl{}i cr{},r{},0x{:04X}", if instr.l() { "d" } else { "w" },
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instr.crfd(), instr.ra(), instr.uimm16()).unwrap();
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}
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PpcOpcode::cmp => {
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write!(out, "cmp{} cr{},r{},r{}", if instr.l() { "d" } else { "w" },
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instr.crfd(), instr.ra(), instr.rb()).unwrap();
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}
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PpcOpcode::cmpl => {
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write!(out, "cmpl{} cr{},r{},r{}", if instr.l() { "d" } else { "w" },
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instr.crfd(), instr.ra(), instr.rb()).unwrap();
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}
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// X-form ALU (3-register)
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PpcOpcode::addx | PpcOpcode::addcx | PpcOpcode::addex | PpcOpcode::addzex |
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PpcOpcode::addmex | PpcOpcode::subfx | PpcOpcode::subfcx | PpcOpcode::subfex |
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PpcOpcode::subfzex | PpcOpcode::subfmex | PpcOpcode::negx |
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PpcOpcode::mullwx | PpcOpcode::mulhwx | PpcOpcode::mulhwux |
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PpcOpcode::divwx | PpcOpcode::divwux |
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PpcOpcode::mulldx | PpcOpcode::mulhdx | PpcOpcode::mulhdux |
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PpcOpcode::divdx | PpcOpcode::divdux => {
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write!(out, "{:?} r{},r{},r{}", instr.opcode, instr.rd(), instr.ra(), instr.rb()).unwrap();
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}
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// X-form logical
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PpcOpcode::andx | PpcOpcode::andcx | PpcOpcode::orx | PpcOpcode::orcx |
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PpcOpcode::xorx | PpcOpcode::norx | PpcOpcode::nandx | PpcOpcode::eqvx => {
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write!(out, "{:?} r{},r{},r{}", instr.opcode, instr.ra(), instr.rs(), instr.rb()).unwrap();
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}
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// Shift/rotate
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PpcOpcode::slwx | PpcOpcode::srwx | PpcOpcode::srawx | PpcOpcode::sldx |
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PpcOpcode::srdx | PpcOpcode::sradx => {
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write!(out, "{:?} r{},r{},r{}", instr.opcode, instr.ra(), instr.rs(), instr.rb()).unwrap();
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}
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PpcOpcode::srawix => {
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write!(out, "srawi r{},r{},{}", instr.ra(), instr.rs(), instr.sh()).unwrap();
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}
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PpcOpcode::sradix => {
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write!(out, "sradi r{},r{},{}", instr.ra(), instr.rs(), instr.sh64()).unwrap();
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}
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// Rotate
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PpcOpcode::rlwinmx => {
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write!(out, "rlwinm r{},r{},{},{},{}", instr.ra(), instr.rs(), instr.sh(), instr.mb(), instr.me()).unwrap();
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}
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PpcOpcode::rlwimix => {
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write!(out, "rlwimi r{},r{},{},{},{}", instr.ra(), instr.rs(), instr.sh(), instr.mb(), instr.me()).unwrap();
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}
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PpcOpcode::rlwnmx => {
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write!(out, "rlwnm r{},r{},r{},{},{}", instr.ra(), instr.rs(), instr.rb(), instr.mb(), instr.me()).unwrap();
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}
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// Special register moves
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PpcOpcode::mfspr => {
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let spr_name = match instr.spr() {
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1 => "xer",
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8 => "lr",
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9 => "ctr",
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268 => "tbl",
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269 => "tbu",
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_ => "",
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};
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if spr_name.is_empty() {
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write!(out, "mfspr r{},{}", instr.rd(), instr.spr()).unwrap();
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} else {
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write!(out, "mf{} r{}", spr_name, instr.rd()).unwrap();
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}
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}
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PpcOpcode::mtspr => {
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let spr_name = match instr.spr() {
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1 => "xer",
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8 => "lr",
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9 => "ctr",
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_ => "",
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};
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if spr_name.is_empty() {
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write!(out, "mtspr {},r{}", instr.spr(), instr.rs()).unwrap();
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} else {
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write!(out, "mt{} r{}", spr_name, instr.rs()).unwrap();
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}
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}
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PpcOpcode::mfcr => {
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write!(out, "mfcr r{}", instr.rd()).unwrap();
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}
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PpcOpcode::mtcrf => {
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write!(out, "mtcrf 0x{:02X},r{}", instr.crm(), instr.rs()).unwrap();
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}
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// Extend
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PpcOpcode::extsbx => write!(out, "extsb r{},r{}", instr.ra(), instr.rs()).unwrap(),
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PpcOpcode::extshx => write!(out, "extsh r{},r{}", instr.ra(), instr.rs()).unwrap(),
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PpcOpcode::extswx => write!(out, "extsw r{},r{}", instr.ra(), instr.rs()).unwrap(),
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PpcOpcode::cntlzwx => write!(out, "cntlzw r{},r{}", instr.ra(), instr.rs()).unwrap(),
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PpcOpcode::cntlzdx => write!(out, "cntlzd r{},r{}", instr.ra(), instr.rs()).unwrap(),
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// X-form load/store
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PpcOpcode::lwzx | PpcOpcode::lwzux | PpcOpcode::lbzx | PpcOpcode::lbzux |
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PpcOpcode::lhzx | PpcOpcode::lhzux | PpcOpcode::lhax | PpcOpcode::lhaux |
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PpcOpcode::lwax | PpcOpcode::lwaux | PpcOpcode::ldx | PpcOpcode::ldux |
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PpcOpcode::lfsx | PpcOpcode::lfsux | PpcOpcode::lfdx | PpcOpcode::lfdux |
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PpcOpcode::lwbrx | PpcOpcode::lhbrx | PpcOpcode::ldbrx |
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PpcOpcode::lwarx | PpcOpcode::ldarx => {
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write!(out, "{:?} r{},r{},r{}", instr.opcode, instr.rd(), instr.ra(), instr.rb()).unwrap();
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}
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PpcOpcode::stwx | PpcOpcode::stwux | PpcOpcode::stbx | PpcOpcode::stbux |
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PpcOpcode::sthx | PpcOpcode::sthux | PpcOpcode::stdx | PpcOpcode::stdux |
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PpcOpcode::stfsx | PpcOpcode::stfsux | PpcOpcode::stfdx | PpcOpcode::stfdux |
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PpcOpcode::stwbrx | PpcOpcode::sthbrx | PpcOpcode::stdbrx |
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PpcOpcode::stwcx | PpcOpcode::stdcx | PpcOpcode::stfiwx => {
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write!(out, "{:?} r{},r{},r{}", instr.opcode, instr.rs(), instr.ra(), instr.rb()).unwrap();
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}
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// Cache/sync ops (no-ops for interpreter)
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PpcOpcode::dcbf | PpcOpcode::dcbi | PpcOpcode::dcbst |
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PpcOpcode::dcbt | PpcOpcode::dcbtst | PpcOpcode::icbi => {
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write!(out, "{:?} r{},r{}", instr.opcode, instr.ra(), instr.rb()).unwrap();
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}
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PpcOpcode::dcbz | PpcOpcode::dcbz128 => {
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write!(out, "{:?} r{},r{}", instr.opcode, instr.ra(), instr.rb()).unwrap();
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}
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PpcOpcode::sync | PpcOpcode::eieio | PpcOpcode::isync => {
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write!(out, "{:?}", instr.opcode).unwrap();
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}
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// Load/store multiple
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PpcOpcode::lmw => write!(out, "lmw r{},{}(r{})", instr.rd(), instr.d(), instr.ra()).unwrap(),
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PpcOpcode::stmw => write!(out, "stmw r{},{}(r{})", instr.rs(), instr.d(), instr.ra()).unwrap(),
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// DS-form loads/stores
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PpcOpcode::ld | PpcOpcode::ldu | PpcOpcode::lwa => {
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write!(out, "{:?} r{},{}(r{})", instr.opcode, instr.rd(), instr.ds(), instr.ra()).unwrap();
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}
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PpcOpcode::std | PpcOpcode::stdu => {
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write!(out, "{:?} r{},{}(r{})", instr.opcode, instr.rs(), instr.ds(), instr.ra()).unwrap();
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}
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// CR logical ops
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PpcOpcode::crand | PpcOpcode::crandc | PpcOpcode::creqv | PpcOpcode::crnand |
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PpcOpcode::crnor | PpcOpcode::cror | PpcOpcode::crorc | PpcOpcode::crxor => {
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write!(out, "{:?} {},{},{}", instr.opcode, instr.crbd(), instr.crba(), instr.crbb()).unwrap();
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}
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PpcOpcode::mcrf => {
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write!(out, "mcrf cr{},cr{}", instr.crfd(), instr.crfs()).unwrap();
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}
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// Trap
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PpcOpcode::tdi => write!(out, "tdi {},r{},{}", instr.rd(), instr.ra(), instr.simm16()).unwrap(),
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PpcOpcode::twi => write!(out, "twi {},r{},{}", instr.rd(), instr.ra(), instr.simm16()).unwrap(),
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PpcOpcode::td => write!(out, "td {},r{},r{}", instr.rd(), instr.ra(), instr.rb()).unwrap(),
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PpcOpcode::tw => write!(out, "tw {},r{},r{}", instr.rd(), instr.ra(), instr.rb()).unwrap(),
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// Default: just print opcode and raw hex
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_ => {
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write!(out, "{:?} [{:08X}]", instr.opcode, instr.raw).unwrap();
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}
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}
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out
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}
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/// Disassemble a range of instructions from a byte slice.
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pub fn disassemble_block(data: &[u8], base_addr: u32, count: usize) -> Vec<(u32, String)> {
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let mut result = Vec::new();
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for i in 0..count {
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let offset = i * 4;
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if offset + 4 > data.len() {
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break;
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}
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let raw = u32::from_be_bytes([
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data[offset],
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data[offset + 1],
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data[offset + 2],
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data[offset + 3],
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]);
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let addr = base_addr + offset as u32;
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let instr = crate::decode(raw, addr);
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let text = disassemble(&instr);
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result.push((addr, text));
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}
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result
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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use crate::decoder::decode;
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#[test]
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fn test_disasm_nop() {
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// ori r0, r0, 0 = NOP
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let instr = decode(0x60000000, 0);
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let text = disassemble(&instr);
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assert!(text.contains("ori"), "Expected 'ori', got: {}", text);
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}
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#[test]
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fn test_disasm_addi() {
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let raw = (14u32 << 26) | (3 << 21) | (1 << 16) | 16;
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let instr = decode(raw, 0);
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let text = disassemble(&instr);
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assert!(text.contains("addi"), "Got: {}", text);
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assert!(text.contains("r3"), "Got: {}", text);
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}
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}
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