From caa37fc595a4021617a000ffbd41a5722a025516 Mon Sep 17 00:00:00 2001 From: MechaCat02 Date: Sat, 2 May 2026 14:49:43 +0200 Subject: [PATCH] docs(audit): post-P8 end-to-end review findings + acid test result Document the post-P8 cross-cutting review and acid test outcome: End-to-end reviewer caught: - BLOCKING-LIKELY: lwa/lwax/lwaux ISA deviation (fixed in f1166d0) - Cosmetic: fpscr round_single_toward_zero duplicate-branch (fixed in 09c6c92) - Minor performance: reservation table active_reservers as slot-occupancy - Asymmetry note: extswx remains 64-bit ABI per audit PPCBUG-038 (wontfix) Acid test (-n 4B --parallel --reservations-table, pre-lwa-hotfix build): - swaps=1, draws=0 - exit 0, no panics, no errors, no RtlRaiseException - 14 thread spawns, 2 LR-sentinel exits - Renderer plateau NOT unblocked by cumulative P1-P8 correctness fixes Implication: the Sylpheed `draws=0` plateau has a non-PPC-correctness root cause. PPC fixes were correctness-justified independent of the renderer (well-grounded against canary). Next investigation tracks: graphics pipeline (EDRAM resolve, RT readback), kernel HLE (event signaling, timers), or the unresolved BST-validation paradox per `project_xenia_rs_sylpheed_event_chain_2026_04_29.md`. Out of scope for the PPC instruction audit. Co-Authored-By: Claude Sonnet 4.6 --- audit-report-2026-04-29.md | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/audit-report-2026-04-29.md b/audit-report-2026-04-29.md index 70c47c8..2cf4536 100644 --- a/audit-report-2026-04-29.md +++ b/audit-report-2026-04-29.md @@ -520,6 +520,32 @@ After applying Phase 1 alone, run `xenia-rs check sylpheed.iso -n 4B --parallel` --- +### Post-P8 — End-to-end review + acid test (2026-05-02) + +**End-to-end reviewer findings** (cross-cutting after all 8 phases): + +1. **BLOCKING-LIKELY**: `lwa`/`lwax`/`lwaux` were converted to zero-extend in P4 batch 5 (PPCBUG-105 "minimal-fix"); reviewer flagged this as ISA-deviating. Per PowerISA, "Load Word and Algebraic" must sign-extend. Hotfix landed at HEAD f1166d0 — restored `as i32 as i64 as u64` form, updated test from `lwa_high_bit_set_zero_extends_upper` to `lwa_sign_extends_to_i64`. +2. **Cosmetic** `fpscr.rs:289` duplicate-branch typo in `round_single_toward_zero` — both branches were `adj_bits - 1`. Replaced with the unconditional form + comment. HEAD 09c6c92. +3. **Minor** reservation table's `active_reservers` counter is slot-occupancy, not reserver-count — once dirtied via cross-line-collision displacement, stores eternally pay the `invalidate_for_write` Acquire-load cost. Correctness-preserving (counter is upper bound), but performance can degrade. Documented; deferred to a focused performance sub-batch. +4. **Asymmetric** `extswx` is the only sign-extend opcode left at 64-bit ABI (P4 converted every other extsXx to 32-bit). Per PPCBUG-038 (audit `wontfix`), this matches ISA's documented "argument-register canonicalization in 64-bit mode" intent. No code change. Reviewer flagged the asymmetry — accepted. + +**Acid test result** (`xenia-rs check sylpheed.iso -n 4000000000 --parallel --reservations-table`, 2026-05-02 12:28→12:46): +- Exit code: 0 (clean termination, no panics, no RtlRaiseException, no halts) +- swaps=1 (frame=1 XE_SWAP, fb=0x4b0d7000, 1280×720) +- draws=0 +- 14 ExCreateThread spawns, 2 worker exits via LR sentinel +- The renderer plateau is **NOT unblocked** by the cumulative P1-P8 correctness fixes +- Note: the binary tested was pre-lwa-hotfix (built before commit f1166d0). The lwa change is unlikely to affect Sylpheed (compilers don't emit `lwa` in 32-bit-ABI code), but a re-run after the hotfix would be the conservative confirmation. + +**Implication**: the renderer plateau (`draws=0`) has a non-PPC-correctness root cause. The audit's catch was correctness-justified independent of the renderer (PPCBUGs are real bugs, well-grounded against canary), but the cumulative ~161 PPCBUG fixes do not unblock the specific Sylpheed-rendering issue. Next investigation tracks should focus on: +- Graphics-pipeline-side issues (EDRAM resolve gaps per `project_xenia_rs_edram_resolve_gap.md`, RT readback) +- Kernel HLE divergences (event signaling, timer queues, file system) +- The unresolved BST-validation paradox documented in `project_xenia_rs_sylpheed_event_chain_2026_04_29.md` (sub_82175E68 registers 0x828F3F68 in the BST but the validator doesn't find it eight instructions later) + +These are out of scope for the PPC instruction audit. + +--- + ## Index — every PPCBUG referenced (in numerical order) This list intentionally includes every ID found in `audit-findings.md` so nothing is dropped. For each entry's full description / file:line / fix snippet / test recommendation, see the corresponding `### PPCBUG-NNN` heading in `audit-findings.md`.