chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
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migration/project-root/ppc-manual/alu/addx.md
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migration/project-root/ppc-manual/alu/addx.md
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# `addx` — Add
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> **Category:** [Integer ALU](../categories/alu.md) · **Form:** [XO](../forms/XO.md) · **Opcode:** `0x7c000214`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `add` | `addx` | — | Add |
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| `addo` | `addx` | OE=1 | Add |
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| `add.` | `addx` | Rc=1 | Add |
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| `addo.` | `addx` | OE=1, Rc=1 | Add |
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## Syntax
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```asm
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add[OE][Rc] [RD], [RA], [RB]
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```
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## Encoding
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### `addx` — form `XO`
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- **Opcode word:** `0x7c000214`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `266`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (31) |
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| 6–10 | `RT` | destination GPR |
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| 11–15 | `RA` | source A |
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| 16–20 | `RB` | source B |
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| 21 | `OE` | overflow-enable flag |
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| 22–30 | `XO` | extended opcode (9 bits) |
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| 31 | `Rc` | record-form flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RA` | addx: read | Source GPR (`r0`–`r31`). |
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| `RB` | addx: read | Source GPR. |
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| `RD` | addx: write | Destination GPR. |
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| `OE` | addx: write (conditional) | Overflow-enable bit. When 1, the instruction updates `XER[OV]` and stickies `XER[SO]` on signed overflow. |
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| `CR` | addx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
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## Register Effects
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### `addx`
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- **Reads (always):** `RA`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `RD`
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- **Writes (conditional):** `OE`, `CR`
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## Status-Register Effects
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- `addx`: **CR0** ← signed-compare(result, 0) with `SO ← XER[SO]`, when `Rc=1`.; **XER[OV]** ← signed-overflow(result); **XER[SO]** stickies, when `OE=1`.
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## Operation (pseudocode)
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```
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RT <- (RA) + (RB)
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```
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## C Translation Example
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```c
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/* add / add. / addo / addo. (XO-form) */
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uint64_t a = r[insn.RA], b = r[insn.RB];
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uint64_t result = a + b;
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r[insn.RT] = result;
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if (insn.OE) { bool ov = (~(a ^ b) & (a ^ result)) >> 63;
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if (ov) { xer.OV = 1; xer.SO = 1; } else xer.OV = 0; }
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if (insn.Rc) update_cr0_signed((int64_t)result);
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```
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## Implementation References
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**`addx`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="addx"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_alu.cc:50`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_alu.cc#L50)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:8`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L8)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:875`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L875)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:175-189`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L175-L189)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::addx => {
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// PPCBUG-012+020: 32-bit ABI writeback truncation + CR0 i32 view.
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let ra32 = ctx.gpr[instr.ra()] as u32;
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let rb32 = ctx.gpr[instr.rb()] as u32;
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let result32 = ra32.wrapping_add(rb32);
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ctx.gpr[instr.rd()] = result32 as u64;
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if instr.oe() {
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let true_sum = (ra32 as i32 as i128) + (rb32 as i32 as i128);
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overflow::apply(ctx, true_sum != (result32 as i32) as i128);
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}
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if instr.rc_bit() {
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ctx.update_cr_signed(0, result32 as i32 as i64);
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}
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Extended Pseudocode
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```
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RT <- (RA) + (RB) ; modulo 2^64, carry discarded
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if OE then
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XER[OV] <- (~(RA ^ RB) & (RA ^ RT))[0] ; signed overflow: same-sign inputs, opposite-sign result
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XER[SO] <- XER[SO] | XER[OV]
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if Rc then
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CR0[LT,GT,EQ] <- signed_compare(RT, 0) ; 64-bit comparison on the Xenon
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CR0[SO] <- XER[SO]
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```
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## Special Cases & Edge Conditions
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- **No trap on overflow.** `addo` / `addo.` record overflow in `XER[OV]` and sticky-set `XER[SO]`. A trap can only be produced by a separate `td`/`tw` instruction examining the result.
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- **Signed-overflow predicate.** Overflow occurs iff both addends share a sign bit and the result has the opposite sign bit: `OV = ((~(a ^ b)) & (a ^ rt)) >> 63`. Unsigned carry is *not* tracked — use [`addcx`](addcx.md) when you need `XER[CA]`.
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- **`XER[SO]` is sticky.** Once set, it remains set until cleared by `mcrxr`. The `.` record forms copy it into `CR0[SO]`.
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- **64-bit CR update on Xenon.** The Xbox 360 Xenon CPU is 64-bit, so `add.` compares the full 64-bit result against zero. **Xenia-rs presently truncates to 32 bits** before the CR update (`result as i32 as i64` in [`interpreter.rs:95`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L95)). If your translator must match xenia bit-for-bit, emit a 32-bit compare; if it must be spec-correct, emit a 64-bit compare. Most Xbox 360 object code works either way because results that overflow 32 bits are rare outside of explicit 64-bit math.
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- **OE overflow detection not emulated in xenia-rs.** The `addo` / `addo.` branch in `interpreter.rs` is a `TODO` stub. A faithful translator should still emit the overflow check — titles rarely observe `XER[OV]`, but it's occasionally used by profiling / sanity-checking code paths.
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- **Operand aliasing.** `add r3, r3, r3`, `add r3, r3, r4`, `add r3, r4, r3` are all legal. The addition reads both source operands before writing `RT`.
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- **No immediate form.** For `RT = RA + imm` use [`addi`](addi.md) / [`addis`](addis.md). Those are distinct opcodes, not a flag on `add`.
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## Related Instructions
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- [`addcx`](addcx.md) — produces the carry-out in `XER[CA]`.
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- [`addex`](addex.md) — sums `(RA) + (RB) + XER[CA]` (carry-in chain).
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- [`addmex`](addmex.md), [`addzex`](addzex.md) — add to `−1` or `0` with carry-in (used to propagate borrows across multiword subtracts).
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- [`addi`](addi.md), [`addis`](addis.md) — D-form immediate adds; no `Rc`/`OE`.
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- [`addic`](addic.md), [`addicx`](addicx.md) — D-form adds that set `XER[CA]`.
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- [`subfx`](subfx.md) — the dual: `RT ← (RB) − (RA)`.
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- [`negx`](negx.md) — two's-complement negate.
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## IBM Reference
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- [AIX 7.3 — `add` (Add)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-add-instruction)
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- [PowerISA v2.07B, Book I, §3.3.8 — Fixed-Point Arithmetic Instructions](https://openpowerfoundation.org/specifications/isa/) (overflow predicate, CR0 / `XER[SO]` semantics).
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