chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
137
migration/project-root/ppc-manual/alu/divwux.md
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migration/project-root/ppc-manual/alu/divwux.md
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# `divwux` — Divide Word Unsigned
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> **Category:** [Integer ALU](../categories/alu.md) · **Form:** [XO](../forms/XO.md) · **Opcode:** `0x7c000396`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `divwu` | `divwux` | — | Divide Word Unsigned |
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| `divwuo` | `divwux` | OE=1 | Divide Word Unsigned |
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| `divwu.` | `divwux` | Rc=1 | Divide Word Unsigned |
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| `divwuo.` | `divwux` | OE=1, Rc=1 | Divide Word Unsigned |
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## Syntax
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```asm
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divwu[OE][Rc] [RD], [RA], [RB]
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```
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## Encoding
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### `divwux` — form `XO`
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- **Opcode word:** `0x7c000396`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `459`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (31) |
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| 6–10 | `RT` | destination GPR |
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| 11–15 | `RA` | source A |
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| 16–20 | `RB` | source B |
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| 21 | `OE` | overflow-enable flag |
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| 22–30 | `XO` | extended opcode (9 bits) |
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| 31 | `Rc` | record-form flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RA` | divwux: read | Source GPR (`r0`–`r31`). |
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| `RB` | divwux: read | Source GPR. |
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| `RD` | divwux: write | Destination GPR. |
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| `OE` | divwux: write (conditional) | Overflow-enable bit. When 1, the instruction updates `XER[OV]` and stickies `XER[SO]` on signed overflow. |
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| `CR` | divwux: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
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## Register Effects
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### `divwux`
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- **Reads (always):** `RA`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `RD`
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- **Writes (conditional):** `OE`, `CR`
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## Status-Register Effects
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- `divwux`: **CR0** ← signed-compare(result, 0) with `SO ← XER[SO]`, when `Rc=1`.; **XER[OV]** ← signed-overflow(result); **XER[SO]** stickies, when `OE=1`.
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## Operation (pseudocode)
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```
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RT <- ((RA)[32:63] /u (RB)[32:63]) zero-extended to 64 ; undefined if RB=0
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`divwux`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="divwux"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_alu.cc:269`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_alu.cc#L269)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:21`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L21)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:877`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L877)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:413-430`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L413-L430)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::divwux => {
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// PPCBUG-020: 32-bit ABI CR0 view.
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let ra = ctx.gpr[instr.ra()] as u32;
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let rb = ctx.gpr[instr.rb()] as u32;
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let ov = overflow::divw_ov_unsigned(rb);
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if ov {
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ctx.gpr[instr.rd()] = 0;
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} else {
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ctx.gpr[instr.rd()] = (ra / rb) as u64;
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}
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if instr.oe() {
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overflow::apply(ctx, ov);
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}
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if instr.rc_bit() {
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ctx.update_cr_signed(0, ctx.gpr[instr.rd()] as u32 as i32 as i64);
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}
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **32-bit operands, zero-extended result.** Both `RA` and `RB` are read as their low 32 bits, unsigned (`as u32`); the quotient is computed as `u32`, then *zero-extended* to 64 bits. The high 32 bits of `RA`/`RB` are ignored on input and the high 32 bits of `RT` are zero on output.
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- **Single undefined case.** Division by zero (`RB == 0`); xenia-rs returns 0 ([`interpreter.rs:251`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L251)). No `INT_MIN/-1` case because the operands are unsigned.
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- **No trap on Xenon.** Same as [`divdx`](divdx.md) — silent undefined result.
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- **`OE=1` should set `XER[OV]` on `RB == 0`**; xenia-rs ignores this.
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- **`Rc=1` CR0 update.** [`interpreter.rs:256`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L256) uses `as i32 as i64` — for an unsigned 32-bit quotient stored in the low 32 bits with high zeros, this matches spec exactly; the i32 view will be negative iff the unsigned quotient ≥ 2^31. Worth flagging when comparing CR0 against zero after a large `divwu`.
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- **Truncating quotient.** Floor division for non-negative integers; matches C `unsigned` semantics.
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- **Same slow non-pipelined latency** as `divw`.
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## Related Instructions
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- [`divwx`](divwx.md) — signed 32-bit divide.
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- [`divdux`](divdux.md), [`divdx`](divdx.md) — 64-bit variants.
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- [`mullwx`](mullwx.md) — pair to recover the remainder.
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- [`cmplwi`](cmpli.md) (simplified) — guard the divisor.
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## IBM Reference
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- [AIX 7.3 — `divwu` (Divide Word Unsigned)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-divwu-divide-word-unsigned-instruction)
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