chore: add migration/ bundle for cross-machine setup

Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on another machine can be brought up to identical configuration via migration/setup.sh: - claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/ (103 files, 1.1 MB - MEMORY.md + every project_xenia_rs_*.md from audits addis_signext through audit-058) - project-root/dot-claude/ <project-root>/.claude/settings.json (Stop hook + permissions) - project-root/ppc-manual/ <project-root>/ppc-manual/ (PowerPC reference docs, 397 files, 3.7 MB) - project-root/run-canary.sh <project-root>/run-canary.sh - README.md Human-readable setup checklist - setup.sh Idempotent installer (also reclones xenia-canary at pinned HEAD 6de80dffe) - MANIFEST.md Per-file mapping + per-file-not-bundled restoration recipe Excluded from bundle (not shippable via git): - Sylpheed ISO (7.8 GB; copyright; manual copy required) - sylpheed.db (395 MB; regenerable from XEX via analysis tooling) - target/ build artifacts (rebuild on target) - audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed) - audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed) - xenia-canary checkout (setup.sh reclones from git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe) Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
2026-05-10 21:38:38 +02:00
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+# `isync` — Instruction Synchronize
+
+> **Category:** [Integer ALU](../categories/alu.md) · **Form:** [XL](../forms/XL.md) · **Opcode:** `0x4c00012c`
+
+<!-- GENERATED: BEGIN -->
+
+## Assembler Mnemonics
+
+| Mnemonic | XML entry | Flags | Description |
+| --- | --- | --- | --- |
+| `isync` | `isync` | — | Instruction Synchronize |
+
+## Syntax
+
+```asm
+isync
+```
+
+## Encoding
+
+### `isync` — form `XL`
+
+- **Opcode word:** `0x4c00012c`
+- **Primary opcode (bits 0–5):** `19`
+- **Extended opcode:** `150`
+- **Synchronising:** no
+
+| Bits | Field | Meaning |
+| --- | --- | --- |
+| 0–5 | `OPCD` | primary opcode (19) |
+| 6–10 | `BT/BO` | target / branch options |
+| 11–15 | `BA/BI` | source A / CR bit to test |
+| 16–20 | `BB` | source B |
+| 21–30 | `XO` | extended opcode (10 bits) |
+| 31 | `LK` | link flag |
+
+## Operands
+
+| Field | Role | Description |
+| --- | --- | --- |
+
+## Register Effects
+
+### `isync`
+
+- **Reads (always):** _none_
+- **Reads (conditional):** _none_
+- **Writes (always):** _none_
+- **Writes (conditional):** _none_
+
+## Status-Register Effects
+
+_No condition-register or status-register effects._
+
+## Operation (pseudocode)
+
+```
+instruction-stream synchronisation — discards speculative state.
+```
+
+## C Translation Example
+
+```c
+/* C translation: the xenia-rs interpreter arm below in           */
+/* Implementation References is the authoritative semantic        */
+/* snapshot. Translate it line-by-line:                            */
+/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
+/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
+/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
+/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
+/* The Register Effects and Status-Register Effects tables above  */
+/* enumerate every side effect a faithful translation must emit.  */
+```
+
+## Implementation References
+
+**`isync`**
+- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="isync"`](../../xenia-canary/tools/ppc-instructions.xml)
+- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:759`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_memory.cc#L759)
+- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:32`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L32)
+- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:714`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L714)
+- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1691-1693`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1691-L1693)
+<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
+
+```rust
+        PpcOpcode::sync | PpcOpcode::eieio | PpcOpcode::isync => {
+            ctx.pc += 4;
+        }
+```
+</details>
+
+<!-- GENERATED: END -->
+
+## Special Cases & Edge Conditions
+
+- **Instruction-fetch barrier.** Discards any speculatively fetched/decoded instructions and forces all subsequent ones to be re-fetched after preceding instructions complete. Required after self-modifying code, JIT-emitted code, and after MMU/page-table changes.
+- **Stronger than [`sync`](sync.md) for instruction stream**, weaker for memory stream — `isync` does not order stores against later loads. It only forces a fetch refresh.
+- **Common idiom: `dcbf` / `icbi` / `sync` / `isync`** — flush data cache, invalidate instruction cache, drain memory, refetch — used by JITs and self-modifying loaders.
+- **No operands.** Encoded as a fixed-form `XL` instruction; assemblers always emit `0x4c00012c`.
+- **Xenia-rs is a no-op.** [`interpreter.rs:1267`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1267) handles `sync`/`eieio`/`isync` together. Because xenia interprets in straight-line program order without any speculative instruction cache, no barrier behaviour is needed for correctness.
+- **Privilege level: user.** Unlike most cache management ops, `isync` is unprivileged and frequently appears in userland trampolines.
+
+## Related Instructions
+
+- [`sync`](sync.md) — heavy memory barrier.
+- [`eieio`](eieio.md) — I/O ordering for caching-inhibited storage.
+- `icbi`, `dcbf`, `dcbst` — cache management ops (outside this page set) usually paired with `isync`.
+
+## IBM Reference
+
+- [AIX 7.3 — `isync` (Instruction Synchronize)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-isync-instruction-synchronize-instruction)