chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
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migration/project-root/ppc-manual/alu/mulhdx.md
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migration/project-root/ppc-manual/alu/mulhdx.md
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# `mulhdx` — Multiply High Doubleword
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> **Category:** [Integer ALU](../categories/alu.md) · **Form:** [XO](../forms/XO.md) · **Opcode:** `0x7c000092`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `mulhd` | `mulhdx` | — | Multiply High Doubleword |
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| `mulhd.` | `mulhdx` | Rc=1 | Multiply High Doubleword |
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## Syntax
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```asm
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mulhd[Rc] [RD], [RA], [RB]
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```
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## Encoding
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### `mulhdx` — form `XO`
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- **Opcode word:** `0x7c000092`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `73`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (31) |
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| 6–10 | `RT` | destination GPR |
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| 11–15 | `RA` | source A |
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| 16–20 | `RB` | source B |
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| 21 | `OE` | overflow-enable flag |
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| 22–30 | `XO` | extended opcode (9 bits) |
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| 31 | `Rc` | record-form flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `RA` | mulhdx: read | Source GPR (`r0`–`r31`). |
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| `RB` | mulhdx: read | Source GPR. |
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| `RD` | mulhdx: write | Destination GPR. |
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| `CR` | mulhdx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
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## Register Effects
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### `mulhdx`
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- **Reads (always):** `RA`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `RD`
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- **Writes (conditional):** `CR`
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## Status-Register Effects
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- `mulhdx`: **CR0** ← signed-compare(result, 0) with `SO ← XER[SO]`, when `Rc=1`.
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## Operation (pseudocode)
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```
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RT <- ((RA) * (RB))[0:63] ; high 64 of signed 64×64
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`mulhdx`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="mulhdx"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_alu.cc:297`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_alu.cc#L297)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:57`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L57)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:864`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L864)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:445-453`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L445-L453)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::mulhdx => {
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let ra = ctx.gpr[instr.ra()] as i64 as i128;
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let rb = ctx.gpr[instr.rb()] as i64 as i128;
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ctx.gpr[instr.rd()] = (ra.wrapping_mul(rb) >> 64) as u64;
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if instr.rc_bit() {
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ctx.update_cr_signed(0, ctx.gpr[instr.rd()] as i64);
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}
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Returns the high 64 bits of a signed 64×64 product.** Pair with [`mulldx`](mulldx.md) (which returns the low 64 bits) to obtain the full 128-bit product. Both must be issued separately; PowerPC has no fused multiply-double-wide instruction.
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- **No `OE` bit.** This XO-form instruction has no overflow-enable variant — there is no "high half overflow" because the high half is always defined.
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- **Xenia widens to `i128` natively.** [`interpreter.rs:275`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L275) does the multiply in 128 bits then extracts the high 64. The `i64 as i128` casts ensure signed extension on both sides.
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- **`Rc=1` CR0 update is correctly 64-bit.** [`interpreter.rs:278`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L278) uses `as i64` directly. CR0 reflects the sign of the high half: `LT` if the product is negative, `GT` if positive and large enough to overflow into the high half, `EQ` if the product fits in 64 bits *signed* (so the high half is the sign-extension of the low half — but xenia's check uses raw signed-zero compare, which equates only when the high half is exactly zero, i.e. the product is in `[0, 2^63)`).
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- **Use [`mulhdux`](mulhdux.md) for the unsigned high half.** The two instructions differ in whether the operands are sign- or zero-extended before the multiply.
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- **Slow.** 64-bit multiply is multi-cycle on Xenon; combining `mulhd` with `mulld` for a full 128-bit product roughly doubles the cost.
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## Related Instructions
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- [`mulldx`](mulldx.md) — low 64 bits of the same signed product.
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- [`mulhdux`](mulhdux.md) — high 64 bits, unsigned interpretation.
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- [`mullwx`](mullwx.md), [`mulhwx`](mulhwx.md), [`mulhwux`](mulhwux.md) — 32-bit family.
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- [`divdx`](divdx.md), [`divdux`](divdux.md) — 64-bit division.
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## IBM Reference
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- [AIX 7.3 — `mulhd` (Multiply High Doubleword)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-mulhd-multiply-high-double-word-instruction)
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