chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
180
migration/project-root/ppc-manual/branch/bclrx.md
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migration/project-root/ppc-manual/branch/bclrx.md
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# `bclrx` — Branch Conditional to Link Register
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> **Category:** [Branch & System](../categories/branch.md) · **Form:** [XL](../forms/XL.md) · **Opcode:** `0x4c000020` · _sync_
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `bclr` | `bclrx` | — | Branch Conditional to Link Register |
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| `bclrl` | `bclrx` | LK=1 | Branch Conditional to Link Register |
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## Syntax
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```asm
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bclr[LK] [BO], [BI]
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```
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## Encoding
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### `bclrx` — form `XL`
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- **Opcode word:** `0x4c000020`
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- **Primary opcode (bits 0–5):** `19`
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- **Extended opcode:** `16`
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- **Synchronising:** yes
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (19) |
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| 6–10 | `BT/BO` | target / branch options |
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| 11–15 | `BA/BI` | source A / CR bit to test |
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| 16–20 | `BB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `LK` | link flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `LK` | bclrx: read | Link bit. When 1, LR ← address-of-next-instruction before the branch is taken. |
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| `BO` | bclrx: read | 5-bit branch options — selects CTR decrement, CTR test polarity, and CR bit test polarity. See `forms/XL.md`. |
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| `BI` | bclrx: read | CR bit index (0–31) selected by BO's condition test. |
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| `CR` | bclrx: read (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
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| `CTR` | bclrx: read (conditional); bclrx: write (conditional) | Count register. Decremented and optionally tested by conditional branches when `BO[2]=0`. |
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| `LR` | bclrx: write (conditional) | Link register. Written by `bl`/`bla`/`bcl`/`bclrl`/`bcctrl`; read by `bclr`/`bclrl`. |
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## Register Effects
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### `bclrx`
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- **Reads (always):** `LK`, `BO`, `BI`
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- **Reads (conditional):** `CR`, `CTR`
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- **Writes (always):** _none_
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- **Writes (conditional):** `CTR`, `LR`
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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if ¬BO[2] then CTR <- CTR − 1
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ctr_ok <- BO[2] | ((CTR ≠ 0) XOR BO[3])
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cond_ok <- BO[0] | (CR[BI] ≡ BO[1])
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if ctr_ok & cond_ok then NIA <- LR[0:61] || 0b00
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if LK then LR <- CIA + 4
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```
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## C Translation Example
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```c
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/* bclr/bclrl — branch conditional to LR */
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if (!(insn.BO & 4)) ctr -= 1;
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bool ctr_ok = (insn.BO & 4) || ((ctr != 0) ^ !!(insn.BO & 2));
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bool cond_ok = (insn.BO & 16) || (cr_bit(insn.BI) == !!(insn.BO & 8));
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uint32_t next = pc + 4;
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if (ctr_ok && cond_ok) pc = lr & ~3u; else pc = next;
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if (insn.LK) lr = next;
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```
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## Implementation References
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**`bclrx`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="bclrx"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_control.cc:282`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_control.cc#L282)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:11`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L11)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:711`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L711)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:939-961`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L939-L961)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::bclrx => {
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let bo = instr.bo();
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let bi = instr.bi();
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if bo & 0b00100 == 0 {
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ctx.ctr = ctx.ctr.wrapping_sub(1);
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}
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let ctr_ok = (bo & 0b00100) != 0
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|| (((ctx.ctr as u32) != 0) ^ ((bo & 0b00010) != 0));
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let cond_ok = (bo & 0b10000) != 0
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|| (ctx.get_cr_bit(bi) == ((bo & 0b01000) != 0));
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let next_pc = ctx.pc + 4;
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if ctr_ok && cond_ok {
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ctx.pc = (ctx.lr as u32) & !3;
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} else {
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ctx.pc = next_pc;
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}
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if instr.lk() {
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ctx.lr = next_pc as u64;
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}
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}
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```
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</details>
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<!-- GENERATED: END -->
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## BO Encoding (5 bits)
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`BO` controls two independent tests and two "hints". Bit 0 is the MSB.
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| BO (binary) | CTR decrement? | CTR test | CR test | Meaning |
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| --- | --- | --- | --- | --- |
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| `0000z` | yes | `CTR ≠ 0` | `¬CR[BI]` | decrement, branch if CTR ≠ 0 **and** CR[BI] false |
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| `0001z` | yes | `CTR = 0` | `¬CR[BI]` | decrement, branch if CTR = 0 **and** CR[BI] false |
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| `001at` | yes | `CTR ≠ 0` / `CTR = 0` | — | decrement, branch on CTR only |
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| `0100z` | no | — | `¬CR[BI]` | branch if CR[BI] false |
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| `0101z` | no | — | `CR[BI]` | branch if CR[BI] true |
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| `011at` | no | — | — | branch always (`z` and `t` are prediction hints) |
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| `1z00z` | yes | `CTR ≠ 0` | — | decrement, branch if CTR ≠ 0 |
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| `1z01z` | yes | `CTR = 0` | — | decrement, branch if CTR = 0 |
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| `1z1zz` | no | — | — | branch always |
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Bit **`BO[0]` = 1** disables the CR test; **`BO[2]` = 1** disables the CTR decrement/test. `BO[1]` and `BO[3]` select the polarity of each test. `BO[4]` is a branch-prediction hint (0 = not taken, 1 = taken; ignored on the Xenon in most cases).
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The most common bclr instance in Xbox 360 disassembly is `BO = 0b10100` → `blr` (branch always to LR), the function epilogue. `BO = 0b01100, BI = 2` → `beqlr` (return if `cr0.EQ`), also common.
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## Special Cases & Edge Conditions
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- **LR alignment mask.** The target address is `LR & ~3` — the low 2 bits are cleared. This silently ignores a misaligned LR; incoming code should always produce 4-byte-aligned LR values.
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- **Ordering of CTR decrement and branch.** The CTR is decremented **first**, then compared to zero **after** the decrement. So after `bdnz` at `CTR = 1`, the CTR becomes `0` and the branch is not taken.
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- **Self-referential LR write.** `bclrl` writes `LR ← CIA + 4` **before** reading `LR` to set `NIA`. Per the PowerISA, `bclrl` reads the *old* `LR` for the branch target and writes the *new* `LR` with the return address, atomically from software's perspective. Xenia implements it this way (`next_pc` captured first, then `lr` written).
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- **Branch prediction hints (`BO[4]`).** The Xenon does static prediction on the basis of these hints, but behaviour is architecturally unobservable. Translators may ignore them.
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- **Synchronisation.** `bclr` is **context-synchronising** (hence the `sync` flag in xenia's XML). Translators must ensure side-effecting instructions preceding the branch have committed — trivial in a sequential C translation but relevant for JIT backends.
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- **xenia's `LR_HALT_SENTINEL`.** Xenia sets `LR` to `0xBCBCBCBC` at thread start; when the top-level guest function returns via `blr`, the interpreter loop halts cleanly. Translators replicating guest behaviour don't need this — but if you generate a test harness, the sentinel is a convenient "function returned" signal.
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## Related Instructions
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- [`bcctrx`](bcctrx.md) — branch conditional to **CTR** (used by indirect calls / vtables).
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- [`bcx`](bcx.md) — branch conditional to an immediate displacement (D-form).
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- [`bx`](bx.md) — unconditional branch (I-form).
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- [`mtlr`](../control/mtspr.md), [`mflr`](../control/mfspr.md) — set/get LR via `mtspr 8, …` / `mfspr …, 8`.
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- [`sc`](sc.md) — system call (alternative control-flow exit).
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## Simplified Mnemonics
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Assemblers fold common `BO`/`BI` patterns to single mnemonics:
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| Simplified | Expansion |
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| --- | --- |
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| `blr` | `bclr BO=0b10100, BI=0` — branch always to LR |
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| `blrl` | `bclrl BO=0b10100, BI=0` — branch always to LR with link (tail-call trampoline) |
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| `beqlr crN` | `bclr BO=0b01100, BI=4·N+2` — return if `crN.EQ` |
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| `bnelr crN` | `bclr BO=0b00100, BI=4·N+2` — return if `crN.NE` |
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| `bltlr crN` | `bclr BO=0b01100, BI=4·N+0` — return if `crN.LT` |
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| `bgelr crN` | `bclr BO=0b00100, BI=4·N+0` — return if `crN.GE` |
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| `bgtlr crN` | `bclr BO=0b01100, BI=4·N+1` — return if `crN.GT` |
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| `blelr crN` | `bclr BO=0b00100, BI=4·N+1` — return if `crN.LE` |
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Xbox 360 disassemblers almost always emit the simplified form; the translation agent should learn to recognise them.
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## IBM Reference
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- [AIX 7.3 — `bclr` (Branch Conditional to Link Register)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-bclr-bclrl-branch-conditional-link-register-instruction)
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- [AIX 7.3 — Branch simplified mnemonics](https://www.ibm.com/docs/en/aix/7.3.0?topic=mnemonics-branch-simplified)
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