chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
184
migration/project-root/ppc-manual/branch/td.md
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184
migration/project-root/ppc-manual/branch/td.md
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# `td` — Trap Doubleword
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> **Category:** [Branch & System](../categories/branch.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c000088`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `td` | `td` | — | Trap Doubleword |
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## Syntax
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```asm
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td [TO], [RA], [RB]
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```
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## Encoding
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### `td` — form `X`
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- **Opcode word:** `0x7c000088`
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- **Primary opcode (bits 0–5):** `31`
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- **Extended opcode:** `68`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `TO` | td: read | Trap-on condition mask (5 bits) — LT, GT, EQ, LGT, LLT bits. |
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| `RA` | td: read | Source GPR (`r0`–`r31`). |
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| `RB` | td: read | Source GPR. |
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## Register Effects
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### `td`
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- **Reads (always):** `TO`, `RA`, `RB`
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- **Reads (conditional):** _none_
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- **Writes (always):** _none_
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- **Writes (conditional):** _none_
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## Status-Register Effects
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_No condition-register or status-register effects._
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`td`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="td"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_control.cc:552`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_control.cc#L552)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:87`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L87)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:769`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L769)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1762-1796`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1762-L1796)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::tw | PpcOpcode::twi | PpcOpcode::td | PpcOpcode::tdi => {
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// PPCBUG-063: save CIA before incrementing so a trap handler reads
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// the faulting instruction address, not CIA+4.
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// PPCBUG-065: log the SIMM type code on `twi 31, r0, IMM` (Xbox 360
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// typed-trap convention used by the CRT/kernel for C++ exception
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// class dispatch). The audit notes this is relevant to the Sylpheed
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// throw investigation; routing the type code via a payload requires
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// a StepResult enum extension that's deferred for now.
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let trap_pc = ctx.pc;
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let a = ctx.gpr[instr.ra()];
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let b = match instr.opcode {
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PpcOpcode::twi | PpcOpcode::tdi => instr.simm16() as i64 as u64,
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_ => ctx.gpr[instr.rb()],
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};
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let width = match instr.opcode {
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PpcOpcode::tw | PpcOpcode::twi => trap::TrapWidth::Word,
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_ => trap::TrapWidth::Doubleword,
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};
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let fired = trap::evaluate(instr.to(), a, b, width);
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if fired {
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let typed_trap_simm = if matches!(instr.opcode, PpcOpcode::twi)
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&& instr.to() == 31 && instr.ra() == 0 {
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Some(instr.simm16() as u16)
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} else { None };
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tracing::warn!(
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"Trap fired at {:#010x}: {:?} TO={} a={:#x} b={:#x}{}",
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trap_pc, instr.opcode, instr.to(), a, b,
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typed_trap_simm.map_or(String::new(), |t| format!(" typed_trap_simm={:#06x}", t))
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);
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// Leave ctx.pc at CIA (NOT NIA) so trap handlers / SEH delivery
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// can read the faulting instruction address from ctx.pc.
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return StepResult::Trap;
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}
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **`TO` mask encoding (5 bits, MSB-first).** Each bit selects one comparison; the trap fires if *any* selected condition is true. Both operands are treated as 64-bit doublewords:
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| Bit | Mnemonic | Triggered when |
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| --- | --- | --- |
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| `TO[0]` (16) | LT | `(int64) RA < (int64) RB` |
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| `TO[1]` (8) | GT | `(int64) RA > (int64) RB` |
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| `TO[2]` (4) | EQ | `RA == RB` |
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| `TO[3]` (2) | LGT | `(uint64) RA < (uint64) RB` (logical less) |
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| `TO[4]` (1) | LLT | `(uint64) RA > (uint64) RB` (logical greater — historical naming) |
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- **`TO = 31` is unconditional trap.** All five bits set ⇒ the trap fires regardless of operand values; the simplified mnemonic `trap` is `tw 31, 0, 0` for words and **`td 31, 0, 0`** for doublewords. The PowerISA also uses `tdi 31, 0, 0` (or `twi`) as a debugger break.
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- **64-bit comparison.** Unlike [`tw`](tw.md), `td` always compares the full 64-bit GPRs. On the Xenon (64-bit) this is meaningful; PPC32 implementations don't have `td`.
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- **No register effects.** Only the side effect is the trap. No CR/LR/CTR/XER updates.
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- **Hardware behaviour.** When the trap fires, hardware raises a Program interrupt with `SRR1[TRAP]` set and vectors to `0x700`. The Xbox 360 hypervisor / kernel handles it (assertion failure, debugger trap, etc.).
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- **xenia simplification.** xenia-rs collapses all four trap variants (`td`, `tdi`, `tw`, `twi`) into one match arm that *unconditionally* logs and returns `StepResult::Trap` — it does **not** evaluate `TO` against the operands. This is a material divergence from the spec: in xenia every trap fires even if the condition is false. Real Xenon code rarely uses non-trivial `TO` masks (typical use is the unconditional `trap` for `__assert` / debugger break), so the divergence is normally invisible.
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- **Distinguishing assert vs. break.** Compilers commonly emit `tdne r3, r3` (impossible) or `tdi 0, r0, 0` patterns that *cannot* trap as inert markers. Xenia's blanket trap would mis-fire on these — a small known bug; track it if you see spurious traps.
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## Related Instructions
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- [`tdi`](tdi.md) — same condition test against a 16-bit signed immediate (D-form).
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- [`tw`](tw.md) / [`twi`](twi.md) — 32-bit (word) variants for comparing low halves of GPRs.
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- [`sc`](sc.md) — synchronous kernel entry via system-call exception (different vector, different intent).
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- [`mtmsr`](../control/mtmsr.md) — kernel returns from the trap handler via `rfid`-family instructions.
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### Simplified Mnemonics
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| Simplified | Expansion | Triggered when |
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| --- | --- | --- |
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| `td RA, RB` (=`tdu`) | `td 31, RA, RB` | unconditional trap |
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| `tdeq RA, RB` | `td 4, RA, RB` | `RA == RB` |
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| `tdne RA, RB` | `td 24, RA, RB` | `RA != RB` |
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| `tdlt RA, RB` | `td 16, RA, RB` | signed less than |
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| `tdle RA, RB` | `td 20, RA, RB` | signed less or equal |
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| `tdgt RA, RB` | `td 8, RA, RB` | signed greater than |
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| `tdge RA, RB` | `td 12, RA, RB` | signed greater or equal |
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| `tdllt RA, RB` | `td 2, RA, RB` | unsigned less than |
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| `tdlge RA, RB` | `td 5, RA, RB` | unsigned greater or equal |
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| `tdlgt RA, RB` | `td 1, RA, RB` | unsigned greater than |
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| `tdlle RA, RB` | `td 6, RA, RB` | unsigned less or equal |
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## IBM Reference
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- [AIX 7.3 — `td` (Trap Doubleword)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-td-trap-doubleword-instruction)
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- [AIX 7.3 — Trap simplified mnemonics](https://www.ibm.com/docs/en/aix/7.3.0?topic=mnemonics-trap-simplified)
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- PowerISA v2.07B, Book I §3.3.11 — fixed-point trap instructions (`TO` semantics).
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Reference in New Issue
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