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chore: add migration/ bundle for cross-machine setup

Browse Source 
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:

  - claude-memory/             ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
                               (103 files, 1.1 MB - MEMORY.md + every
                                project_xenia_rs_*.md from audits
                                addis_signext through audit-058)
  - project-root/dot-claude/   <project-root>/.claude/settings.json
                               (Stop hook + permissions)
  - project-root/ppc-manual/   <project-root>/ppc-manual/
                               (PowerPC reference docs, 397 files, 3.7 MB)
  - project-root/run-canary.sh <project-root>/run-canary.sh
  - README.md                  Human-readable setup checklist
  - setup.sh                   Idempotent installer (also reclones
                               xenia-canary at pinned HEAD 6de80dffe)
  - MANIFEST.md                Per-file mapping + per-file-not-bundled
                               restoration recipe

Excluded from bundle (not shippable via git):
  - Sylpheed ISO (7.8 GB; copyright; manual copy required)
  - sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
  - target/ build artifacts (rebuild on target)
  - audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
  - audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
  - xenia-canary checkout (setup.sh reclones from
    git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
2026-05-10 21:38:38 +02:00
parent 8e709b0a24
commit e6d43a23ac
505 changed files with 86028 additions and 0 deletions
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# Integer ALU
Fixed-point add/sub/multiply/divide, logical, rotate, shift, compare, count-leading-zeros, sign-extension, trap-on-condition.
**70 families** · **70 XML entries**.
<!-- GENERATED: BEGIN -->
| Family | Form | Description | Members |
| --- | --- | --- | --- |
| [`addcx`](addcx.md) | `XO` | Add Carrying | `addcx` |
| [`addex`](addex.md) | `XO` | Add Extended | `addex` |
| [`addi`](addi.md) | `D` | Add Immediate | `addi` |
| [`addic`](addic.md) | `D` | Add Immediate Carrying | `addic` |
| [`addic.`](addicx.md) | `D` | Add Immediate Carrying and Record | `addic.` |
| [`addis`](addis.md) | `D` | Add Immediate Shifted | `addis` |
| [`addmex`](addmex.md) | `XO` | Add to Minus One Extended | `addmex` |
| [`addx`](addx.md) | `XO` | Add | `addx` |
| [`addzex`](addzex.md) | `XO` | Add to Zero Extended | `addzex` |
| [`andcx`](andcx.md) | `X` | AND with Complement | `andcx` |
| [`andi.`](andix.md) | `D` | AND Immediate | `andi.` |
| [`andis.`](andisx.md) | `D` | AND Immediate Shifted | `andis.` |
| [`andx`](andx.md) | `X` | AND | `andx` |
| [`cmp`](cmp.md) | `X` | Compare | `cmp` |
| [`cmpi`](cmpi.md) | `D` | Compare Immediate | `cmpi` |
| [`cmpl`](cmpl.md) | `X` | Compare Logical | `cmpl` |
| [`cmpli`](cmpli.md) | `D` | Compare Logical Immediate | `cmpli` |
| [`cntlzdx`](cntlzdx.md) | `X` | Count Leading Zeros Doubleword | `cntlzdx` |
| [`cntlzwx`](cntlzwx.md) | `X` | Count Leading Zeros Word | `cntlzwx` |
| [`divdux`](divdux.md) | `XO` | Divide Doubleword Unsigned | `divdux` |
| [`divdx`](divdx.md) | `XO` | Divide Doubleword | `divdx` |
| [`divwux`](divwux.md) | `XO` | Divide Word Unsigned | `divwux` |
| [`divwx`](divwx.md) | `XO` | Divide Word | `divwx` |
| [`eieio`](eieio.md) | `X` | Enforce In-Order Execution of I/O | `eieio` |
| [`eqvx`](eqvx.md) | `X` | Equivalent | `eqvx` |
| [`extsbx`](extsbx.md) | `X` | Extend Sign Byte | `extsbx` |
| [`extshx`](extshx.md) | `X` | Extend Sign Half Word | `extshx` |
| [`extswx`](extswx.md) | `X` | Extend Sign Word | `extswx` |
| [`isync`](isync.md) | `XL` | Instruction Synchronize | `isync` |
| [`mulhdux`](mulhdux.md) | `XO` | Multiply High Doubleword Unsigned | `mulhdux` |
| [`mulhdx`](mulhdx.md) | `XO` | Multiply High Doubleword | `mulhdx` |
| [`mulhwux`](mulhwux.md) | `XO` | Multiply High Word Unsigned | `mulhwux` |
| [`mulhwx`](mulhwx.md) | `XO` | Multiply High Word | `mulhwx` |
| [`mulldx`](mulldx.md) | `XO` | Multiply Low Doubleword | `mulldx` |
| [`mulli`](mulli.md) | `D` | Multiply Low Immediate | `mulli` |
| [`mullwx`](mullwx.md) | `XO` | Multiply Low Word | `mullwx` |
| [`nandx`](nandx.md) | `X` | NAND | `nandx` |
| [`negx`](negx.md) | `XO` | Negate | `negx` |
| [`norx`](norx.md) | `X` | NOR | `norx` |
| [`orcx`](orcx.md) | `X` | OR with Complement | `orcx` |
| [`ori`](ori.md) | `D` | OR Immediate | `ori` |
| [`oris`](oris.md) | `D` | OR Immediate Shifted | `oris` |
| [`orx`](orx.md) | `X` | OR | `orx` |
| [`rldclx`](rldclx.md) | `MDS` | Rotate Left Doubleword then Clear Left | `rldclx` |
| [`rldcrx`](rldcrx.md) | `MDS` | Rotate Left Doubleword then Clear Right | `rldcrx` |
| [`rldiclx`](rldiclx.md) | `MD` | Rotate Left Doubleword Immediate then Clear Left | `rldiclx` |
| [`rldicrx`](rldicrx.md) | `MD` | Rotate Left Doubleword Immediate then Clear Right | `rldicrx` |
| [`rldicx`](rldicx.md) | `MD` | Rotate Left Doubleword Immediate then Clear | `rldicx` |
| [`rldimix`](rldimix.md) | `MD` | Rotate Left Doubleword Immediate then Mask Insert | `rldimix` |
| [`rlwimix`](rlwimix.md) | `M` | Rotate Left Word Immediate then Mask Insert | `rlwimix` |
| [`rlwinmx`](rlwinmx.md) | `M` | Rotate Left Word Immediate then AND with Mask | `rlwinmx` |
| [`rlwnmx`](rlwnmx.md) | `M` | Rotate Left Word then AND with Mask | `rlwnmx` |
| [`sldx`](sldx.md) | `X` | Shift Left Doubleword | `sldx` |
| [`slwx`](slwx.md) | `X` | Shift Left Word | `slwx` |
| [`sradix`](sradix.md) | `XS` | Shift Right Algebraic Doubleword Immediate | `sradix` |
| [`sradx`](sradx.md) | `X` | Shift Right Algebraic Doubleword | `sradx` |
| [`srawix`](srawix.md) | `X` | Shift Right Algebraic Word Immediate | `srawix` |
| [`srawx`](srawx.md) | `X` | Shift Right Algebraic Word | `srawx` |
| [`srdx`](srdx.md) | `X` | Shift Right Doubleword | `srdx` |
| [`srwx`](srwx.md) | `X` | Shift Right Word | `srwx` |
| [`subfcx`](subfcx.md) | `XO` | Subtract From Carrying | `subfcx` |
| [`subfex`](subfex.md) | `XO` | Subtract From Extended | `subfex` |
| [`subficx`](subficx.md) | `D` | Subtract From Immediate Carrying | `subficx` |
| [`subfmex`](subfmex.md) | `XO` | Subtract From Minus One Extended | `subfmex` |
| [`subfx`](subfx.md) | `XO` | Subtract From | `subfx` |
| [`subfzex`](subfzex.md) | `XO` | Subtract From Zero Extended | `subfzex` |
| [`sync`](sync.md) | `X` | Synchronize | `sync` |
| [`xori`](xori.md) | `D` | XOR Immediate | `xori` |
| [`xoris`](xoris.md) | `D` | XOR Immediate Shifted | `xoris` |
| [`xorx`](xorx.md) | `X` | XOR | `xorx` |
<!-- GENERATED: END -->

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# Branch & System
Unconditional / conditional branches, branch to LR/CTR, traps, system call.
**9 families** · **9 XML entries**.
<!-- GENERATED: BEGIN -->
| Family | Form | Description | Members |
| --- | --- | --- | --- |
| [`bcctrx`](bcctrx.md) | `XL` | Branch Conditional to Count Register | `bcctrx` |
| [`bclrx`](bclrx.md) | `XL` | Branch Conditional to Link Register | `bclrx` |
| [`bcx`](bcx.md) | `B` | Branch Conditional | `bcx` |
| [`bx`](bx.md) | `I` | Branch | `bx` |
| [`sc`](sc.md) | `SC` | System Call | `sc` |
| [`td`](td.md) | `X` | Trap Doubleword | `td` |
| [`tdi`](tdi.md) | `D` | Trap Doubleword Immediate | `tdi` |
| [`tw`](tw.md) | `X` | Trap Word | `tw` |
| [`twi`](twi.md) | `D` | Trap Word Immediate | `twi` |
<!-- GENERATED: END -->

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# Control / CR / SPR
Condition-register logical ops, CR field moves, mfspr/mtspr/mtcrf, time-base reads, synchronisation (sync, isync, eieio).
**26 families** · **26 XML entries**.
<!-- GENERATED: BEGIN -->
| Family | Form | Description | Members |
| --- | --- | --- | --- |
| [`crand`](crand.md) | `XL` | Condition Register AND | `crand` |
| [`crandc`](crandc.md) | `XL` | Condition Register AND with Complement | `crandc` |
| [`creqv`](creqv.md) | `XL` | Condition Register Equivalent | `creqv` |
| [`crnand`](crnand.md) | `XL` | Condition Register NAND | `crnand` |
| [`crnor`](crnor.md) | `XL` | Condition Register NOR | `crnor` |
| [`cror`](cror.md) | `XL` | Condition Register OR | `cror` |
| [`crorc`](crorc.md) | `XL` | Condition Register OR with Complement | `crorc` |
| [`crxor`](crxor.md) | `XL` | Condition Register XOR | `crxor` |
| [`mcrf`](mcrf.md) | `XL` | Move Condition Register Field | `mcrf` |
| [`mcrfs`](mcrfs.md) | `X` | Move to Condition Register from FPSCR | `mcrfs` |
| [`mcrxr`](mcrxr.md) | `X` | Move to Condition Register from XER | `mcrxr` |
| [`mfcr`](mfcr.md) | `X` | Move from Condition Register | `mfcr` |
| [`mffsx`](mffsx.md) | `X` | Move from FPSCR | `mffsx` |
| [`mfmsr`](mfmsr.md) | `X` | Move from Machine State Register | `mfmsr` |
| [`mfspr`](mfspr.md) | `XFX` | Move from Special-Purpose Register | `mfspr` |
| [`mftb`](mftb.md) | `XFX` | Move from Time Base | `mftb` |
| [`mfvscr`](mfvscr.md) | `VX` | Move from VSCR | `mfvscr` |
| [`mtcrf`](mtcrf.md) | `XFX` | Move to Condition Register Fields | `mtcrf` |
| [`mtfsb0x`](mtfsb0x.md) | `X` | Move to FPSCR Bit 0 | `mtfsb0x` |
| [`mtfsb1x`](mtfsb1x.md) | `X` | Move to FPSCR Bit 1 | `mtfsb1x` |
| [`mtfsfix`](mtfsfix.md) | `X` | Move to FPSCR Field Immediate | `mtfsfix` |
| [`mtfsfx`](mtfsfx.md) | `XFL` | Move to FPSCR Fields | `mtfsfx` |
| [`mtmsr`](mtmsr.md) | `X` | Move to Machine State Register | `mtmsr` |
| [`mtmsrd`](mtmsrd.md) | `X` | Move to Machine State Register Doubleword | `mtmsrd` |
| [`mtspr`](mtspr.md) | `XFX` | Move to Special-Purpose Register | `mtspr` |
| [`mtvscr`](mtvscr.md) | `VX` | Move to VSCR | `mtvscr` |
<!-- GENERATED: END -->

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# Floating-Point
IEEE-754 add/sub/mul/div/sqrt, fused multiply-add, conversions, compares, FPSCR moves.
**33 families** · **33 XML entries**.
<!-- GENERATED: BEGIN -->
| Family | Form | Description | Members |
| --- | --- | --- | --- |
| [`fabsx`](fabsx.md) | `X` | Floating Absolute Value | `fabsx` |
| [`faddsx`](faddsx.md) | `A` | Floating Add Single | `faddsx` |
| [`faddx`](faddx.md) | `A` | Floating Add | `faddx` |
| [`fcfidx`](fcfidx.md) | `X` | Floating Convert From Integer Doubleword | `fcfidx` |
| [`fcmpo`](fcmpo.md) | `X` | Floating Compare Ordered | `fcmpo` |
| [`fcmpu`](fcmpu.md) | `X` | Floating Compare Unordered | `fcmpu` |
| [`fctidx`](fctidx.md) | `X` | Floating Convert to Integer Doubleword | `fctidx` |
| [`fctidzx`](fctidzx.md) | `X` | Floating Convert to Integer Doubleword with Round Toward Zero | `fctidzx` |
| [`fctiwx`](fctiwx.md) | `X` | Floating Convert to Integer Word | `fctiwx` |
| [`fctiwzx`](fctiwzx.md) | `X` | Floating Convert to Integer Word with Round Toward Zero | `fctiwzx` |
| [`fdivsx`](fdivsx.md) | `A` | Floating Divide Single | `fdivsx` |
| [`fdivx`](fdivx.md) | `A` | Floating Divide | `fdivx` |
| [`fmaddsx`](fmaddsx.md) | `A` | Floating Multiply-Add Single | `fmaddsx` |
| [`fmaddx`](fmaddx.md) | `A` | Floating Multiply-Add | `fmaddx` |
| [`fmrx`](fmrx.md) | `X` | Floating Move Register | `fmrx` |
| [`fmsubsx`](fmsubsx.md) | `A` | Floating Multiply-Subtract Single | `fmsubsx` |
| [`fmsubx`](fmsubx.md) | `A` | Floating Multiply-Subtract | `fmsubx` |
| [`fmulsx`](fmulsx.md) | `A` | Floating Multiply Single | `fmulsx` |
| [`fmulx`](fmulx.md) | `A` | Floating Multiply | `fmulx` |
| [`fnabsx`](fnabsx.md) | `X` | Floating Negative Absolute Value | `fnabsx` |
| [`fnegx`](fnegx.md) | `X` | Floating Negate | `fnegx` |
| [`fnmaddsx`](fnmaddsx.md) | `A` | Floating Negative Multiply-Add Single | `fnmaddsx` |
| [`fnmaddx`](fnmaddx.md) | `A` | Floating Negative Multiply-Add | `fnmaddx` |
| [`fnmsubsx`](fnmsubsx.md) | `A` | Floating Negative Multiply-Subtract Single | `fnmsubsx` |
| [`fnmsubx`](fnmsubx.md) | `A` | Floating Negative Multiply-Subtract | `fnmsubx` |
| [`fresx`](fresx.md) | `A` | Floating Reciprocal Estimate Single | `fresx` |
| [`frspx`](frspx.md) | `X` | Floating Round to Single | `frspx` |
| [`frsqrtex`](frsqrtex.md) | `A` | Floating Reciprocal Square Root Estimate | `frsqrtex` |
| [`fselx`](fselx.md) | `A` | Floating Select | `fselx` |
| [`fsqrtsx`](fsqrtsx.md) | `A` | Floating Square Root Single | `fsqrtsx` |
| [`fsqrtx`](fsqrtx.md) | `A` | Floating Square Root | `fsqrtx` |
| [`fsubsx`](fsubsx.md) | `A` | Floating Subtract Single | `fsubsx` |
| [`fsubx`](fsubx.md) | `A` | Floating Subtract | `fsubx` |
<!-- GENERATED: END -->

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# Memory
Loads/stores for byte, half, word, doubleword, float, multiple and string; cache management (dcbt, dcbf, dcbz); reservation pair lwarx/stwcx.
**56 families** · **112 XML entries**.
<!-- GENERATED: BEGIN -->
| Family | Form | Description | Members |
| --- | --- | --- | --- |
| [`dcbf`](dcbf.md) | `X` | Data Cache Block Flush | `dcbf` |
| [`dcbi`](dcbi.md) | `X` | Data Cache Block Invalidate | `dcbi` |
| [`dcbst`](dcbst.md) | `X` | Data Cache Block Store | `dcbst` |
| [`dcbt`](dcbt.md) | `X` | Data Cache Block Touch | `dcbt` |
| [`dcbtst`](dcbtst.md) | `X` | Data Cache Block Touch for Store | `dcbtst` |
| [`dcbz`](dcbz.md) | `DCBZ` | Data Cache Block Clear to Zero | `dcbz`, `dcbz128` |
| [`icbi`](icbi.md) | `X` | Instruction Cache Block Invalidate | `icbi` |
| [`lbz`](lbz.md) | `D` | Load Byte and Zero | `lbz`, `lbzu`, `lbzux`, `lbzx` |
| [`ld`](ld.md) | `DS` | Load Doubleword | `ld`, `ldu`, `ldux`, `ldx` |
| [`ldarx`](ldarx.md) | `X` | Load Doubleword and Reserve Indexed | `ldarx` |
| [`ldbrx`](ldbrx.md) | `X` | Load Doubleword Byte-Reverse Indexed | `ldbrx` |
| [`lfd`](lfd.md) | `D` | Load Floating-Point Double | `lfd`, `lfdu`, `lfdux`, `lfdx` |
| [`lfs`](lfs.md) | `D` | Load Floating-Point Single | `lfs`, `lfsu`, `lfsux`, `lfsx` |
| [`lha`](lha.md) | `D` | Load Half Word Algebraic | `lha`, `lhau`, `lhaux`, `lhax` |
| [`lhbrx`](lhbrx.md) | `X` | Load Half Word Byte-Reverse Indexed | `lhbrx` |
| [`lhz`](lhz.md) | `D` | Load Half Word and Zero | `lhz`, `lhzu`, `lhzux`, `lhzx` |
| [`lmw`](lmw.md) | `D` | Load Multiple Word | `lmw` |
| [`lswi`](lswi.md) | `X` | Load String Word Immediate | `lswi` |
| [`lswx`](lswx.md) | `X` | Load String Word Indexed | `lswx` |
| [`lvebx`](lvebx.md) | `X` | Load Vector Element Byte Indexed | `lvebx` |
| [`lvehx`](lvehx.md) | `X` | Load Vector Element Half Word Indexed | `lvehx` |
| [`lvewx`](lvewx.md) | `X` | Load Vector Element Word Indexed | `lvewx`, `lvewx128` |
| [`lvlx`](lvlx.md) | `X` | Load Vector Left Indexed | `lvlx`, `lvlx128` |
| [`lvlxl`](lvlxl.md) | `X` | Load Vector Left Indexed LRU | `lvlxl`, `lvlxl128` |
| [`lvrx`](lvrx.md) | `X` | Load Vector Right Indexed | `lvrx`, `lvrx128` |
| [`lvrxl`](lvrxl.md) | `X` | Load Vector Right Indexed LRU | `lvrxl`, `lvrxl128` |
| [`lvx`](lvx.md) | `X` | Load Vector Indexed | `lvx`, `lvx128` |
| [`lvxl`](lvxl.md) | `X` | Load Vector Indexed LRU | `lvxl`, `lvxl128` |
| [`lwa`](lwa.md) | `DS` | Load Word Algebraic | `lwa`, `lwaux`, `lwax` |
| [`lwarx`](lwarx.md) | `X` | Load Word and Reserve Indexed | `lwarx` |
| [`lwbrx`](lwbrx.md) | `X` | Load Word Byte-Reverse Indexed | `lwbrx` |
| [`lwz`](lwz.md) | `D` | Load Word and Zero | `lwz`, `lwzu`, `lwzux`, `lwzx` |
| [`stb`](stb.md) | `D` | Store Byte | `stb`, `stbu`, `stbux`, `stbx` |
| [`std`](std.md) | `DS` | Store Doubleword | `std`, `stdu`, `stdux`, `stdx` |
| [`stdbrx`](stdbrx.md) | `X` | Store Doubleword Byte-Reverse Indexed | `stdbrx` |
| [`stdcx`](stdcx.md) | `X` | Store Doubleword Conditional Indexed | `stdcx` |
| [`stfd`](stfd.md) | `D` | Store Floating-Point Double | `stfd`, `stfdu`, `stfdux`, `stfdx` |
| [`stfiwx`](stfiwx.md) | `X` | Store Floating-Point as Integer Word Indexed | `stfiwx` |
| [`stfs`](stfs.md) | `D` | Store Floating-Point Single | `stfs`, `stfsu`, `stfsux`, `stfsx` |
| [`sth`](sth.md) | `D` | Store Half Word | `sth`, `sthu`, `sthux`, `sthx` |
| [`sthbrx`](sthbrx.md) | `X` | Store Half Word Byte-Reverse Indexed | `sthbrx` |
| [`stmw`](stmw.md) | `D` | Store Multiple Word | `stmw` |
| [`stswi`](stswi.md) | `X` | Store String Word Immediate | `stswi` |
| [`stswx`](stswx.md) | `X` | Store String Word Indexed | `stswx` |
| [`stvebx`](stvebx.md) | `X` | Store Vector Element Byte Indexed | `stvebx` |
| [`stvehx`](stvehx.md) | `X` | Store Vector Element Half Word Indexed | `stvehx` |
| [`stvewx`](stvewx.md) | `X` | Store Vector Element Word Indexed | `stvewx`, `stvewx128` |
| [`stvlx`](stvlx.md) | `X` | Store Vector Left Indexed | `stvlx`, `stvlx128` |
| [`stvlxl`](stvlxl.md) | `X` | Store Vector Left Indexed LRU | `stvlxl`, `stvlxl128` |
| [`stvrx`](stvrx.md) | `X` | Store Vector Right Indexed | `stvrx`, `stvrx128` |
| [`stvrxl`](stvrxl.md) | `X` | Store Vector Right Indexed LRU | `stvrxl`, `stvrxl128` |
| [`stvx`](stvx.md) | `X` | Store Vector Indexed | `stvx`, `stvx128` |
| [`stvxl`](stvxl.md) | `X` | Store Vector Indexed LRU | `stvxl`, `stvxl128` |
| [`stw`](stw.md) | `D` | Store Word | `stw`, `stwu`, `stwux`, `stwx` |
| [`stwbrx`](stwbrx.md) | `X` | Store Word Byte-Reverse Indexed | `stwbrx` |
| [`stwcx`](stwcx.md) | `X` | Store Word Conditional Indexed | `stwcx` |
<!-- GENERATED: END -->

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# VMX (Altivec)
128-bit SIMD over 32 registers V0–V31. Integer/float arithmetic, logical, compare, permute/merge, pack/unpack, saturation helpers.
**144 families** · **193 XML entries**.
<!-- GENERATED: BEGIN -->
| Family | Form | Description | Members |
| --- | --- | --- | --- |
| [`lvsl`](lvsl.md) | `X` | Load Vector for Shift Left Indexed | `lvsl`, `lvsl128` |
| [`lvsr`](lvsr.md) | `X` | Load Vector for Shift Right Indexed | `lvsr`, `lvsr128` |
| [`vaddcuw`](vaddcuw.md) | `VX` | Vector Add Carryout Unsigned Word | `vaddcuw` |
| [`vaddfp`](vaddfp.md) | `VX` | Vector Add Floating Point | `vaddfp`, `vaddfp128` |
| [`vaddsbs`](vaddsbs.md) | `VX` | Vector Add Signed Byte Saturate | `vaddsbs` |
| [`vaddshs`](vaddshs.md) | `VX` | Vector Add Signed Half Word Saturate | `vaddshs` |
| [`vaddsws`](vaddsws.md) | `VX` | Vector Add Signed Word Saturate | `vaddsws` |
| [`vaddubm`](vaddubm.md) | `VX` | Vector Add Unsigned Byte Modulo | `vaddubm` |
| [`vaddubs`](vaddubs.md) | `VX` | Vector Add Unsigned Byte Saturate | `vaddubs` |
| [`vadduhm`](vadduhm.md) | `VX` | Vector Add Unsigned Half Word Modulo | `vadduhm` |
| [`vadduhs`](vadduhs.md) | `VX` | Vector Add Unsigned Half Word Saturate | `vadduhs` |
| [`vadduwm`](vadduwm.md) | `VX` | Vector Add Unsigned Word Modulo | `vadduwm` |
| [`vadduws`](vadduws.md) | `VX` | Vector Add Unsigned Word Saturate | `vadduws` |
| [`vand`](vand.md) | `VX` | Vector Logical AND | `vand`, `vand128` |
| [`vandc`](vandc.md) | `VX` | Vector Logical AND with Complement | `vandc`, `vandc128` |
| [`vavgsb`](vavgsb.md) | `VX` | Vector Average Signed Byte | `vavgsb` |
| [`vavgsh`](vavgsh.md) | `VX` | Vector Average Signed Half Word | `vavgsh` |
| [`vavgsw`](vavgsw.md) | `VX` | Vector Average Signed Word | `vavgsw` |
| [`vavgub`](vavgub.md) | `VX` | Vector Average Unsigned Byte | `vavgub` |
| [`vavguh`](vavguh.md) | `VX` | Vector Average Unsigned Half Word | `vavguh` |
| [`vavguw`](vavguw.md) | `VX` | Vector Average Unsigned Word | `vavguw` |
| [`vcfsx`](vcfsx.md) | `VX` | Vector Convert from Signed Fixed-Point Word | `vcfsx` |
| [`vcfux`](vcfux.md) | `VX` | Vector Convert from Unsigned Fixed-Point Word | `vcfux` |
| [`vcmpbfp`](vcmpbfp.md) | `VC` | Vector Compare Bounds Floating Point | `vcmpbfp`, `vcmpbfp128` |
| [`vcmpeqfp`](vcmpeqfp.md) | `VC` | Vector Compare Equal-to Floating Point | `vcmpeqfp`, `vcmpeqfp128` |
| [`vcmpequb`](vcmpequb.md) | `VC` | Vector Compare Equal-to Unsigned Byte | `vcmpequb` |
| [`vcmpequh`](vcmpequh.md) | `VC` | Vector Compare Equal-to Unsigned Half Word | `vcmpequh` |
| [`vcmpequw`](vcmpequw.md) | `VC` | Vector Compare Equal-to Unsigned Word | `vcmpequw`, `vcmpequw128` |
| [`vcmpgefp`](vcmpgefp.md) | `VC` | Vector Compare Greater-Than-or-Equal-to Floating Point | `vcmpgefp`, `vcmpgefp128` |
| [`vcmpgtfp`](vcmpgtfp.md) | `VC` | Vector Compare Greater-Than Floating Point | `vcmpgtfp`, `vcmpgtfp128` |
| [`vcmpgtsb`](vcmpgtsb.md) | `VC` | Vector Compare Greater-Than Signed Byte | `vcmpgtsb` |
| [`vcmpgtsh`](vcmpgtsh.md) | `VC` | Vector Compare Greater-Than Signed Half Word | `vcmpgtsh` |
| [`vcmpgtsw`](vcmpgtsw.md) | `VC` | Vector Compare Greater-Than Signed Word | `vcmpgtsw` |
| [`vcmpgtub`](vcmpgtub.md) | `VC` | Vector Compare Greater-Than Unsigned Byte | `vcmpgtub` |
| [`vcmpgtuh`](vcmpgtuh.md) | `VC` | Vector Compare Greater-Than Unsigned Half Word | `vcmpgtuh` |
| [`vcmpgtuw`](vcmpgtuw.md) | `VC` | Vector Compare Greater-Than Unsigned Word | `vcmpgtuw` |
| [`vctsxs`](vctsxs.md) | `VX` | Vector Convert to Signed Fixed-Point Word Saturate | `vctsxs` |
| [`vctuxs`](vctuxs.md) | `VX` | Vector Convert to Unsigned Fixed-Point Word Saturate | `vctuxs` |
| [`vexptefp`](vexptefp.md) | `VX` | Vector 2 Raised to the Exponent Estimate Floating Point | `vexptefp`, `vexptefp128` |
| [`vlogefp`](vlogefp.md) | `VX` | Vector Log2 Estimate Floating Point | `vlogefp`, `vlogefp128` |
| [`vmaddfp`](vmaddfp.md) | `VA` | Vector Multiply-Add Floating Point | `vmaddfp`, `vmaddfp128` |
| [`vmaxfp`](vmaxfp.md) | `VX` | Vector Maximum Floating Point | `vmaxfp`, `vmaxfp128` |
| [`vmaxsb`](vmaxsb.md) | `VX` | Vector Maximum Signed Byte | `vmaxsb` |
| [`vmaxsh`](vmaxsh.md) | `VX` | Vector Maximum Signed Half Word | `vmaxsh` |
| [`vmaxsw`](vmaxsw.md) | `VX` | Vector Maximum Signed Word | `vmaxsw` |
| [`vmaxub`](vmaxub.md) | `VX` | Vector Maximum Unsigned Byte | `vmaxub` |
| [`vmaxuh`](vmaxuh.md) | `VX` | Vector Maximum Unsigned Half Word | `vmaxuh` |
| [`vmaxuw`](vmaxuw.md) | `VX` | Vector Maximum Unsigned Word | `vmaxuw` |
| [`vmhaddshs`](vmhaddshs.md) | `VA` | Vector Multiply-High and Add Signed Signed Half Word Saturate | `vmhaddshs` |
| [`vmhraddshs`](vmhraddshs.md) | `VA` | Vector Multiply-High Round and Add Signed Signed Half Word Saturate | `vmhraddshs` |
| [`vminfp`](vminfp.md) | `VX` | Vector Minimum Floating Point | `vminfp`, `vminfp128` |
| [`vminsb`](vminsb.md) | `VX` | Vector Minimum Signed Byte | `vminsb` |
| [`vminsh`](vminsh.md) | `VX` | Vector Minimum Signed Half Word | `vminsh` |
| [`vminsw`](vminsw.md) | `VX` | Vector Minimum Signed Word | `vminsw` |
| [`vminub`](vminub.md) | `VX` | Vector Minimum Unsigned Byte | `vminub` |
| [`vminuh`](vminuh.md) | `VX` | Vector Minimum Unsigned Half Word | `vminuh` |
| [`vminuw`](vminuw.md) | `VX` | Vector Minimum Unsigned Word | `vminuw` |
| [`vmladduhm`](vmladduhm.md) | `VA` | Vector Multiply-Low and Add Unsigned Half Word Modulo | `vmladduhm` |
| [`vmrghb`](vmrghb.md) | `VX` | Vector Merge High Byte | `vmrghb` |
| [`vmrghh`](vmrghh.md) | `VX` | Vector Merge High Half Word | `vmrghh` |
| [`vmrghw`](vmrghw.md) | `VX` | Vector Merge High Word | `vmrghw`, `vmrghw128` |
| [`vmrglb`](vmrglb.md) | `VX` | Vector Merge Low Byte | `vmrglb` |
| [`vmrglh`](vmrglh.md) | `VX` | Vector Merge Low Half Word | `vmrglh` |
| [`vmrglw`](vmrglw.md) | `VX` | Vector Merge Low Word | `vmrglw`, `vmrglw128` |
| [`vmsummbm`](vmsummbm.md) | `VA` | Vector Multiply-Sum Mixed-Sign Byte Modulo | `vmsummbm` |
| [`vmsumshm`](vmsumshm.md) | `VA` | Vector Multiply-Sum Signed Half Word Modulo | `vmsumshm` |
| [`vmsumshs`](vmsumshs.md) | `VA` | Vector Multiply-Sum Signed Half Word Saturate | `vmsumshs` |
| [`vmsumubm`](vmsumubm.md) | `VA` | Vector Multiply-Sum Unsigned Byte Modulo | `vmsumubm` |
| [`vmsumuhm`](vmsumuhm.md) | `VA` | Vector Multiply-Sum Unsigned Half Word Modulo | `vmsumuhm` |
| [`vmsumuhs`](vmsumuhs.md) | `VA` | Vector Multiply-Sum Unsigned Half Word Saturate | `vmsumuhs` |
| [`vmulesb`](vmulesb.md) | `VX` | Vector Multiply Even Signed Byte | `vmulesb` |
| [`vmulesh`](vmulesh.md) | `VX` | Vector Multiply Even Signed Half Word | `vmulesh` |
| [`vmuleub`](vmuleub.md) | `VX` | Vector Multiply Even Unsigned Byte | `vmuleub` |
| [`vmuleuh`](vmuleuh.md) | `VX` | Vector Multiply Even Unsigned Half Word | `vmuleuh` |
| [`vmulosb`](vmulosb.md) | `VX` | Vector Multiply Odd Signed Byte | `vmulosb` |
| [`vmulosh`](vmulosh.md) | `VX` | Vector Multiply Odd Signed Half Word | `vmulosh` |
| [`vmuloub`](vmuloub.md) | `VX` | Vector Multiply Odd Unsigned Byte | `vmuloub` |
| [`vmulouh`](vmulouh.md) | `VX` | Vector Multiply Odd Unsigned Half Word | `vmulouh` |
| [`vnmsubfp`](vnmsubfp.md) | `VA` | Vector Negative Multiply-Subtract Floating Point | `vnmsubfp`, `vnmsubfp128` |
| [`vnor`](vnor.md) | `VX` | Vector Logical NOR | `vnor`, `vnor128` |
| [`vor`](vor.md) | `VX` | Vector Logical OR | `vor`, `vor128` |
| [`vperm`](vperm.md) | `VA` | Vector Permute | `vperm`, `vperm128` |
| [`vpkpx`](vpkpx.md) | `VX` | Vector Pack Pixel | `vpkpx` |
| [`vpkshss`](vpkshss.md) | `VX` | Vector Pack Signed Half Word Signed Saturate | `vpkshss`, `vpkshss128` |
| [`vpkshus`](vpkshus.md) | `VX` | Vector Pack Signed Half Word Unsigned Saturate | `vpkshus`, `vpkshus128` |
| [`vpkswss`](vpkswss.md) | `VX` | Vector Pack Signed Word Signed Saturate | `vpkswss`, `vpkswss128` |
| [`vpkswus`](vpkswus.md) | `VX` | Vector Pack Signed Word Unsigned Saturate | `vpkswus`, `vpkswus128` |
| [`vpkuhum`](vpkuhum.md) | `VX` | Vector Pack Unsigned Half Word Unsigned Modulo | `vpkuhum`, `vpkuhum128` |
| [`vpkuhus`](vpkuhus.md) | `VX` | Vector Pack Unsigned Half Word Unsigned Saturate | `vpkuhus`, `vpkuhus128` |
| [`vpkuwum`](vpkuwum.md) | `VX` | Vector Pack Unsigned Word Unsigned Modulo | `vpkuwum`, `vpkuwum128` |
| [`vpkuwus`](vpkuwus.md) | `VX` | Vector Pack Unsigned Word Unsigned Saturate | `vpkuwus`, `vpkuwus128` |
| [`vrefp`](vrefp.md) | `VX` | Vector Reciprocal Estimate Floating Point | `vrefp`, `vrefp128` |
| [`vrfim`](vrfim.md) | `VX` | Vector Round to Floating-Point Integer toward -Infinity | `vrfim`, `vrfim128` |
| [`vrfin`](vrfin.md) | `VX` | Vector Round to Floating-Point Integer Nearest | `vrfin`, `vrfin128` |
| [`vrfip`](vrfip.md) | `VX` | Vector Round to Floating-Point Integer toward +Infinity | `vrfip`, `vrfip128` |
| [`vrfiz`](vrfiz.md) | `VX` | Vector Round to Floating-Point Integer toward Zero | `vrfiz`, `vrfiz128` |
| [`vrlb`](vrlb.md) | `VX` | Vector Rotate Left Integer Byte | `vrlb` |
| [`vrlh`](vrlh.md) | `VX` | Vector Rotate Left Integer Half Word | `vrlh` |
| [`vrlw`](vrlw.md) | `VX` | Vector Rotate Left Integer Word | `vrlw`, `vrlw128` |
| [`vrsqrtefp`](vrsqrtefp.md) | `VX` | Vector Reciprocal Square Root Estimate Floating Point | `vrsqrtefp`, `vrsqrtefp128` |
| [`vsel`](vsel.md) | `VA` | Vector Conditional Select | `vsel`, `vsel128` |
| [`vsl`](vsl.md) | `VX` | Vector Shift Left | `vsl` |
| [`vslb`](vslb.md) | `VX` | Vector Shift Left Integer Byte | `vslb` |
| [`vsldoi`](vsldoi.md) | `VA` | Vector Shift Left Double by Octet Immediate | `vsldoi`, `vsldoi128` |
| [`vslh`](vslh.md) | `VX` | Vector Shift Left Integer Half Word | `vslh` |
| [`vslo`](vslo.md) | `VX` | Vector Shift Left by Octet | `vslo`, `vslo128` |
| [`vslw`](vslw.md) | `VX` | Vector Shift Left Integer Word | `vslw`, `vslw128` |
| [`vspltb`](vspltb.md) | `VX` | Vector Splat Byte | `vspltb` |
| [`vsplth`](vsplth.md) | `VX` | Vector Splat Half Word | `vsplth` |
| [`vspltisb`](vspltisb.md) | `VX` | Vector Splat Immediate Signed Byte | `vspltisb` |
| [`vspltish`](vspltish.md) | `VX` | Vector Splat Immediate Signed Half Word | `vspltish` |
| [`vspltisw`](vspltisw.md) | `VX` | Vector Splat Immediate Signed Word | `vspltisw`, `vspltisw128` |
| [`vspltw`](vspltw.md) | `VX` | Vector Splat Word | `vspltw`, `vspltw128` |
| [`vsr`](vsr.md) | `VX` | Vector Shift Right | `vsr` |
| [`vsrab`](vsrab.md) | `VX` | Vector Shift Right Algebraic Byte | `vsrab` |
| [`vsrah`](vsrah.md) | `VX` | Vector Shift Right Algebraic Half Word | `vsrah` |
| [`vsraw`](vsraw.md) | `VX` | Vector Shift Right Algebraic Word | `vsraw`, `vsraw128` |
| [`vsrb`](vsrb.md) | `VX` | Vector Shift Right Byte | `vsrb` |
| [`vsrh`](vsrh.md) | `VX` | Vector Shift Right Half Word | `vsrh` |
| [`vsro`](vsro.md) | `VX` | Vector Shift Right Octet | `vsro`, `vsro128` |
| [`vsrw`](vsrw.md) | `VX` | Vector Shift Right Word | `vsrw`, `vsrw128` |
| [`vsubcuw`](vsubcuw.md) | `VX` | Vector Subtract Carryout Unsigned Word | `vsubcuw` |
| [`vsubfp`](vsubfp.md) | `VX` | Vector Subtract Floating Point | `vsubfp`, `vsubfp128` |
| [`vsubsbs`](vsubsbs.md) | `VX` | Vector Subtract Signed Byte Saturate | `vsubsbs` |
| [`vsubshs`](vsubshs.md) | `VX` | Vector Subtract Signed Half Word Saturate | `vsubshs` |
| [`vsubsws`](vsubsws.md) | `VX` | Vector Subtract Signed Word Saturate | `vsubsws` |
| [`vsububm`](vsububm.md) | `VX` | Vector Subtract Unsigned Byte Modulo | `vsububm` |
| [`vsububs`](vsububs.md) | `VX` | Vector Subtract Unsigned Byte Saturate | `vsububs` |
| [`vsubuhm`](vsubuhm.md) | `VX` | Vector Subtract Unsigned Half Word Modulo | `vsubuhm` |
| [`vsubuhs`](vsubuhs.md) | `VX` | Vector Subtract Unsigned Half Word Saturate | `vsubuhs` |
| [`vsubuwm`](vsubuwm.md) | `VX` | Vector Subtract Unsigned Word Modulo | `vsubuwm` |
| [`vsubuws`](vsubuws.md) | `VX` | Vector Subtract Unsigned Word Saturate | `vsubuws` |
| [`vsum2sws`](vsum2sws.md) | `VX` | Vector Sum Across Partial (1/2) Signed Word Saturate | `vsum2sws` |
| [`vsum4sbs`](vsum4sbs.md) | `VX` | Vector Sum Across Partial (1/4) Signed Byte Saturate | `vsum4sbs` |
| [`vsum4shs`](vsum4shs.md) | `VX` | Vector Sum Across Partial (1/4) Signed Half Word Saturate | `vsum4shs` |
| [`vsum4ubs`](vsum4ubs.md) | `VX` | Vector Sum Across Partial (1/4) Unsigned Byte Saturate | `vsum4ubs` |
| [`vsumsws`](vsumsws.md) | `VX` | Vector Sum Across Signed Word Saturate | `vsumsws` |
| [`vupkhpx`](vupkhpx.md) | `VX` | Vector Unpack High Pixel | `vupkhpx` |
| [`vupkhsb`](vupkhsb.md) | `VX` | Vector Unpack High Signed Byte | `vupkhsb`, `vupkhsb128` |
| [`vupkhsh`](vupkhsh.md) | `VX` | Vector Unpack High Signed Half Word | `vupkhsh` |
| [`vupklpx`](vupklpx.md) | `VX` | Vector Unpack Low Pixel | `vupklpx` |
| [`vupklsb`](vupklsb.md) | `VX` | Vector Unpack Low Signed Byte | `vupklsb`, `vupklsb128` |
| [`vupklsh`](vupklsh.md) | `VX` | Vector Unpack Low Signed Half Word | `vupklsh` |
| [`vxor`](vxor.md) | `VX` | Vector Logical XOR | `vxor`, `vxor128` |
<!-- GENERATED: END -->

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# VMX128
Xbox-360-specific Altivec extension that widens the vector register file to 128 registers (V0–V127). Register IDs are encoded with bit-fusion across non-contiguous fields.
**12 families** · **12 XML entries**.
<!-- GENERATED: BEGIN -->
| Family | Form | Description | Members |
| --- | --- | --- | --- |
| [`vcfpsxws128`](vcfpsxws128.md) | `VX128_3` | Vector128 Convert From Floating-Point to Signed Fixed-Point Word Saturate | `vcfpsxws128` |
| [`vcfpuxws128`](vcfpuxws128.md) | `VX128_3` | Vector128 Convert From Floating-Point to Unsigned Fixed-Point Word Saturate | `vcfpuxws128` |
| [`vcsxwfp128`](vcsxwfp128.md) | `VX128_3` | Vector128 Convert From Signed Fixed-Point Word to Floating-Point | `vcsxwfp128` |
| [`vcuxwfp128`](vcuxwfp128.md) | `VX128_3` | Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point | `vcuxwfp128` |
| [`vmaddcfp128`](vmaddcfp128.md) | `VX128` | Vector128 Multiply Add Floating Point | `vmaddcfp128` |
| [`vmsum3fp128`](vmsum3fp128.md) | `VX128` | Vector128 Multiply Sum 3-way Floating Point | `vmsum3fp128` |
| [`vmsum4fp128`](vmsum4fp128.md) | `VX128` | Vector128 Multiply Sum 4-way Floating-Point | `vmsum4fp128` |
| [`vmulfp128`](vmulfp128.md) | `VX128` | Vector128 Multiply Floating-Point | `vmulfp128` |
| [`vpermwi128`](vpermwi128.md) | `VX128_P` | Vector128 Permutate Word Immediate | `vpermwi128` |
| [`vpkd3d128`](vpkd3d128.md) | `VX128_4` | Vector128 Pack D3Dtype, Rotate Left Immediate and Mask Insert | `vpkd3d128` |
| [`vrlimi128`](vrlimi128.md) | `VX128_4` | Vector128 Rotate Left Immediate and Mask Insert | `vrlimi128` |
| [`vupkd3d128`](vupkd3d128.md) | `VX128_3` | Vector128 Unpack D3Dtype | `vupkd3d128` |
<!-- GENERATED: END -->