chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
155
migration/project-root/ppc-manual/control/mcrfs.md
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migration/project-root/ppc-manual/control/mcrfs.md
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# `mcrfs` — Move to Condition Register from FPSCR
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> **Category:** [Control / CR / SPR](../categories/control.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0xfc000080`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `mcrfs` | `mcrfs` | — | Move to Condition Register from FPSCR |
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## Syntax
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```asm
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mcrfs [CRFD], [CRFS]
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```
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## Encoding
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### `mcrfs` — form `X`
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- **Opcode word:** `0xfc000080`
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- **Primary opcode (bits 0–5):** `63`
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- **Extended opcode:** `64`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode |
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| 6–10 | `RT/FRT/VRT` | destination |
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| 11–15 | `RA/FRA/VRA` | source A |
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| 16–20 | `RB/FRB/VRB` | source B |
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| 21–30 | `XO` | extended opcode (10 bits) |
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| 31 | `Rc` | record-form flag |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `CRFS` | mcrfs: read | CR source field. |
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| `FPSCR` | mcrfs: read; mcrfs: write | Floating-Point Status and Control Register. |
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| `CRFD` | mcrfs: write | CR destination field (`crf`, 0–7). |
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## Register Effects
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### `mcrfs`
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- **Reads (always):** `CRFS`, `FPSCR`
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- **Reads (conditional):** _none_
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- **Writes (always):** `CRFD`, `FPSCR`
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- **Writes (conditional):** _none_
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## Status-Register Effects
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- `mcrfs`: **FPSCR** updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`mcrfs`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="mcrfs"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:371`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L371)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:51`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L51)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:904`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L904)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:4716-4745`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L4716-L4745)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::mcrfs => {
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let crfd = instr.crfd();
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let crfs = instr.crfs();
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let shift = 28 - (crfs as u32 * 4);
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let nibble = ((ctx.fpscr >> shift) & 0xF) as u8;
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ctx.cr[crfd] = crate::context::CrField::from_u8(nibble);
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// Clearable exception bits: 0 (FX), 3 (OX), 4 (UX), 5 (ZX),
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// 6 (XX), 7 (VXSNAN), 8 (VXISI), 9 (VXIDI), 10 (VXZDZ),
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// 11 (VXIMZ), 12 (VXVC), 21 (VXSOFT), 22 (VXSQRT), 23 (VXCVI).
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// (Bit positions are PowerISA MSB-0; here 'FPSCR bit n' means
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// the bit at (31-n) in our little-endian u32.)
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const CLEARABLE_MASK: u32 =
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(1 << 31) | (1 << (31 - 3)) | (1 << (31 - 4)) |
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(1 << (31 - 5)) | (1 << (31 - 6)) | (1 << (31 - 7)) |
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(1 << (31 - 8)) | (1 << (31 - 9)) | (1 << (31 - 10)) |
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(1 << (31 - 11)) | (1 << (31 - 12)) |
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(1 << (31 - 21)) | (1 << (31 - 22)) | (1 << (31 - 23));
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let nibble_mask = 0xFu32 << shift;
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ctx.fpscr &= !(nibble_mask & CLEARABLE_MASK);
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// PPCBUG-068: recompute the VX summary bit. If any VX* exception
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// bit remains set, VX must remain set; if all are cleared, VX
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// must clear. (FEX recomputation omitted — xenia doesn't model
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// enabled-exception dispatch.)
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if ctx.fpscr & fpscr::VX_ALL != 0 {
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ctx.fpscr |= fpscr::VX;
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} else {
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ctx.fpscr &= !fpscr::VX;
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}
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Operation.** Copies one 4-bit FPSCR field into the chosen CR field, then **clears the source FPSCR exception-status bits** (sticky-bit reset). The non-exception status bits (FPRF, etc.) are *not* cleared.
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- **Bits cleared in FPSCR.** The architectural rule is: any bit in the source FPSCR field that is one of {FX, OX, UX, ZX, XX, VXSNAN, VXISI, VXIDI, VXZDZ, VXIMZ, VXVC, VXSOFT, VXSQRT, VXCVI} is reset to 0 after the copy. FEX and VX (summary bits) are subsequently re-derived. Many other FPSCR bits (rounding mode, FPRF, FR/FI) are not affected — even if they fall in `CRFS`.
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- **CR field destination.** `CRFD` is a 3-bit field index (0..7); the four bits land in their natural positions (LT, GT, EQ, SO) of the chosen CR field. After `mcrfs`, `crf` can be tested with the usual conditional branches.
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- **Use case.** Inspect a particular FPSCR exception group, then act on it with a `bc` — e.g. test FPSCR[24..27] (the FI / FR / VXSNAN / VXISI cluster) and branch.
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- **Privilege.** Non-privileged on the Xenon — application-visible.
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- **xenia status.** Decoded (decoder slot 727), but the interpreter does **not** ship a body in the snapshot on this page — `mcrfs` is rare in title code. xenia's FPSCR model is incomplete (most exception bits are stubbed), so even when implemented, the cleared bits typically have no observable effect.
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- **No `Rc`.** X-form, but the `Rc` bit position is unused (reserved 0).
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## Related Instructions
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- [`mffsx`](mffsx.md) — read entire FPSCR into an FPR.
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- [`mtfsfx`](mtfsfx.md), [`mtfsb0x`](mtfsb0x.md), [`mtfsb1x`](mtfsb1x.md), [`mtfsfix`](mtfsfix.md) — write FPSCR bits/fields.
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- [`mcrf`](mcrf.md) — copy a CR field to another CR field.
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- [`mcrxr`](mcrxr.md) — analogous copy from XER (also clears).
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`mcrfs` has no simplified mnemonics.
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## IBM Reference
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- [AIX 7.3 — `mcrfs` (Move to Condition Register from FPSCR)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-mcrfs-move-condition-register-from-fpscr-instruction)
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- PowerISA v2.07B, Book I §4.6 — FPSCR layout (sticky exception bits and which clear semantics apply).
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