chore: add migration/ bundle for cross-machine setup

Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:

  - claude-memory/             ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
                               (103 files, 1.1 MB - MEMORY.md + every
                                project_xenia_rs_*.md from audits
                                addis_signext through audit-058)
  - project-root/dot-claude/   <project-root>/.claude/settings.json
                               (Stop hook + permissions)
  - project-root/ppc-manual/   <project-root>/ppc-manual/
                               (PowerPC reference docs, 397 files, 3.7 MB)
  - project-root/run-canary.sh <project-root>/run-canary.sh
  - README.md                  Human-readable setup checklist
  - setup.sh                   Idempotent installer (also reclones
                               xenia-canary at pinned HEAD 6de80dffe)
  - MANIFEST.md                Per-file mapping + per-file-not-bundled
                               restoration recipe

Excluded from bundle (not shippable via git):
  - Sylpheed ISO (7.8 GB; copyright; manual copy required)
  - sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
  - target/ build artifacts (rebuild on target)
  - audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
  - audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
  - xenia-canary checkout (setup.sh reclones from
    git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

migration/project-root/ppc-manual/control/mtspr.md

@@ -0,0 +1,161 @@
+# `mtspr` — Move to Special-Purpose Register
+
+> **Category:** [Control / CR / SPR](../categories/control.md) · **Form:** [XFX](../forms/XFX.md) · **Opcode:** `0x7c0003a6`
+
+<!-- GENERATED: BEGIN -->
+
+## Assembler Mnemonics
+
+| Mnemonic | XML entry | Flags | Description |
+| --- | --- | --- | --- |
+| `mtspr` | `mtspr` | — | Move to Special-Purpose Register |
+
+## Syntax
+
+```asm
+mtspr [SPR], [RS]
+```
+
+## Encoding
+
+### `mtspr` — form `XFX`
+
+- **Opcode word:** `0x7c0003a6`
+- **Primary opcode (bits 0–5):** `31`
+- **Extended opcode:** `467`
+- **Synchronising:** no
+
+| Bits | Field | Meaning |
+| --- | --- | --- |
+| 0–5 | `OPCD` | primary opcode (31) |
+| 6–10 | `RT` | destination / source GPR |
+| 11–20 | `spr/tbr/FXM` | SPR/TBR number (byte-swapped halves) or CR field mask |
+| 21–30 | `XO` | extended opcode |
+| 31 | `—` | reserved |
+
+## Operands
+
+| Field | Role | Description |
+| --- | --- | --- |
+| `RS` | mtspr: read | Source GPR (alias for RD in some stores). |
+| `SPR` | mtspr: write | Special-Purpose-Register number. Encoded with the two 5-bit halves swapped (bits 11-15 become the high half, bits 16-20 the low half). |
+
+## Register Effects
+
+### `mtspr`
+
+- **Reads (always):** `RS`
+- **Reads (conditional):** _none_
+- **Writes (always):** `SPR`
+- **Writes (conditional):** _none_
+
+## Status-Register Effects
+
+_No condition-register or status-register effects._
+
+## Operation (pseudocode)
+
+```
+n <- spr_number(SPR)
+SPR(n) <- (RS)
+```
+
+## C Translation Example
+
+```c
+/* C translation: the xenia-rs interpreter arm below in           */
+/* Implementation References is the authoritative semantic        */
+/* snapshot. Translate it line-by-line:                            */
+/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
+/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
+/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
+/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
+/* The Register Effects and Status-Register Effects tables above  */
+/* enumerate every side effect a faithful translation must emit.  */
+```
+
+## Implementation References
+
+**`mtspr`**
+- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="mtspr"`](../../xenia-canary/tools/ppc-instructions.xml)
+- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_control.cc:771`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_control.cc#L771)
+- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:55`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L55)
+- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:810`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L810)
+- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:1596-1626`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L1596-L1626)
+<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
+
+```rust
+        PpcOpcode::mtspr => {
+            let spr = instr.spr();
+            let val = ctx.gpr[instr.rs()];
+            match spr {
+                crate::context::spr::XER => ctx.set_xer(val as u32),
+                crate::context::spr::LR => ctx.lr = val,
+                crate::context::spr::CTR => ctx.ctr = val as u32 as u64,
+                crate::context::spr::DEC => ctx.dec = val as u32,
+                crate::context::spr::TBL_WRITE => {
+                    ctx.timebase = (ctx.timebase & 0xFFFF_FFFF_0000_0000) | (val & 0xFFFF_FFFF);
+                }
+                crate::context::spr::TBU_WRITE => {
+                    ctx.timebase = (ctx.timebase & 0x0000_0000_FFFF_FFFF) | ((val & 0xFFFF_FFFF) << 32);
+                }
+                crate::context::spr::VRSAVE => ctx.vrsave = val as u32,
+                // Benign writes — swallow silently to avoid false Unimplemented
+                // warnings on SPRs that have no observable effect in userspace.
+                crate::context::spr::SPRG0
+                | crate::context::spr::SPRG1
+                | crate::context::spr::SPRG2
+                | crate::context::spr::SPRG3
+                | crate::context::spr::HID0
+                | crate::context::spr::HID1
+                | crate::context::spr::DAR
+                | crate::context::spr::DSISR => {}
+                _ => {
+                    tracing::warn!("mtspr: unimplemented SPR {}", spr);
+                }
+            }
+            ctx.pc += 4;
+        }
+```
+</details>
+
+<!-- GENERATED: END -->
+
+## Special Cases & Edge Conditions
+
+- **SPR halves are swapped in the encoding.** As with [`mfspr`](mfspr.md), the 10-bit `spr` field stores the two 5-bit halves transposed. Software always names the *logical* SPR number; assemblers handle the swap. Decoded number `n = ((field & 0x1F) << 5) | ((field >> 5) & 0x1F)`.
+- **SPRs writable from userspace (Xenon, modelled by xenia).**
+
+  | Decoded # | Name      | Effect                                            |
+  | ---       | ---       | ---                                                |
+  | 1         | XER       | unpacked into `ctx.xer_so/xer_ov/xer_ca` and length field |
+  | 8         | LR        | `ctx.lr ← RS` |
+  | 9         | CTR       | `ctx.ctr ← RS` |
+  | 256       | VRSAVE    | `ctx.vrsave ← RS & 0xFFFFFFFF` |
+
+- **SPRs xenia silently swallows (no observable effect).** SPRG0..3, HID0, HID1, DAR, DSISR — these are kernel/diagnostic registers; xenia accepts the write to avoid spurious "unimplemented SPR" warnings, but the value is discarded.
+- **Privileged SPRs.** On real hardware, writes to MSR-visible kernel SPRs (SPRG0..3, HID0/1, DSISR, DAR, PIR, etc.) require supervisor mode and trap from problem state. xenia does **not** enforce privilege.
+- **Time-base writes are privileged.** `mtspr 268/269` (TBL/TBU) only works in supervisor mode on real hardware. xenia will warn `mtspr: unimplemented SPR` for these — do **not** assume the time base can be guest-written.
+- **Simplified mnemonics.** `mtxer RS` ≡ `mtspr 1, RS`, `mtlr RS` ≡ `mtspr 8, RS`, `mtctr RS` ≡ `mtspr 9, RS`. These dominate Xbox 360 disassembly.
+- **No CR / XER side effects.** `mtspr` itself doesn't record (the *target* SPR may itself be XER, in which case XER is being directly overwritten).
+- **Not synchronising.** xenia's XML omits the `sync` flag; PowerISA does require some `mtspr` cases (e.g. SDR1, MMU regs) to be context-synchronising — none of them appear in title binaries.
+
+## Related Instructions
+
+- [`mfspr`](mfspr.md) — inverse: read an SPR into a GPR.
+- [`mftb`](mftb.md) — read time-base (preferred over `mfspr TBL/TBU`).
+- [`mtmsr`](mtmsr.md), [`mtmsrd`](mtmsrd.md) — write MSR (separate opcode).
+- [`mcrxr`](mcrxr.md) — sample-and-clear XER's overflow/carry bits.
+
+### Simplified Mnemonics
+
+| Simplified  | Expansion         |
+| ---         | ---               |
+| `mtxer RS`  | `mtspr 1, RS`     |
+| `mtlr  RS`  | `mtspr 8, RS`     |
+| `mtctr RS`  | `mtspr 9, RS`     |
+
+## IBM Reference
+
+- [AIX 7.3 — `mtspr` (Move to Special Purpose Register)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-mtspr-move-special-purpose-register-instruction)
+- PowerISA v2.07B, Book III §4 — SPR number table and privilege rules.