chore: add migration/ bundle for cross-machine setup

Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:

  - claude-memory/             ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
                               (103 files, 1.1 MB - MEMORY.md + every
                                project_xenia_rs_*.md from audits
                                addis_signext through audit-058)
  - project-root/dot-claude/   <project-root>/.claude/settings.json
                               (Stop hook + permissions)
  - project-root/ppc-manual/   <project-root>/ppc-manual/
                               (PowerPC reference docs, 397 files, 3.7 MB)
  - project-root/run-canary.sh <project-root>/run-canary.sh
  - README.md                  Human-readable setup checklist
  - setup.sh                   Idempotent installer (also reclones
                               xenia-canary at pinned HEAD 6de80dffe)
  - MANIFEST.md                Per-file mapping + per-file-not-bundled
                               restoration recipe

Excluded from bundle (not shippable via git):
  - Sylpheed ISO (7.8 GB; copyright; manual copy required)
  - sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
  - target/ build artifacts (rebuild on target)
  - audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
  - audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
  - xenia-canary checkout (setup.sh reclones from
    git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

migration/project-root/ppc-manual/fpu/fmrx.md

@@ -0,0 +1,120 @@
+# `fmrx` — Floating Move Register
+
+> **Category:** [Floating-Point](../categories/fpu.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0xfc000090`
+
+<!-- GENERATED: BEGIN -->
+
+## Assembler Mnemonics
+
+| Mnemonic | XML entry | Flags | Description |
+| --- | --- | --- | --- |
+| `fmr` | `fmrx` | — | Floating Move Register |
+| `fmr.` | `fmrx` | Rc=1 | Floating Move Register |
+
+## Syntax
+
+```asm
+fmr[Rc] [FD], [FB]
+```
+
+## Encoding
+
+### `fmrx` — form `X`
+
+- **Opcode word:** `0xfc000090`
+- **Primary opcode (bits 0–5):** `63`
+- **Extended opcode:** `72`
+- **Synchronising:** no
+
+| Bits | Field | Meaning |
+| --- | --- | --- |
+| 0–5 | `OPCD` | primary opcode |
+| 6–10 | `RT/FRT/VRT` | destination |
+| 11–15 | `RA/FRA/VRA` | source A |
+| 16–20 | `RB/FRB/VRB` | source B |
+| 21–30 | `XO` | extended opcode (10 bits) |
+| 31 | `Rc` | record-form flag |
+
+## Operands
+
+| Field | Role | Description |
+| --- | --- | --- |
+| `FB` | fmrx: read | Source B floating-point register. |
+| `FD` | fmrx: write | Destination floating-point register. |
+| `CR` | fmrx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
+
+## Register Effects
+
+### `fmrx`
+
+- **Reads (always):** `FB`
+- **Reads (conditional):** _none_
+- **Writes (always):** `FD`
+- **Writes (conditional):** `CR`
+
+## Status-Register Effects
+
+- `fmrx`: **CR0** ← signed-compare(result, 0) with `SO ← XER[SO]`, when `Rc=1`.
+
+## Operation (pseudocode)
+
+```
+FRT <- FRB
+```
+
+## C Translation Example
+
+```c
+/* C translation: the xenia-rs interpreter arm below in           */
+/* Implementation References is the authoritative semantic        */
+/* snapshot. Translate it line-by-line:                            */
+/*   - ctx.gpr[N]  -> r[N]       (or f[]/v[] for FPRs/VRs)        */
+/*   - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be   */
+/*   - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v)   */
+/*   - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO   */
+/* The Register Effects and Status-Register Effects tables above  */
+/* enumerate every side effect a faithful translation must emit.  */
+```
+
+## Implementation References
+
+**`fmrx`**
+- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="fmrx"`](../../xenia-canary/tools/ppc-instructions.xml)
+- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:496`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L496)
+- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:28`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L28)
+- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:906`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L906)
+- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2752-2756`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2752-L2756)
+<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
+
+```rust
+        PpcOpcode::fmrx => {
+            ctx.fpr[instr.rd()] = ctx.fpr[instr.rb()];
+            if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
+            ctx.pc += 4;
+        }
+```
+</details>
+
+<!-- GENERATED: END -->
+
+## Special Cases & Edge Conditions
+
+- **Bit-pattern copy, no rounding.** `fmr` copies the 64-bit binary representation of `FRB` into `FRT` unchanged. No precision loss, no FPSCR exception bits, no NaN quietening. xenia-rs implements this as a plain `f64` copy.
+- **NaN preserved verbatim.** Signalling/quiet bit, payload, and sign are all preserved exactly. Unlike arithmetic instructions, `fmr` does **not** quieten signalling NaNs.
+- **Special values.** All bit patterns pass through untouched, including ±0, ±∞, and any NaN. The destination receives an exact copy.
+- **FPSCR.** Hardware does **not** update `FPRF` or any exception bit. The "FPSCR write" implied in the header refers only to `Rc=1` updating CR1 from existing FPSCR contents.
+- **`Rc=1` (`fmr.`)** copies `FPSCR[FX, FEX, VX, OX]` into CR1.
+- **No `FRA`.** X-form, primary 63, XO 72. Reads `FRB` only.
+- **Cheaper than load-store.** Compilers emit `fmr` for FPR-to-FPR moves; transferring a value via memory (`stfd`/`lfd`) would be far more expensive.
+
+## Related Instructions
+
+- [`fabsx`](fabsx.md), [`fnegx`](fnegx.md), [`fnabsx`](fnabsx.md) — sign-bit variants of the move (clear / toggle / set).
+- [`fselx`](fselx.md) — branch-free select; like a conditional `fmr`.
+- [`mffsx`](mffsx.md) — read FPSCR into an FPR; complementary "FPR move" for a control register.
+- `stfd`/`lfd` — memory-mediated FPR transfer (much slower; used for register window spills).
+
+## IBM Reference
+
+- [AIX 7.3 — `fmr` (Floating Move Register)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-fmr-floating-move-register-instruction)
+- [PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor](https://openpowerfoundation.org/specifications/isa/) (move-class instructions explicitly bypass quietening and FPSCR side effects).