chore: add migration/ bundle for cross-machine setup
Bundles state that lives OUTSIDE the xenia-rs repo so a fresh clone on
another machine can be brought up to identical configuration via
migration/setup.sh:
- claude-memory/ ~/.claude/projects/-home-fabi-RE-Project-Sylpheed/memory/
(103 files, 1.1 MB - MEMORY.md + every
project_xenia_rs_*.md from audits
addis_signext through audit-058)
- project-root/dot-claude/ <project-root>/.claude/settings.json
(Stop hook + permissions)
- project-root/ppc-manual/ <project-root>/ppc-manual/
(PowerPC reference docs, 397 files, 3.7 MB)
- project-root/run-canary.sh <project-root>/run-canary.sh
- README.md Human-readable setup checklist
- setup.sh Idempotent installer (also reclones
xenia-canary at pinned HEAD 6de80dffe)
- MANIFEST.md Per-file mapping + per-file-not-bundled
restoration recipe
Excluded from bundle (not shippable via git):
- Sylpheed ISO (7.8 GB; copyright; manual copy required)
- sylpheed.db (395 MB; regenerable from XEX via analysis tooling)
- target/ build artifacts (rebuild on target)
- audit-runs probe firehoses (.log/.stdout/.stderr ~11 GB; rerun if needed)
- audit-runs memory dumps (.bin ~4.5 GB; rerun audit-026/027/029 if needed)
- xenia-canary checkout (setup.sh reclones from
git.mc02.dev/fabi/Xenia-Canary.git at HEAD 6de80dffe)
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
MechaCat02
147
migration/project-root/ppc-manual/fpu/fnmaddsx.md
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migration/project-root/ppc-manual/fpu/fnmaddsx.md
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# `fnmaddsx` — Floating Negative Multiply-Add Single
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> **Category:** [Floating-Point](../categories/fpu.md) · **Form:** [A](../forms/A.md) · **Opcode:** `0xec00003e`
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<!-- GENERATED: BEGIN -->
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## Assembler Mnemonics
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| Mnemonic | XML entry | Flags | Description |
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| --- | --- | --- | --- |
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| `fnmadds` | `fnmaddsx` | — | Floating Negative Multiply-Add Single |
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| `fnmadds.` | `fnmaddsx` | Rc=1 | Floating Negative Multiply-Add Single |
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## Syntax
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```asm
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fnmadds[Rc] [FD], [FA], [FC], [FB]
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```
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## Encoding
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### `fnmaddsx` — form `A`
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- **Opcode word:** `0xec00003e`
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- **Primary opcode (bits 0–5):** `59`
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- **Extended opcode:** `31`
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- **Synchronising:** no
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| Bits | Field | Meaning |
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| --- | --- | --- |
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| 0–5 | `OPCD` | primary opcode (59 or 63) |
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| 6–10 | `FRT` | destination FPR |
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| 11–15 | `FRA` | source A FPR |
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| 16–20 | `FRB` | source B FPR |
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| 21–25 | `FRC` | source C FPR (multiplier for madd-style ops) |
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| 26–30 | `XO` | extended opcode (5 bits) |
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| 31 | `Rc` | record-form flag (updates CR1) |
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## Operands
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| Field | Role | Description |
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| --- | --- | --- |
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| `FA` | fnmaddsx: read | Source A floating-point register (`fr0`–`fr31`). |
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| `FC` | fnmaddsx: read | Source C floating-point register (for madd-style ops). |
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| `FB` | fnmaddsx: read | Source B floating-point register. |
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| `FD` | fnmaddsx: write | Destination floating-point register. |
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| `CR` | fnmaddsx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
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| `FPSCR` | fnmaddsx: write | Floating-Point Status and Control Register. |
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## Register Effects
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### `fnmaddsx`
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- **Reads (always):** `FA`, `FC`, `FB`
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- **Reads (conditional):** _none_
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- **Writes (always):** `FD`, `FPSCR`
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- **Writes (conditional):** `CR`
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## Status-Register Effects
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- `fnmaddsx`: **CR1** ← FPSCR[FX, FEX, VX, OX] when `Rc=1`.; **FPSCR** updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).
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## Operation (pseudocode)
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```
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; Pseudocode derives directly from the xenia-rs interpreter
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; arm (see Implementation References). Operation semantics:
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; - Read source operands from the fields listed under Operands.
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; - Apply the arithmetic / logical / memory action described
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; in the Description field above.
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; - Write results to the destination register(s); update any
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; status bits enumerated under Status-Register Effects.
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; Consult the IBM AIX reference link under IBM Reference for
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; canonical PPC-style pseudocode where xenia's expression is
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; terse.
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```
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## C Translation Example
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```c
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/* C translation: the xenia-rs interpreter arm below in */
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/* Implementation References is the authoritative semantic */
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/* snapshot. Translate it line-by-line: */
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/* - ctx.gpr[N] -> r[N] (or f[]/v[] for FPRs/VRs) */
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/* - mem.read_u*/write_u* -> mem_read_u*_be / mem_write_u*_be */
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/* - ctx.update_cr_signed(fld, v) -> update_cr_signed(fld, v) */
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/* - ctx.xer_ca / xer_ov / xer_so -> xer.CA / xer.OV / xer.SO */
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/* The Register Effects and Status-Register Effects tables above */
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/* enumerate every side effect a faithful translation must emit. */
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```
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## Implementation References
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**`fnmaddsx`**
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- xenia-canary XML: [`tools/ppc-instructions.xml` — search for `mnem="fnmaddsx"`](../../xenia-canary/tools/ppc-instructions.xml)
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- xenia-canary emit: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:222`](../../xenia-canary/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L222)
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- xenia-rs opcode: [`crates/xenia-cpu/src/opcode.rs:29`](../../xenia-rs/crates/xenia-cpu/src/opcode.rs#L29)
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- xenia-rs decoder: [`crates/xenia-cpu/src/decoder.rs:395`](../../xenia-rs/crates/xenia-cpu/src/decoder.rs#L395)
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- xenia-rs interpreter: [`crates/xenia-cpu/src/interpreter.rs:2706-2720`](../../xenia-rs/crates/xenia-cpu/src/interpreter.rs#L2706-L2720)
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<details><summary>xenia-rs interpreter body (frozen snapshot)</summary>
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```rust
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PpcOpcode::fnmaddsx => {
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// PPCBUG-181 + PPCBUG-183: VXISI + NaN sign preservation.
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let a = ctx.fpr[instr.ra()];
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let c = ctx.fpr[instr.rc()];
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let b = ctx.fpr[instr.rb()];
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fpscr::check_invalid_mul(ctx, a, c);
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fpscr::check_invalid_fma_add(ctx, a, c, b, false);
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let fma = a.mul_add(c, b);
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let neg = if fma.is_nan() { fma } else { -fma };
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let result = to_single(ctx, neg);
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ctx.fpr[instr.rd()] = result;
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fpscr::update_after_op(ctx, result, a.is_finite() && b.is_finite() && c.is_finite());
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if instr.rc_bit() { update_cr1_from_fpscr(ctx); }
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ctx.pc += 4;
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}
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```
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</details>
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<!-- GENERATED: END -->
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## Special Cases & Edge Conditions
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- **Single rounding then negate then round-to-single.** Computes `−((FRA × FRC) + FRB)` and rounds to binary32. xenia-rs uses `to_single(-(a.mul_add(c, b)))` — the negation is a sign-flip on the binary64 intermediate, then `to_single` rounds to binary32.
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- **NaN sign behaviour.** PowerISA specifies the negation does **not** flip the sign bit of a NaN result. xenia uses Rust's `Neg`, which does flip the NaN sign bit. Observable only via bit-level inspection. **xenia quirk.**
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- **Operand order.** Assembler: `FD, FA, FC, FB`.
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- **Invalid operations.** `0×∞` → `VXIMZ`; opposing-infinity collision → `VXISI`. Quiet NaN result with `FPSCR[VX, FX]`.
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- **FPSCR side effects.** Hardware updates `FPRF`, `FR`, `FI`, `FX`, `OX`, `UX`, `XX`, `VXIMZ`, `VXISI`, `VXSNAN`. xenia-rs does not (xenia quirk).
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- **`Rc=1` (`fnmadds.`)** copies `FPSCR[FX, FEX, VX, OX]` into CR1.
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- **NaN propagation.** Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
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- **Single-precision overflow** returns ±∞ and sets `OX`/`XX`/`FX`.
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- **Use case.** Single-precision Newton-Raphson refinement and graphics-pipeline math where the negated product-sum form is convenient.
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- **Denormal flush.** Xenon boots with `FPSCR[NI]=1`; xenia uses host IEEE behavior.
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## Related Instructions
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- [`fnmaddx`](fnmaddx.md) — double-precision sibling.
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- [`fmaddsx`](fmaddsx.md), [`fmsubsx`](fmsubsx.md), [`fnmsubsx`](fnmsubsx.md) — other single-precision fused-multiply variants.
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- [`fmulsx`](fmulsx.md), [`faddsx`](faddsx.md) — non-fused decomposition.
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- [`fnegx`](fnegx.md), [`fnabsx`](fnabsx.md) — sign-bit ops.
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- [`frspx`](frspx.md) — explicit double→single rounding.
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## IBM Reference
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- [AIX 7.3 — `fnmadds` (Floating Negative Multiply-Add Single)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-fnmadds-floating-negative-multiply-add-single-instruction)
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- [PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor](https://openpowerfoundation.org/specifications/isa/).
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